A low power 6T-4C non-volatile memory using charge sharing and …
This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to …
Abstract—This report describes a low power 6T-4C non-volatile memory design using a bit-line nonprecharge and - plate-line charge-share techniques. Two proposed techniques …
A low power 6T-4C non-volatile memory using charge sharing and …
May 1, 2015 · To reduce this amount of power loss and achieve power efficient memory, we propose a new SRAM design that integrates charge pump circuits to harvest and reuse bit …
A low power 6T-4C non-volatile memory using charge sharing and …
Fig. 4. Schematic of bit-line with (a) precharger, (b) equalizer. - "A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques"
A Survey of Emerging Memory in a Microcontroller …
Feb 29, 2024 · In addition, innovative plate-line charge-share and bit-line non-precharge techniques effectively mitigate the active power dissipation from the large Fecap, making the 6T-4C macro suitable for an electrocardiograph …
A low power 6T-4C non-volatile memory using charge sharing and …
Two proposed techniques contribute to decrease energy consumption. The bit-line nonprecharge technique can reduce 73% of write energy consumption and 76% of read …
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Low-voltage ultrafast nonvolatile memory via direct charge ...
Aug 6, 2022 · Here, Chen et al. demonstrate operation speed of 20 ns and power consumption of 10 fJ using graphdiyne oxide as a threshold switching layer instead of a dielectric blocking layer.
Design and Performance Evaluation of a Non-Volatile Hybrid 6T …
This work proposes a non-volatile hybrid 6T-4MTJ SRAM bit cell based on 32-nanometer technology and shows it's comparison with a conventional 6T SRAM bit cell to evaluate the …
RRAM-based non-volatile SRAM cell architectures for …
Jan 24, 2020 · This paper compares three NVSRAM cells, including 6T2R, 10T1R and 8T1R cells. All structures are based on the traditional 6T SRAM and implemented in 130-nm technology. TGs are added to 6T2R and 10T1R …
(PDF) A 6.14μA normally-off ECG-SoC with noise tolerant heart …
Dec 9, 2014 · Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate …