MIPS

MIPS P8700 processors are redefining performance, scalability, and safety for next generation #ADAS and autonomous driving #SoCs. P8700 clusters deliver high throughput real-time response with ASIL-B functional safety, enabling automakers and chip developers to scale efficiently from Level 1 to Level 5 autonomy. With support for simultaneous multithreading, advanced I/O coherence, and a scalable multi-core architecture, the P8700 is built to keep complex automotive workloads safe and efficient. Learn more in our whitepaper.

Attending SPS in Nuremberg, Germany? Stop by booth 429 in Hall 6 to explore how MIPS innovative RISC-V processor IP is powering the future of Physical AI, and real-time data orchestration across automotive, industrial, and communications industries. #PhysicalAI #SPS

The MIPS I8500 is a best-in-class match-action processor purpose-built for the Physical AI era, where sensing, thinking, acting, and communicating converge in real time. Watch the video to learn more. #PhysicalAI

Since the evolution of “System on Chip”, processors have arguably been heterogeneous; multiple ISAs that enable the programming of different hardware blocks. RISC-V provides a modular and extensible way to build these blocks, with an open collaborative framework that enables contributions from all. MIPS Atlas portfolio of RISC-V IP is focused on Physical AI workloads: Sense, Think, Act, Communicate. These are the building blocks of the next wave of autonomous platforms as AI leaves the data center and enters the physical world. #Innovation #PhysicalAI #RISCV #MIPS

At embedded world Exhibition&Conference, Mark Throndson spoke on “Networking Native RISC-V Processor for the Datacenter,” discussing several optimizations that can be achieved within a standard RISC-V solution that tailor the implementation to networking. He highlighted the multi-threaded, award-winning MIPS I8500, which implements a big-endian-native CPU and compute cluster, allowing for packet header and payload data to be natively processed in network byte order, removing the overhead of performing any byte swizzling within hardware gates or in software instructions. To learn more about the I8500, view the data sheet and programmer’s guide below in the comments. #EW2025 #RISCV

MIPS Sean Murphy took the stage at embedded world Exhibition&Conference sharing how MIPS is creating RISC-V custom instructions to accelerate real-rime applications. He unveiled a novel solution for accelerating real-time motor control algorithms using a MIPS defined trigonometric math custom instruction extension. This enables faster, more precise, energy-efficient motors, ideal for robotics, automation, electric vehicles, and future AI systems. Stop by booth 2009 to meet Sean and the rest of the team! #EW2025 

Today the MIPS I8500 won Embedded Computing Design’s Best in Show Award for Microcontrollers, Microprocessors, and IP at embedded world Exhibition&Conference! Stop by booth 2009 to meet the MIPS team and learn more about our RISC-V IP processors that Sense, Think, Act, and Communicate, the essential technology stack for Physical AI. #EW2025 #PhysicalAI Sean Murphy, Derry Murphy, Takuya Katayama, Mark Throndson, James Prior.

Attending RHET?  We hope to see you at the MIPS sponsored welcome reception at the Radiation Hardened Electronic Technologies Meeting tomorrow at the Albany Hilton. Mingle with MIPS representatives and learn more about the technologies shaping the future of Physical AI. #RHET

Come see us - I'll be there