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Working Control

The document describes a VHDL implementation of a control unit for a digital system. It defines the entity with various input and output ports, as well as a state machine that transitions through multiple states to manage operations like loading data and controlling memory. The architecture includes processes for state registration and next state logic, detailing the behavior of the control signals based on the current state.

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65 views3 pages

Working Control

The document describes a VHDL implementation of a control unit for a digital system. It defines the entity with various input and output ports, as well as a state machine that transitions through multiple states to manage operations like loading data and controlling memory. The architecture includes processes for state registration and next state logic, detailing the behavior of the control signals based on the current state.

Uploaded by

A_B_C_D_Z
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.

all; entity control is port (Funct : out std_logic_vector ( 2 downto 0 ); ld_x : out std_logic; ld_y : out std_logic; clk, reset : in std_logic; Aludrive, W_R, MEMDRIVE : out std_logic; Address : out std_logic_vector ( 7 downto 0 ); MAINBUS : in std_logic_vector ( 7 downto 0 )); end control; architecture Behav of control is type states is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10); signal state, next_state : states; signal PC: std_logic_vector (7 downto 0); begin state_register : process (clk, reset) begin if (reset = '1') then state <= S0; elsif ( clk'event and clk = '1' ) then state <= next_state; end if; end process; next_state_logic : process (state) begin case state is when S0 => next_state <= S1; when S1 => next_state<= S2; when S2 => next_state <= S3; when S3 => next_state<= S4; when S4 => next_state<= S5; when S5 => next_state<= S6; when S6 => next_state<= S7; when S7=> next_state<=S8; when S8=> next_state<=S9; when S9=> next_state<=S10; when S10=> next_state<=S1; end case; end process;

Dataflow : process (clk) --variable opcode: std_logic_vector(2 downto 0); begin if( clk'event and clk = '1' ) then case state is when S0=> PC<="00000000"; Address<="00000000"; W_R <= '0'; MEMDRIVE<='1'; ld_x<='0'; ld_y<='0'; Aludrive<='0'; Funct<="000"; when S1=> W_R<='0'; Address <= PC ; MEMDRIVE<='1'; PC<= PC+1; when S2=> ld_x<='1'; when S3=> Address<=PC; MEMDRIVE<='1'; W_R <= '0'; PC<= PC+1; ld_x<='0'; when S4=> ld_y<='1'; when S5=> ld_x<='0'; ld_y<='0'; W_R <= '0'; MEMDRIVE<='1'; Address<=PC; PC<=PC+1; when S6=> Address<=PC-3; when S7=> Funct<=MAINBUS(2 downto 0); when S8=> MEMDRIVE<='0'; Aludrive<='1'; WHEN S9=> W_R<='1'; when S10=> W_R<='0'; MEMDRIVE<='0'; ld_x<='0'; ld_y<='0'; Aludrive<='0';

end case; end if; end process; end Behav;

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