1

POWER MOSFETS
INTRODUCTION TO FETS
FETs use field effect for their operation. FET is manufactured by diffusing two
areas of p-type into the n-type semiconductor as shown. Each p-region is connected to a
gate terminal; the gate is a p-region while source and drain are n-region. Since it is similar
to two diodes one is a gate source diode and the other is a gate drain diode.
Fig:1: Schematic symbol of JFET
Fig. 2: Structure of FET with biasing
In BJTs we forward bias the B-E diode but in a JFET, we always reverse bias the
gate-source diode. Since only a small reverse current can exist in the gate lead. Therefore
0
G
I = , therefore , )
in
R ideal = .
The term field effect is related to the depletion layers around each p-region as
shown. When the supply voltage
DD
V is applied as shown it forces free electrons to flow
2
from source to drain. With gate reverse biased, the electrons need to flow from source to
drain, they must pass through the narrow channel between the two depletion layers. The
more the negative gate voltage is the tighter the channel becomes.
Therefore JFET acts as a voltage controlled device rather than a current controlled
device.
JFET has almost infinite input impedance but the price paid for this is loss of
control over the output current, since JFET is less sensitive to changes in the output
voltage than a BJT.
JFET CHARACTERISTICS
3
The maximum drain current out of a JFET occurs when 0
GS
V = . As
DS
V is
increased for 0 to a few volts, the current will increase as determined by ohms law. As
DS
V approaches
P
V the depletion region will widen, carrying a noticeable reduction in
channel width. If
DS
V is increased to a level where the two depletion region would touch a
pinch-off will result.
D
I now maintains a saturation level
DSS
I . Between 0 volts and
pinch off voltage
P
V is the ohmic region. After
P
V , the regions constant current or active
region.
If negative voltage is applied between gate and source the depletion region similar
to those obtained with 0
GS
V = are formed but at lower values of
DS
V . Therefore
saturation level is reached earlier.
We can find two important parameters from the above characteristics
-
ds
r = drain to source resistance =
DS
D
V
I
A
A
.
-
m
g = transconductance of the device =
D
GS
I
V
A
A
.
- The gain of the device, amplification factor
ds m
r g = .
4
SHOCKLEY EQUATION
The FET is a square law device and the drain current
D
I is given by the Shockley
equation
2
1
GS
D DSS
P
V
I I
V
| |
=
|
\ .
and 1
D
GS P
DSS
I
V V
I
| |
=
|
|
\ .
MOSFET
MOSFET stands for metal oxide semiconductor field effect transistor. There are
two types of MOSFET
- Depletion type MOSFET
- Enhancement type MOSFET
DEPLETION TYPE MOSFET
CONSTRUCTION
Symbol of n-channel depletion type MOSFET
It consists of a highly doped p-type substrate into which two blocks of heavily
doped n-type material are diffused to form a source and drain. A n-channel is formed by
diffusing between source and drain. A thin layer of
2
SiO is grown over the entire surface
and holes are cut in
2
SiO to make contact with n-type blocks. The gate is also connected
to a metal contact surface but remains insulated from the n-channel by the
2
SiO
layer.
2
SiO layer results in an extremely high input impedance of the order of
10
10 to
15
10 O for this area.
5
Fig. 4: Structure of n-channel depletion type MOSFET
OPERATION
When 0
GS
V V = and
DS
V is applied and current flows from drain to source similar
to JFET. When 1
GS
V V = , the negative potential will tend to pressure electrons towards
the p-type substrate and attracts hole from p-type substrate. Therefore recombination
occurs and will reduce the number of free electrons in the n-channel for conduction.
Therefore with increased negative gate voltage
D
I reduces.
For positive values,
gs
V , additional electrons from p-substrate will flow into the
channel and establish new carriers which will result in an increase in drain current with
positive gate voltage.
DRAIN CHARACTERISTICS
6
TRANSFER CHARACTERISTICS
ENHANCEMENT TYPE MOSFET
Here current control in an n-channel device is now affected by positive gate to
source voltage rather than the range of negative voltages of JFETs and depletion type
MOSFET.
BASIC CONSTRUCTION
A slab of p-type material is formed and two n-regions are formed in the substrate.
The source and drain terminals are connected through metallic contacts to n-doped
regions, but the absence of a channel between the doped n-regions. The
2
SiO layer is still
present to isolate the gate metallic platform from the region between drain and source, but
now it is separated by a section of p-type material.
Fig. 5: Structure of n-channel enhancement type MOSFET
7
OPERATION
If 0
GS
V V = and a voltage is applied between the drain and source, the absence of a
n-channel will result in a current of effectively zero amperes. With
DS
V set at some
positive voltage and
GS
V set at 0V, there are two reverse biased p-n junction between the
n-doped regions and p substrate to oppose any significant flow between drain and source.
If both
DS
V and
GS
V have been set at some positive voltage, then positive potential
at the gate will pressure the holes in the p-substrate along the edge of
2
SiO layer to leave
the area and enter deeper region of p-substrate. However the electrons in the p-substrate
will be attracted to the positive gate and accumulate in the region near the surface of the
2
SiO layer. The negative carriers will not be absorbed due to insulating
2
SiO layer,
forming an inversion layer which results in current flow from drain to source.
The level of
GS
V that results in significant increase in drain current is called
threshold voltage
T
V . As
GS
V increases the density of free carriers will increase resulting
in increased level of drain current. If
GS
V is constant
DS
V is increased; the drain current
will eventually reach a saturation level as occurred in JFET.
DRAIN CHARACTERISTICS
8
TRANSFER CHARACTERISTICS
POWER MOSFETS
Power MOSFETs are generally of enhancement type only. This MOSFET is
turned ON when a voltage is applied between gate and source. The MOSFET can be
turned OFF by removing the gate to source voltage. Thus gate has control over the
conduction of the MOSFET. The turn-on and turn-off times of MOSFETs are very small.
Hence they operate at very high frequencies; hence MOSFETs are preferred in
applications such as choppers and inverters. Since only voltage drive (gate-source) is
required, the drive circuits of MOSFET are very simple. The paralleling of MOSFETs is
easier due to their positive temperature coefficient. But MOSFTSs have high on-state
resistance hence for higher currents; losses in the MOSFETs are substantially increased.
Hence MOSFETs are used for low power applications.
CONSTRUCTION
Source
Gate
J
3
Drain
p
-
p
-
n
+
n
+ n
+
n
-
n
+
Source
Metal layer
n
-
n
+
substrate
Load
V
DD
n
+
Current path
-
-
-
-
-
-
-
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
V
GS
Silicon
dioxide
Metal
9
Power MOSFETs have additional features to handle larger powers. On the
n
+
substrate high resistivity n

layer is epitaxially grown. The thickness of n

layer
determines the voltage blocking capability of the device. On the other side of n
+
substrate,
a metal layer is deposited to form the drain terminal. Now p

regions are diffused in the

epitaxially grown n

layer. Further n
+
regions are diffused in the p

regions as shown.
2
SiO layer is added, which is then etched so as to fit metallic source and gate terminals.
A power MOSFET actually consists of a parallel connection of thousands of basic
MOSFET cells on the same single chip of silicon.
When gate circuit voltage is zero and
DD
V is present, n p
+
junctions are reverse
biased and no current flows from drain to source. When gate terminal is made positive
with respect to source, an electric field is established and electrons from n

channel in the
p

regions. Therefore a current from drain to source is established.

Power MOSFET conduction is due to majority carriers therefore time delays
caused by removal of recombination of minority carriers is removed.
Because of the drift region the ON state drop of MOSFET increases. The
thickness of the drift region determines the breakdown voltage of MOSFET. As seen a
parasitic BJT is formed, since emitter base is shorted to source it does not conduct.
SWITCHING CHARACTERISTICS
The switching model of MOSFETs is as shown in the figure 6(a). The various
inter electrode capacitance of the MOSFET which cannot be ignored during high
frequency switching are represented by , &
gs gd ds
C C C . The switching waveforms are as
shown in figure 7 . The turn on time
d
t is the time that is required to charge the input
capacitance to the threshold voltage level. The rise time
r
t is the gate charging time from
this threshold level to the full gate voltage
gsp
V . The turn off delay time
doff
t is the time
required for the input capacitance to discharge from overdriving the voltage
1
V to the
pinch off region. The fall time is the time required for the input capacitance to discharge
from pinch off region to the threshold voltage. Thus basically switching ON and OFF
depend on the charging time of the input gate capacitance.
10
Fig.6: Switching model of MOSFET
Fig.7: Switching waveforms and times of Power MOSFET
GATE DRIVE
The turn-on time can be reduced by connecting a RC circuit as shown to charge
the capacitance faster. When the gate voltage is turned on, the initial charging current of
the capacitance is
G
G
S
V
I
R
= .
The steady state value of gate voltage is
1
G G
GS
S G
R V
V
R R R
=
+ +
.
Where
S
R is the internal resistance of gate drive force.
11
Gate Signal
V
G
C
1
+
-
R
S
R
1
R
G
R
D
V
DD
I
D
+
-
Fig. 8: Fast turn on gate drive circuit
COMPARISON OF MOSFET WITH BJT
- Power MOSFETS have lower switching losses but its on-resistance and
conduction losses are more. A BJT has higher switching loss bit lower conduction
loss. So at high frequency applications power MOSFET is the obvious choice. But
at lower operating frequencies BJT is superior.
- MOSFET has positive temperature coefficient for resistance. This makes parallel
operation of MOSFETs easy. If a MOSFET shares increased current initially, it
heats up faster, its resistance increases and this increased resistance causes this
current to shift to other devices in parallel. A BJT is a negative temperature
coefficient, so current shaving resistors are necessary during parallel operation of
BJTs.
- In MOSFET secondary breakdown does not occur because it have positive
temperature coefficient. But BJT exhibits negative temperature coefficient which
results in secondary breakdown.
- Power MOSFETs in higher voltage ratings have more conduction losses.
- Power MOSFETs have lower ratings compared to BJTs . Power MOSFETs
500V to 140A, BJT 1200V, 800A.
12
MOSIGT OR IGBT
The metal oxide semiconductor insulated gate transistor or
IGBT combines the advantages of BJTs and MOSFETs.
Therefore an IGBT has high input impedance like a MOSFET
and low-on state power loss as in a BJT. Further IGBT is free
from second breakdown problem present in BJT.
IGBT BASIC STRUCTURE AND WORKING
Emitter
Gate
J
3
J
2
J
1
Collector
p
p
n
+
n
+ n
+
n
-
p substrate
+
Emitter
E G
Metal
Silicon
dioxide
Metal layer
C
n
-
p
+
Load
V
CC
n
+
Current path
-
-
-
-
-
-
-
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
V
G
It is constructed virtually in the same manner as a power MOSFET. However, the
substrate is now a p
+
layer called the collector.
When gate is positive with respect to positive with respect to emitter and with gate
emitter voltage greater than
GSTH
V , an n channel is formed as in case of power MOSFET.
This n

channel short circuits the n

region with n
+
emitter regions.
An electron movement in the n

channel in turn causes substantial hole injection

from p
+
substrate layer into the epitaxially n

layer. Eventually a forward current is

established.
13
The three layers p
+
, n

and p constitute a pnp transistor with p

+
as emitter, n

as base and p as collector. Also n

, p and n
+
layers constitute a npn transistor. The
MOSFET is formed with input gate, emitter as source and n

region as drain. Equivalent

circuit is as shown below.
E
G
J
3
J
2
J
1
C
pnp
npn
p
n
+
n
+
n
+
n
+
n
-
p substrate
+
S
G
D
14
Also p serves as collector for pnp device and also as base for npn transistor. The
two pnp and npn is formed as shown.
When gate is applied , )
GS GSth
V V > MOSFET turns on. This gives the base drive to
1
T . Therefore
1
T starts conducting. The collector of
1
T is base of
2
T . Therefore
regenerative action takes place and large number of carriers are injected into the n

drift
region. This reduces the ON-state loss of IGBT just like BJT.
When gate drive is removed IGBT is turn-off. When gate is removed the induced
channel will vanish and internal MOSFET will turn-off. Therefore
1
T will turn-off it
2
T turns off.
Structure of IGBT is such that
1
R is very small. If
1
R small
1
T will not conduct
therefore IGBTs are different from MOSFETs since resistance of drift region reduces
when gate drive is applied due to p
+
injecting region. Therefore ON state IGBT is very
small.
IGBT CHARACTERISTICS
STATIC CHARACTERISTICS
Fig. 9: IGBT bias circuit
Static V-I characteristics (
C
I versus
CE
V )
Same as in BJT except control is by
GE
V . Therefore IGBT is a voltage controlled
device.
Transfer Characteristics (
C
I versus
GE
V )
Identical to that of MOSFET. When
GE GET
V V < , IGBT is in off-state.
15
APPLICATIONS
Widely used in medium power applications such as DC and AC motor drives,
UPS systems, Power supplies for solenoids, relays and contractors.
Though IGBTs are more expensive than BJTs, they have lower gate drive
requirements, lower switching losses. The ratings up to 1200V, 500A.
SERIES AND PARALLEL OPERATION
Transistors may be operated in series to increase their voltage handling capability.
It is very important that the series-connected transistors are turned on and off
simultaneously. Other wise, the slowest device at turn-on and the fastest devices at turn-
off will be subjected to the full voltage of the collector emitter circuit and the particular
device may be destroyed due to high voltage. The devices should be matched for gain,
transconductance, threshold voltage, on state voltage, turn-on time, and turn-off time.
Even the gate or base drive characteristics should be identical.
Transistors are connected in parallel if one device cannot handle the load current
demand. For equal current sharings, the transistors should be matched for gain,
transconductance, saturation voltage, and turn-on time and turn-off time. But in practice,
it is not always possible to meet these requirements. A reasonable amount of current
sharing (45 to 55% with two transistors) can be obtained by connecting resistors in series
with the emitter terminals as shown in the figure 10.
Fig. 10: Parallel connection of Transistors
16
The resistor will help current sharing under steady state conditions. Current
sharing under dynamic conditions can be accomplished by connecting coupled inductors.
If the current through
1
Q rises, the , ) l di dt across
1
L increases, and a corresponding
voltage of opposite polarity is induced across inductor
2
L . The result is low impedance
path, and the current is shifted to
2
Q . The inductors would generate voltage spikes and
they may be expensive and bulky, especially at high currents.
Fig. 11: Dynamic current sharing
BJTs have a negative temperature coefficient. During current sharing, if one BJT
carries more current, its on-state resistance decreases and its current increases further,
whereas MOSFETS have positive temperature coefficient and parallel operation is
relatively easy. The MOSFET that initially draws higher current heats up faster and its
on-state resistance increases, resulting in current shifting to the other devices. IGBTs
require special care to match the characteristics due to the variations of the temperature
coefficients with the collector current.
PROBLEM
1. Two MOSFETS which are connected in parallel carry a total current of 20
T
I A = .
The drain to source voltage of MOSFET
1
M is
1
2.5
DS
V V = and that of MOSFET
2
M is
2
3
DS
V V = . Determine the drain current of each transistor and difference in
current sharing it the current sharing series resistances are (a)
1
0.3
s
R = O and
2
0.2
s
R = O, and (b)
1 2
0.5
s s
R R = = O.
Solution
(a) , )
1 2 1 1 1 2 2 2 2
&
D D T DS D s DS D s s T D
I I I V I R V I R R I I + = + = + =
2 1 2
1
1 2
1
2
3 2.5 20 0.2
9 45%
0.3 0.2
20 9 11 55%
55 45 10%
DS DS T s
D
s s
D
D
V V I R
I
R R
I A or
I A or
I
+
=
+
+
= =
+
= =
A = =
17
(b)
1
3 2.5 20 0.5
10.5 52.5%
0.5 0.5
D
I A or
+
= =
+
2
20 10.5 9.5 47.5%
52.5 47.5 5%
D
I A or
I
= =
A = =
di dt AND dv dt LIMITATIONS
Transistors require certain turn-on and turn-off times. Neglecting the delay time
d
t and the storage time
s
t , the typical voltage and current waveforms of a BJT switch is
shown below.
During turn-on, the collector rise and the di dt is
...(1)
cs L
r r
I I di
dt t t
= =
During turn off, the collector emitter voltage must rise in relation to the fall of the
collector current, and is
...(2)
s cc
f f
V V dv
dt t t
= =
The conditions di dt and dv dt in equation (1) and (2) are set by the transistor
switching characteristics and must be satisfied during turn on and turn off. Protection
circuits are normally required to keep the operating di dt and dv dt within the allowable
limits of transistor. A typical switch with di dt and dv dt protection is shown in figure
(a), with operating wave forms in figure (b). The RC network across the transistor is
known as the snubber circuit or snubber and limits the dv dt . The inductor
S
L , which
limits the di dt , is sometimes called series snubber.
18
Let us assume that under steady state conditions the load current
L
I is free
wheeling through diode
m
D , which has negligible reverse reco`very time. When
transistor
1
Q is turned on, the collector current rises and current of diode
m
D falls, because
m
D will behave as short circuited. The equivalent circuit during turn on is shown in figure
below
The turn on di dt is
...(3)
s
s
V di
dt L
=
Equating equations (1) and (3) gives the value of
s
L
...(4)
s r
s
L
V t
L
I
=
During turn off, the capacitor
s
C will charge by the load current and the equivalent
circuit is shown in figure (4). The capacitor voltage will appear across the transistor and
the dv dt is
...(5)
L
s
I dv
dt C
=
Equating equation (2) to equation (5) gives the required value of capacitance,
...(6)
L f
s
s
I t
C
V
=
19
Once the capacitor is charge to
s
V , the freewheeling diode will turn on. Due to the
energy stored in
s
L , there will be damped resonant circuit as shown in figure (5). The
RLC circuit is normally made critically damped to avoid oscillations. For unity critical
damping, 1 = , and equation
0
2
R C
L

= = yields
2
s
s
s
L
R
C
=
The capacitor
s
C has to discharge through the transistor and the increase the peak
current rating of the transistor. The discharge through the transistor can be avoided by
placing resistor
s
R across
s
C instead of placing
s
R across
s
D .
The discharge current is shown in figure below. When choosing the value of
s
R ,
the discharge time,
s s s
R C = should also be considered. A discharge time of one third the
switching period,
s
T is usually adequate.
1
3
1
3
s s s
s
s
s s
R C T
f
R
f C
= =
=
ISOLATION OF GATE AND BASE DRIVES
Necessity
Driver circuits are operated at very low power levels. Normally the gating circuit
are digital in nature which means the signal levels are 3 to 12 volts. The gate and base
drives are connected to power devices which operate at high power levels.
Illustration
The logic circuit generates four pulses; these pulses have common terminals. The
terminal g , which has a voltage of
G
V , with respect to terminal C , cannot be connected
directly to gate terminal G , therefore
1 g
V should be applied between
1 1
& G S of transistor
1
Q . Therefore there is need for isolation between logic circuit and power transistor.
+
-
V
S
G
3
G
2
S
3
S
2
M
2
R
L
M
3
M
1
S
1
G
1
M
4
G
S
4
G
4
C
Logic
generator
G
1
G
1
G
2
G
3
G
4
g
1
g
2
g
3
g
4
(a) Circuit arrangement
(b) Logic generator
20
Gate pulses
0
V
G
0
V
G
V V
g3, g4
V V
g1, g2
t
V
Gs
S
D I
D
V
G
G
V
DD
+
-
R =R
D L
G
+
-
There are two ways of floating or isolating control or gate signal with respect to
ground.
- Pulse transformers
- Optocouplers
PULSE TRANSFORMERS
Pulse transformers have one primary winding and can have one or more secondary
windings.
Multiple secondary windings allow simultaneous gating signals to series and
parallel connected transistors. The transformer should have a very small leakage
inductance and the rise time of output should be very small.
The transformer would saturate at low switching frequency and output would be
distorted.
21
V
1
-V
2
0
Logic
drive
circuit
Q
1
I
C
R
C
+
-
V
CC
R
B
OPTOCOUPLERS
Optocouplers combine infrared LED and a silicon photo transistor. The input
signal is applied to ILED and the output is taken from the photo transistor. The rise and
fall times of photo transistor are very small with typical values of turn on time = 2.5 s
and turn off of 300ns. This limits the high frequency applications. The photo transistor
could be a darlington pair. The phototransistor require separate power supply and add to
complexity and cost and weight of driver circuits.
Optocoupler
R
V
g1
1
+
-
R
B
R
1
1
Q
1
0
R
2
+V
CC
Q
3
G
R
3
I
D
R
G
R
D
S
M
1
D
I
D
G
V
DD
+
-
1