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U S R P Usrp: Niversal Oftware Adio Eripheral

The document summarizes the Universal Software Radio Peripheral (USRP) hardware developed for software-defined radio. It describes the key features of the original USRP board including 4 ADC/DAC channels and a small FPGA. It then summarizes the higher-end USRP2 board with faster ADC/DAC speeds, a gigabit Ethernet interface, and larger FPGA. Finally, it lists some available daughterboards that can be used with the USRPs to interface with different radio frequencies.

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103 views15 pages

U S R P Usrp: Niversal Oftware Adio Eripheral

The document summarizes the Universal Software Radio Peripheral (USRP) hardware developed for software-defined radio. It describes the key features of the original USRP board including 4 ADC/DAC channels and a small FPGA. It then summarizes the higher-end USRP2 board with faster ADC/DAC speeds, a gigabit Ethernet interface, and larger FPGA. Finally, it lists some available daughterboards that can be used with the USRPs to interface with different radio frequencies.

Uploaded by

deepanece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Universal Software Radio Peripheral

(USRP)

By.,
N.Sathurappan
Asso.Prof (ECE)
SEC

contents

Introduction
Matt Ettus developed the USRP board primarily for GNU

Radio users
The USRP board is an integrated board which does ADC,
DAC & FPGA.
Different kinds of USRP boards,
Network series,
Embedded series
Bus series.

USRP: Universal Radio Peripheral


The hardware solution for GNU
SDR

USR
P

USRP
2

Universal Software Ra
dio Peripheral (USRP)

4 ADC 64MS/s (12-bit)


4 DAC 128MS/s (14-bit)
USB 2.0 interface
Small FPGA
MIMO capable

1. Highest speed 480Mb/s


2. Capable of processing signals up to 16 MHz wide

Universal Software Radio


Peripheral (USRP2)

2 ADC 100MS/s (14-bit)


2 DAC 400MS/s (16-bit)
Gigabit Ethernet Interface
Larger FPGA
On-board SRAM
MIMO capable

1. 2 Gbps high-speed serial interface for expansion


2. Capable of processing signals up to 100 MHz wide

Available daughter-boards
Basic TX/RX: 1MHz 250MHz
(20dBm)
LFTX/LFRX: DC 30MHz
RFX900: 750MHz
TVRX:
50MHz-860Mhz
1050MHz(23dBm)
DBSRX:
800MHz 2.4GHz RFX1200: 1150MHz
WBX0510:
50MHz
1450MHz(23dBm)
1GHz(20dBm)
RFX1800:
1.5GHz 2.1GHz(20dBm)
XCVR2450: 2.4GHz 2.5GHz & 4.9GHz
-5.9GHz(20dBm)
RFX2400: 2.3GHz 2.9GHz(17dBm)

RFX400: 400MHz 500MHz

Software Defined Radio Block Diagram

RF Front End
Mixer

Antenna

Low
Noise
Amplifier

Low Pass
Filter

Low Pass
Filter

Local
Oscillator

ADC

FPGA MUX

FPGA DDC

Example 2-1: Simple transmission

A simple sinusoidal wave is transmitted. We can


view it at the receiver in spectrum domain.

USRP B210

b200

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