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Vhdland Digital: The Product Terms Are Allocated

This document contains a VHDL and digital design exam paper consisting of 4 units and 7 questions. It tests knowledge of programmable logic devices (PLDs) like the 22V10 macro cell, VHDL concepts like transport delay and inertial delay, designing state machines and circuits in VHDL, using procedures, packages, generate statements, and guarded blocks. Students must attempt 5 questions by selecting at least one from each section, with each question worth 10 marks for a total exam mark of 100.

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42 views4 pages

Vhdland Digital: The Product Terms Are Allocated

This document contains a VHDL and digital design exam paper consisting of 4 units and 7 questions. It tests knowledge of programmable logic devices (PLDs) like the 22V10 macro cell, VHDL concepts like transport delay and inertial delay, designing state machines and circuits in VHDL, using procedures, packages, generate statements, and guarded blocks. Students must attempt 5 questions by selecting at least one from each section, with each question worth 10 marks for a total exam mark of 100.

Uploaded by

Who Knows
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll No.

Printed Pages

8T_6 tM.12
VHDLAND DIGITAL DESIGN
Paper-ECE-304 E
Time allowed: 3 hoursl

Note

fMaximunt tnark,y

: t00

Attempt five questions in all, by selecting at least


one question from each section.

Unit_I

1. (a)

Explain 22V10 macro cell with near diagram.

How the product terms are allocated to


macro cells in a programmable logic device
(PLD)

(b)

10

Explain advantages of programmable logic.


Explain two programming technologies which
are used in pLDs to establish programmable

connection.
?. (a)
(b)

l0

State the difference berween PROM and pLA.


lmplement full adder using PROM.
l0
Design a three-bit synchronous counter with
an
enable to implement in 22v10 pLD device.
The

design has two additional outputs_one that is


asserted when present count is greater than
three,
and one that is asserted when the count is equal

to

six.

@-e-8-6eso

l0
tP.T.r.

(2)

,
'

Unit-il
,
3. (a) Explain the following giving requisite
statements of VFtrDL:,

(i)
(ii)
(b)

Transport delay

Inerlial

delay.

10

Write the VHDL code of state machine to


detect the sequence "1001" on a data input
then produce a logic '1' output when the
sequence has been'detected. Overlaps must be

considered
4. ' (a)

'

Use

10

NULL statement to'rfrite the VHDL code in

which control signal, CTRL, is having the range


0 to 31. When the value of CTRL is 2 or 18, the
signals X andY willo-e and-ed, otherwise nothing

will

(b)

occur.

10

Write the structural VHDL description of the


circuit Fig. (1)
A:

c
D
E
F

r?\
Unit-ilI
(a). W.rite,rVHDL procedure'program to sort two
S.bit numbers artd use it fcr making the code of
.the following circuit Fig. (2).
irtp

llllrl

inpl

rl) il

()ut

x*{)tt

Fig. (2)

(b)

10

What are two kinds of subprograms. Write

function of XOR gate and use it in the main code

for making half Adder.


6.

(a)

10

Make a VHDL package that includes full


subtractor components and use it for making the

main code of full subtractor.

(b) Write a VHDL

10

code to make a Generic

comparator that compares two n-bit numbers

and B and gives the three outputs as G, E, L

forA > B,A

= B andA < B

respectively.

10

tR,Tqi

(4)
UnitJV

7. (a)

Write a VHDL code using generate construct to


convert binary to gray code coverter. l0

(b)

Explain Alias statement. Elaborate with an


example that how it is useful in dealing with
signal of large vector.
l0

,
@)

Synthesise the following funcrion using 2:1


,A.1

= X1. X3 +X2.X3

(b1 Write VHDL

MUX.

l0

code ro implemenr latch with a


Guarded BLOCK statement.
l0

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