UNIT-5

INTRODUCTION DIGITAL SIGNAL

PROCESSORS AND ITS
APPLICATION
DSP/ISP division
School of Electronics Engineering
VIT University
Vellore -632 014

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 OBJECTIVE
• Understand the DSP Architecture, fixed and
floating point processor differences
• Able to understand how pipelining and
parallelism supports in the DSP Architecture.
• Know how to implement convolution,
correlation, DFT & Filter design using Texas
instruments DSP processor.

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 Introduction
• DSP processors can be divided into two
broad categories:
» General Purpose
» Special Purpose
• Further DSP processors include
» Fixed point devices
» Floating point devices

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 Examples of Fixed and Floating
• Low End Fixed Point
– TMS320C2XX, ADSP21XX, Motorola
(DSP56XXX)
• High End Fixed Point
– TMS320C55XX, DSP16XXX,
– ADSP215XX, DSP56800
• Floating Point
– TMS320C3X, C67XX, ADSP210XX(SHARC
processor), DSP96000, DSP32XX

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 Fixed Point Vs Floating Point
– fixed point processor are :
• cheaper
• smaller
• less power consuming
• Harder to program
– Watch for errors: truncation, overflow, rounding
• Limited dynamic range
• Used in 95% of consumer products

– floating point processors

• have larger accuracy
• are much easier to program
• can access larger memory

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Fixed Point Vs Floating Point
Floating Point Fixed Point
Applications Applications
•Modems •Portable Products

•Digital Subscriber Line (DSL) •2G, 2.5G and 3G Cell Phones

•Wireless Basestations •Digital Audio Players

•Central Office Switches •Digital Still Cameras

•Private Branch Exchange (PBX) •Electronic Books

•Digital Imaging •Voice Recognition

•3D Graphics •GPS Receivers

•Speech Recognition •Headsets

•Voice over IP •Biometrics

•Fingerprint Recognition

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 Special purpose hardware
• Hardware designed for efficient execution of
specific DSP algorithms such as digital filter,
FFT. [ Algorithm-specific digital signal processor]

• Hardware designed for specific application, for

example telecommunications, digital audio, or
control applications.[ Application -specific digital
signal processor]

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 Computer Architecture for Signal
Processing
Techniques
• Harvard Architecture
• Pipelining
• Fast, dedicated hardware multiplier/Accumulator
• Special instruction dedicated to DSP
• Replication
• On-chip memory/cache
• Extended parallelism- SIMD, VLIW and static
superscalar processing
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 Basic generic hardware architecture for signal processing

ALU
Multiplier
Accumulator

Memory units

I/O Shifter Program

X data Y data
devices memory
memory memory

X data bus

Y data bus

DSP DIVISION
Z data bus
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 Harvard
Architecture

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 Hardware Multiply and
accumulate

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 Pipelining
• A technique which allows two or more
operations to overlap during execution.

• It is used extensively in DSP to increase speed.

• The simultaneous functions going on are:

• instruction fetch
• instruction decode
• instruction execution

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 Stages of pipelining

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• In a Harvard architecture (DSP processor with
pipelining) :

• The program instructions and data lie in

separate memory spaces.

• Due to this the fetching of the next instruction

can overlap the execution of the current
instruction.

• Each of the step is known as pipeline stage

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 REGISTERS
• In TMS320 number of registers are used to achieve
pipelining.

• Pre-fetch counter: holds the address of the next

instruction to be fetched.
• Instruction register: holds the instruction to be
executed.
• Queue instruction register: stores the instruction to be
executed if the current is still in process of execution.
• Program counter: contains the address of the next
instruction to be executed

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 Parameters used in pipelining

•Throughput is determined by the number of

instructions through the pipe per unit time.

•In a perfect pipeline the average time per

instruction is given by( Hennesy and
Patterson,1990)
time per instruction(non-pipeline)
number of pipe stages

Average instruction time (nonpipeline)

•Speedup=
DSP DIVISION AverageDSP
instruction
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 ADVANTAGES
The cycle time of the processor is reduced, thus increasing
instruction bandwidth in most cases.

DISADVANTAGES
The design is complex due to addition of extra flip flops.
The manufacture cost is high.
The performance of a pipelined processor is much harder
to predict and may vary more widely between different
programs due to unstable instruction bandwidth.

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 Examples (pipelining)
• Multiply and accumulate operations typified by the following
equation
• a0x(n)+a1x(n-1)+a2x(n-2)+…..+AN-1x(N-1)
• Non pipeline of the above equation

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 MAC Pipeline operation

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 Parallelism
• To achieve increased computational
performance
• Three techniques used to achieve
parallelism are
• SIMD
• VLIW
• Superscalar processing

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 SIMD (Single instruction multiple
data)
• Used to increase number of operation
performed per instruction
• Multiple data path and multiple execution
unit
• Single instruction may be issued to
multiple execution unit to process the
block of data simultaneously and in this
way number of operation performed in one
cycle is increased
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 SIMD

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VLIW (Very Long Instruction Word)

• Substantially increasing the number of

instruction that are processed per cycle
• Essentially a concatenation of several
short instruction and require multiple
execution units running in parallel to carry
out the instructions in a single cycle

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 Features of VLIW
• The cpu contain two data paths and eight independent
execution units, organized in two sets –(L1,S1,M1,D1)
and (L2,S2,M2,D2)
• Each short instruction is 32 bits wide and eight of these
are linked together to form a very long instruction word
packed which may be executed in parallel.
• VLIW architecture is clearly designed to support
instruction level parallelism, together with fast clock
speeds-200MHz

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 Super scalar processing
• Increasing the instruction rate of a DSP processor (the
number of instruction processed in a cycle) by exploiting
instruction-level parallelism.
• Super scalar- computer architecture that enable multiple
instruction to be executed in one cycles
• It is widely used in general purpose processor such as
power PC, and Pentium processor
• Best known super scalar processor is the Analog
devices Tiger SHARC

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 General Purpose Digital Signal
processor
• It is a High speed microprocessor with hardware
architecture

• Instruction sets are optimized for DSP

operations

• Extensive use of parallelism, Harvard

architecture, pipelining and dedicated hardware,
shifting, scaling, multiplication and so on

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Fixed point Digital Signal Processors

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 Fixed point Digital Signal
processors

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 Floating Point Processors

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 Selecting the Digital Signal
Processor
• Architectural features
• Size of on chip memory
• Special Instruction
• I/O capability
• Execution speed
• Clock speed of the processor(MHz)
• Number of instruction performed (MIPS) &
(MFLOPS)

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• Type of Arithmetic
– Fixed point arithmetic
– Floating point arithmetic
• Word Length
– 24 bit word length for audio processing
– Longer data word length lower the error

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 Implementation of DSP algorithm
on general purpose Digital Signal
Processor
• FIR Digital filtering

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 References:

1. Emmanuel C.Ifeachor, “ Digital Signal Processing A Practical Approach” 2 nd

edition, Pearson Education, 2001.

2. Lawrence R Rabiner and Bernard Gold, “Theory and Application of Digital

Signal Processing” , PHI 1992

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