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Finite Word-Length Effects

Finite word-length effects in digital signal processing include: 1) The quantization error that results from representing analog signals with a finite number of bits, which limits the ability to resolve small signals. 2) As the resolution of an analog-to-digital converter (ADC) increases with more bits, the quantization step size and quantization error decreases. 3) The signal-to-quantization noise ratio (SQNR) of an ideal ADC increases by approximately 6 dB for each additional bit of resolution. However, real ADCs have additional noise sources that reduce the actual SNR.

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Rupali Nerkar
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73 views8 pages

Finite Word-Length Effects

Finite word-length effects in digital signal processing include: 1) The quantization error that results from representing analog signals with a finite number of bits, which limits the ability to resolve small signals. 2) As the resolution of an analog-to-digital converter (ADC) increases with more bits, the quantization step size and quantization error decreases. 3) The signal-to-quantization noise ratio (SQNR) of an ideal ADC increases by approximately 6 dB for each additional bit of resolution. However, real ADCs have additional noise sources that reduce the actual SNR.

Uploaded by

Rupali Nerkar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Finite word-length effects

-R.V.Chothe
Analog & digital signals
Analog Digital
Continuous function V of Discrete function Vk of discrete
continuous variable t (time, space sampling variable tk, with k =
etc) : V(t).
integer: Vk = V(tk).

0.3 0.3
0.2 0.2
Voltage [V]

Voltage [V]
0.1 0.1
0 0
-0.1 -0.1 ts ts
-0.2 -0.2
0 2 4 6 8 10 0 2 4 6 8 10
time [ms] sampling time, tk [ms]

Uniform (periodic) sampling.


Sampling frequency fS = 1/ tS
Digital vs analog proc’ing
Digital Signal Processing (DSPing)

Advantages Limitations

• More flexible. • A/D & signal processors speed: wide-


• Often easier system upgrade. band signals still difficult to treat (real-
• Data easily stored. time systems).
• Better control over accuracy • Finite word-length effect.
requirements. • Obsolescence (analog electronics has
• Reproducibility. it, too!).
DSPing: aim & tools
• Predicting a system’s output.
Applications • Implementing a certain processing task.
• Studying a certain signal.

• General purpose processors (GPP), -controllers.


• Digital Signal Processors (DSP).
Hardware • Programmable logic ( PLD, FPGA ).
Fast real-time
Faster DSPing

• Programming languages: Pascal, C / C++ ...


Software • “High level” languages: Matlab, Mathcad, Mathematica…
• Dedicated tools (ex: filter design s/w packages).
ADC - Number of bits N
Continuous input signal digitized into 2N levels.
1113
Uniform, bipolar transfer function (N=3)
2

V FSR
1
Quantisation step q =
2N
0
-4 -3 -2 -1 0 1 2 3 4
-1 V Ex: VFSR = 1V , N = 12 q = 244.1 V
010
-2

001
-3 Voltage ( = q)
000
-4 Scale factor (= 1 / 2N )
VFSR
LSB
1
Percentage (= 100 / 2N )
q/2
0.5

-4 -3 -2 -1 0 1 2 3 4

Quantisation error
-0.5

-q/2
-1
ADC - Quantisation error
0.3

0.2 · Quantisation Error eq in


[-0.5 q, +0.5 q].
Voltage [V]

0.1
· eq limits ability to resolve small
0 signal.
0 2 4 6 8 10
-0.1 · Higher resolution means lower
e q.
-0.2
time [ms]

-4
2 10
|e q | [V]

10
-4
QE for
N = 12
VFS = 1

0 2 4 6 8 10
Sampling time, tk
SNR of ideal ADC
SNR
20


log

RMS  
input

ideal10
 
RMS(e
)
q 
Also called SQNR
(signal-to-quantisation-noise ratio)

p(e)
quantisationerrorprobabilitydensity

1
q

q q eq
2 2
Errorvalue
SNR of ideal ADC
SNRideal  6.02  N  1.76 [dB]

One additional bit SNR increased by 6 dB

Real SNR lower because:


- Real signals have noise.
- Forcing input to full scale unwise.
- Real ADCs have additional noise (aperture jitter, non-linearities etc).

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