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Inverter Layout Tutorial Ete Ayout Uto A: Multimedia VLSI Lab Sang-Hye Chung

The document provides instructions for creating an inverter layout in a layout editor. It describes how to create a new cell, draw MOSFETs, add vias and contacts, do body biasing, label pins, and perform design rule checking and layout versus schematic checks. Key steps include drawing NMOS and PMOS transistors, connecting them to form an inverter, adding well and body contacts, labeling with the same names as in the schematic, and using the software's DRC and LVS tools to check for errors.

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Seungwook Paek
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© Attribution Non-Commercial (BY-NC)
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178 views24 pages

Inverter Layout Tutorial Ete Ayout Uto A: Multimedia VLSI Lab Sang-Hye Chung

The document provides instructions for creating an inverter layout in a layout editor. It describes how to create a new cell, draw MOSFETs, add vias and contacts, do body biasing, label pins, and perform design rule checking and layout versus schematic checks. Key steps include drawing NMOS and PMOS transistors, connecting them to form an inverter, adding well and body contacts, labeling with the same names as in the schematic, and using the software's DRC and LVS tools to check for errors.

Uploaded by

Seungwook Paek
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1

Inverter Layout Tutorial e te ayout uto a

Multimedia VLSI Lab Sang-Hye Chung

2009-09-15

Create a cell
Open Library Manager Library Manager

Write layout and Enter y


2009-09-15

Create a cell
Create a layout cell

Select Virtuoso !
2009-09-15

Create a cell
Layout window and LSW will be created
LSW : Select layers

2009-09-15

Shortcut Keys
Shortcut Keys
Create Instance : i Edit properties : q Create Ruler : k Delete Ruler : Shift + k Create Label : l Create Rectangle : r Stretch : s Fit all : f Zoom in : Ctrl + z Zoom out : Shift + z
2009-09-15

Draw MOSFETs
NMOS consists of
NPSD NACT MET1 CONT POLY

PMOS consists of
PPSD PACT MET1 CONT POLY

2009-09-15

Draw MOSFETs
Example
PMOS (W = 1um, L = 0.18um) ( , ) PACT PPSD NW

CONT MET1

POLY

2009-09-15

Draw MOSFETs
Example
NMOS (W = 1um, L = 0.18um) ( , ) NACT NPSD

CONT MET1

POLY

2009-09-15

Draw Vias and Contacts Via s Contact s


Via is used to connect between Nth metal and N+1th.
VIA n : Met n Met n+1
EX)

M1

VIA1

M2

M1-M2 M1 M2

Contact is used to connect between the substrate and Metal 1. 1


Contact : NACT, PACT, POLY and etc. MET1
2009-09-15

10

Body Biasing
Use CONTs MET1, and etc. CONT s, MET1 etc PMOS case
Bias the N-Well

NMOS case
Bias the substrate (Black background)

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11

Inverter Layout

NW(N-Well) should include ( ) PMOS and Body Contacts

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12

Inverter Layout

CONT, MET1, NPSD, NACT

Poly Contact : POLY, MET1, CONT


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13

Inverter Layout
Poly Contact : POLY, MET1, CONT

CONT, MET1, PPSD, PACT

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14

Inverter Layout
Labeling
Shortcut Key : l Act Pins A t as Pi USE MnPIN
(n : 1~6) 1 6)

Layout MUST have the same label with pin names in the schematic

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15

Inverter Layout

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16

DRC
Design Rule Check
/> Click Calibre Run DRC

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17

DRC

Select Calibre_drc.rule

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18

DRC

Ignore the alert

This must be checked

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19

DRC

Ignore Pattern Density Rule

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20

LVS
Layout Versus Schematic
/> Click Calibre Run LVS

2009-09-15

21

LVS

Select Calibre_lvs.rule

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22

LVS

This must be checked


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23

LVS

Run R LVS
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24

LVS
Hope you smile too

2009-09-15

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