Lecture #26
ANNOUNCEMENTS
Extra Office Hours this week:
Prof. King: Thursday 10/30 12-2 PM Steve: Friday 10/31 12-2 PM Farhana:
Review session: Friday 10/31 2-4 PM, 120 Latimer
OUTLINE
Logic functions NMOS logic gates The CMOS inverter
Reading
Schwarz & Oldham: Chapters 11.2, 15.3 Rabaey et al.: Chapter 5.2
EECS40, Fall 2003 Lecture 26, Slide 1 Prof. King
Digital Signals
For a digital signal, the voltage must be within one of two ranges in order to be defined:
VDD
1
undefined region
VOH VIH VIL increasing voltage
0 Positive Logic: low voltage logic state 0
high voltage logic state 1
EECS40, Fall 2003 Lecture 26, Slide 2
VOL 0 Volts
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Logic Functions, Symbols, & Notation
NAME NOT A SYMBOL F NOTATION F=A TRUTH TABLE
A F 0 1 1 0 A B 0 0 0 1 1 0 1 1 A B 0 0 0 1 1 0 1 1
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OR
A B A B
F = A+B
F 0 1 1 1 F 0 0 0 1
AND
EECS40, Fall 2003
F
Lecture 26, Slide 3
F = AB
NOR
A B
F = A+B
A B 0 0 0 1 1 0 1 1
F 1 0 0 0
NAND
A B
F = AB
A B 0 0 0 1 1 0 1 1 A B 0 0 0 1 1 0 1 1
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F 1 1 1 0 F 0 1 1 0
XOR
(exclusive OR)
EECS40, Fall 2003
A B
F=A+B
Lecture 26, Slide 4
NMOS Inverter (NOT Gate)
Circuit:
RD iD VDD
Voltage-Transfer Characteristic vOUT
F
VDD
+ + vIN
iD
vDS = vOUT
vIN = VDD 0 VT VDD vIN
VDD/RD
increasing vGS = vIN > VT A F 0 1 1 0
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0
EECS40, Fall 2003
vGS = vin VT
Lecture 26, Slide 5
VDD
vDS
Noise Margins
Definition of Input Levels Definition of Noise Margins
logic swing Vsw
VOL
VOH
Noise margin high NM H = VOH VIH Noise margin low NM L = VIL VOL
EECS40, Fall 2003 Lecture 26, Slide 6 Prof. King
NMOS NAND Gate Output is low only if both inputs are high
VDD RD F A
Truth Table
A B 0 0 0 1 1 0 1 1
Lecture 26, Slide 7
F 1 1 1 0
EECS40, Fall 2003
Prof. King
NMOS NOR Gate Output is low if either input is high
VDD RD F A B
Truth Table
A B 0 0 0 1 1 0 1 1
EECS40, Fall 2003 Lecture 26, Slide 8
F 1 0 0 0
Prof. King
Disadvantages of NMOS Logic Gates Large values of RD are required in order to
achieve a low value of VOL keep power consumption low Large resistors are needed, but these take up a lot of space.
One solution is to replace the resistor with an NMOSFET that is always on.
EECS40, Fall 2003
Lecture 26, Slide 9
Prof. King
The CMOS Inverter: Intuitive Perspective
CIRCUIT VDD
G S D
SWITCH MODELS VDD VDD
Rp VOUT VOUT
VOL = 0 V
VIN
D G S
VOUT
VOH = VDD
Rn
Low static power consumption, since one MOSFET is always off in steady state
EECS40, Fall 2003
VIN = VDD
VIN = 0 V
Prof. King
Lecture 26, Slide 10
CMOS Inverter Voltage Transfer Characteristic
VOUT VDD
N: off P: lin N: sat P: lin N: sat P: sat
VDD
G S D
C
VIN
VOUT
D G S
D
N: lin P: sat
0 0
EECS40, Fall 2003
N: lin P: off
VDD
Lecture 26, Slide 11
VIN
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CMOS Inverter Load-Line Analysis
VIN = VDD + VGSp IDn=-IDp
increasing VIN VIN = 0 V
GS
VOUT = VDD + VDSp
p =V IN -V DD
VDD
VDSp=VOUT-VDD + IDn=-IDp
VOUT
+
VIN = VDD
VIN
increasing VIN
0 0
VDSp = - VDD
EECS40, Fall 2003 Lecture 26, Slide 12
VDD
VDSp = 0
VOUT=VDSn
Prof. King
CMOS Inverter Load-Line Analysis: Region A
VIN VTn IDn=-IDp
V
GS p =V IN -V DD
VDD
VDSp=VOUT-VDD + IDn=-IDp
VOUT
+
VIN
0 0
EECS40, Fall 2003 Lecture 26, Slide 13
VDD
VOUT=VDSn
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CMOS Inverter Load-Line Analysis: Region B
VDD/2 > VIN > VTn IDn=-IDp
V
GS p =V IN -V DD
VDD
VDSp=VOUT-VDD + IDn=-IDp
VOUT
+
VIN
0 0
EECS40, Fall 2003 Lecture 26, Slide 14
VDD
VOUT=VDSn
Prof. King
CMOS Inverter Load-Line Analysis: Region D
VDD |VTp| > VIN > VDD/2 IDn=-IDp
V
GS p =V IN -V DD
VDD
VDSp=VOUT-VDD + IDn=-IDp
VOUT
+
VIN
0 0
EECS40, Fall 2003 Lecture 26, Slide 15
VDD
VOUT=VDSn
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CMOS Inverter Load-Line Analysis: Region E
VIN > VDD |VTp| IDn=-IDp
V
GS p =V IN -V DD
VDD
VDSp=VOUT-VDD + IDn=-IDp
VOUT
+
VIN
0 0
EECS40, Fall 2003 Lecture 26, Slide 16
VDD
VOUT=VDSn
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