STA

(STATIC TIMING ANALYSIS)

PRESENTED BY :
PAVAN RAJ
OUT LINES
1.Types of timing analysis
2.Comparison b/w DTA and STA

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3.Limitations of DTA and STA
4.STA at Different Design Phases In ASIC Flow
5.Delays and transition
6.Types of paths and timing arcs
7. Inputs for STA
8.Clock domains
9.Clock latency
10.Timing exceptions
11.Back - annotation

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1.TYPES OF TIMING ANALYSIS
The timing of a design can be verified using Dynamic

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timing analysis and/or Static timing analysis:

 DYNAMIC TIMING ANALYSIS(DTA)

 In dynamic timing analysis both functionality and timing of
the design is checked. A transistor level or gate level
representation of the design and stimulus or vectors or inputs
are used to simulate and analyze the design.

 Ideal for small designs.

 Requires SPICE models(if transistor level net list) to simulate

transistor level circuits.

 Requires functional and timing models (if gate level net list) to
simulate gate level circuits. 3
 STATIC TIMING ANALYSIS (STA)

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 In STA analysis only timing of large gate level net list is
checked using a non-vector based approach.
-The design is assumed to be functionality correct.

Examples of simulators tool used in DTA

- Eldo and Hspice are SPICE simulators.
-QuestaSim and ModelSim are Gate level Simulators.

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2.COMPARISON B/W DTA AND STA

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DTA STA
Advantage : Advantage:

1.Very accurate 1.Fast , exhaustive because it only

check timing not functionality

2.Considers both functionality and 2. Verifies the timing of all paths in

timing the design

3.Suitable for small designs 3. Suitable for large designs

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3.LIMITATIONS OF DTA AND STA

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DTA
 Quality of results depends on input coverage.

 Slow

 Not suitable for large designs

STA
 Define timing exceptions.

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4.STA AT DIFFERENT DESIGN PHASES IN ASIC FLOW

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5.DELAYS AND TRANSITION

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 Delay is the time taken by signal to propagated from one
point to another in a circuit.
 There are two types of delays
 Cell delay or Propagation delay or Gate delay is the time

taken by the signal to propagate through the gate.

 Wire delay or Net delay or Interconnect delay or Extrinsic

delay 0r Flight delay is the delay due to parasitic on a net .

 Slew or transition is time taken by signal to change its

state(0 to 1 , 1 to 0).

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 Intrinsic delay
6.TYPES OF PATHS AND TIMING ARCS

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Fig: Timing Paths and Timing Arcs

 SEQUENTIAL CELL TIMING ARCS
(TIMING MODELS – SEQUENTIAL CELLS)

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CDN is asynchronous inputs ,SE scan enable, SI scan input 10
SETUP & HOLD TIME ,RECOVERY & REMOVAL

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7. INPUTS FOR STA

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8.CLOCK DOMAINS

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Fig: Two clock domains

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Fig: Mutually-exclusive clocks

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Fig: Clock domain crossing

It is not real timing path since data is not propagated through the
Synchronizer logic in one clock cycle. Such a path is referred to as a false paths.

False paths b/w clock domain can be specified using below

Set_false_path –from [get_clocks USBCLK] –to [get_clocks MEMCLK]

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 If clocks are not synchronous ; most of the STA tools
requires them to be explicitly defined as such
 If the clocks are not defined as asynchronous, STA tool

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analyzes and reports timing on timing paths .As asynchronous
clocks don’t have a definite timing relationship, timing
estimates from STA will be erroneous.

 Clock Uncertainty

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9.CLOCK LATENCY

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Fig: skew & latency
10.TIMING EXCEPTIONS

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 Timing exceptions provide a means to suppress the
reporting of timing for specific path.
 There are 3 types of timing exceptions
 False paths
 Multi cycle paths

 Minimum and maximum delay paths.

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11.BACK - ANNOTATION

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 The process of calculating the net delay from the layout
and attaching such that STA tool can include the net
delay for analysis is called Back annotation .

 It is due to the finite resistance and capacitance of the

net. It is also known as wire delay.

Wire delay = function of (Rnet, Cnet+Cpin)

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Interconnect introduces capacitive, resistive and inductive parasites. All three
have multiple effects on the circuit behavior.
1.Interconnect parasites cause an increase in propagation delay (i.e. it slows
down working speed)
2.Interconnect parasites increase energy dissipation and affect the power
distribution.
3.Interconnect parasites introduce extra noise sources, which affect reliability
of the circuit. (Signal Integrity effects/cross talk) 19
CONTINUE……

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 QUERIES

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THANK YOU
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