UNIT 2:
ARCHITECTURE OF
TMS320C5X
Bhooshan Humane
Topics to be Covered
Bus
Addressing
Architecture Structure & CPU AL syntax
modes
memory
Introduction
• TMS320C5X DSP Chip is denoted in brief as 5X.
• TMS320 DSP Family consists of two types of single-chip DSPs:
• A) 16-bit Fixed Point
• B) 32-bit Floating Point
• TMS320C5X belongs to 5th generation of TI’s TMS320 family of
DSPs.
FIVE GENERATIONS OF TMS320
The first five generation of TS320 family are:
C1X, C2X, C3X, C4X & C5X
The C1X, C2X, C2XX, & C5X are 16-bit fixed point procesors.
Instructions sets of the higher generation fixed-point processors are upward compatible to the
lower generation fixed-point processors.
For Eg: C5X can execute the instructions of both C1X & C2X.
C3X & C4X are 32-bit floating-point processors & C4X is upward compatible with C3X instruction
set.
C6X The Sixth Generation
• The sixth generation C6X devices feature 𝑉𝑒𝑙𝑜𝑐𝑖𝑇𝐼𝑇𝑀 an advanced
VLIW architecture developed by TI & can execute 1600 MIPS.
• Thousand instructions per second (TIPS),
• Million instructions per second (MIPS), and
• Billion instructions per second (GIPS).
Applications of above families of TI DSP
C1X, C2X, Toys, Hard Disk Drives,
C2XX, Modems, Cellular Phones &
C5X, C54X Active Car Suspensions.
Fig: Internal Architecture of
C5X
Bus Structure
• Separate Program Bus & data buses allows simultaneous access to
program instruction & data.
• Parallelism.
• Arithmetic , logic & bit-manipulation operations in a single m/c
cycle.
• There are 4 Buses:
Bus Structure
• Program Bus (PB)= carries the instruction code & immediate
operands from program mem. space to CPU.
• Program Address Bus (PAB) = Provides addresses to program
memory space for both read & writes.
• Data Read Bus (DB) = Interconnects various elements of CPU to
data mem. space.
• Data Read Address Bus (DAB) = Provides the address to access the
data mem space.
Central Arithmetic Logic Unit (CALU)
• 16X16 Bit Parallel Multiplier
• Arithmetic Logic Unit (ALU)
• Accumulator (ACC)
• Accumulator Buffer (ACCB)
• Product Register (PREG)
• Left Barrel Shifter
• Right Barrel Shifter
Auxiliary Register ALU (ARAU)
• ARs (16 Bit Registers)
• ARP (Auxiliary Register Pointer)
• 16-bit ALU
• ARCR (Auxiliary Register Compare Register)
• AR0-AR7
Index Register (INDX)
• The 16-bit INDX is used by the ARAU as a step value (addition or
subtraction by more than 1).
Auxiliary Register Compare Register (ARCR)
• Used for address boundary comparison.
• CMPR instruction.
• Result is stored in TC bit of ST1.
• TC=Test Control/Control Flag Bit.
• ST1= Status Register.
Block Move Address Register (BMAR)
• The 16-bit BMAR holds an address value to be used with block
moves & multiply/accumulate operations.
• This register provides the 16-bit address for an indirect-addressed
second operand.
Block Repeat Registers (RPTC, BRCR, PASR, PAER)
• All these registers are 16-bit wide.
• RPTC=Repeat counter Register.
• PASR= Program address start register.
• PAER= Program address end register.
• RPTB = Repeat block of instructions specified by BRCR.
Parallel Logic Unit (PLU)
• It performs Boolean operations or the bit manipulations required
for high-speed controllers.
• The PLU can set, clear, test or toggle bits in a status register control
register, or any data memory location.
Memory-Mapped Registers
• The ‘C5X has 96 registers mapped into page 0 of the data
memory space.
• All ‘C5X DSPs have:
• 28 CPU registers &
• 16 input/output (I/O) port registers but have different
numbers of peripherals & reserved registers.
Program Controller
• Contains Logic Circuitry that decodes the instructions
• Manages the CPU pipeline
• Stores the status of CPU operations &
• Decodes the conditional operations
• Parallelism helps 3 concurrent operations (in any given m/c
cycle):
• Fetch an instruction
• Read an operand
• Write an operand
Program Controller
• 16-bit program counter (PC)
• 16-bit status register ST0, ST1
• PMST (Processor Mode Status Register)
• CBCR (Circular Buffer Control Register)
• (8x16)-bit Hardware Stack
• Address Generation Logic
• Instruction Register
• Interrupt Flag Register
• Interrupt Mask Register
Flags in Status Register
15-13 12 11 10 9 8-0
ARP OV OVM 1 INTM DP
Fig: Status Register 0 (ST0) bit assignment
Flags in Status Register
15-13 12 11 10 9 8-7 6 5 4 3-2 1-0
ARB CNF TC SXM C 11 HM 1 XF 11 PM
Fig: Status Register 1 (ST1) bit assignment
Status Register 1 (ST1)
• ARB = 3-bit field holds the previous value in ARP in ST0.
• CNF ()
Addressing Modes
• Direct Addressing
• Memory – Mapped Register Addressing
• Immediate Addressing
• Indirect Addressing
• Bit- Reversed Addressing
• Short Immediate Addressing
• Long Immediate Addressing
• Dedicated – Register Addressing
Memory – Mapped Register Addressing
LAMM *
Load contents of memory-mapped register
to ACCL; zero ACCH
24
Before Execution of LAMM * After Execution
ARP 1 1
AR1 825h 825h
Data Mem. 6789h 6789h
825h
Data Mem. 8345h
8345h
25h
ACC 2345h ACC 8345h
25
Immediate Addressing
Can be used to load either a 16-bit constant or a constant of length 13,9
or 7
Accordingly referred as:1) Long Immediate 2) Short Immediate
Indicated by the symbol #
Eg: ADD #56h or ADD #4567h
RPT Instruction Using Short-Immediate Addressing
• RPT #99 ;Execute the instruction that follows RPT
;100 times.
Fig: Instruction Register Contents
Indirect Addressing
• The indirect addressing mode of C5X permits the AR used for the
addressing to be updated automatically either after or before the
operand is fetched.
• Separate instructions is not required to update AR.
• SBRK, ADRK (The ADRK instruction adds an immediate value to an
AR; SBRK subtracts an immediate value.)
Subtract Short-Immediate Value From Auxiliary
Register (SBRK)
Subtract Short-Immediate Value From Auxiliary
Register (SBRK)
Various options in Indirect Addressing Mode
Sr. No. Symbol Value of AR pointed by ARP after instruction execution
1 * AR unaltered
2 *+ AR Incremented by 1
3 *- AR Decremented by 1
4 *0+ AR incremented by the content of INDX
5 *0- AR decremented by the content of INDX
6 *BR0+ AR incremented by the content of INDX with reverse carry propogation
7 *BR0- AR decremented by the content of INDX with reverse carry propogation
LACC (Load Accumulator With Shift LACC)
Syntax
• LACC dma [, shift] Direct addressing
• LACC dma, 16 Direct with left shift of 16
• LACC ind [, shift [, ARn]] Indirect addressing
• LACC ind, 16[, ARn] Indirect with left shift of 16
• LACC #lk [, shift] Long immediate addressing
LACC (Load Accumulator With Shift LACC)
Operands
• dma: 7LSBs of the data-memory address
• shift: Left shift value from 0 to 15 (defaults to 0)
• n: Value from 0 to 7 designating the next
auxiliary register
• lk: 16-bit long immediate value
• ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
LACC (Load Accumulator With Shift LACC)
Execution
LACC (Load Accumulator With Shift LACC)
• LACC *, 0
• LACC *+, 1
• LACC *-, 2
• LACC *0+, 4
• LACC *0-, 3
Before Execution After Execution
LACC *, 0 ACC 2345 AR2 1250h
LACC *+, 1 ACC 468Ah AR2 1251h
LACC *-, 2 ACC 8D14h AR2 1250h
1252h
LACC *0+, 4 ACC 307EEh AR2
11A28h AR2 1250h
LACC *0-, 3 ACC
36
Bit-Reveresed Addressing
Sr. No. Instruction Executed Value of AR2
1 MAC 0FF00h, *BR0+ AR2 = 0110 0000 (0th Value)
2 MAC 0FF00h, *BR0+ AR2 = 0110 1000 (1st Value)
3 MAC 0FF00h, *BR0+ AR2 = 0110 0100 (2nd Value)
4 MAC 0FF00h, *BR0+ AR2 = 0110 1100 (3rd Value)
5 MAC 0FF00h, *BR0+ AR2 = 0110 0010 (4th Value)
6 MAC 0FF00h, *BR0+ AR2 = 0110 1010 (5th Value)
7 MAC 0FF00h, *BR0+ AR2 = 0110 0110 (6th Value)
8 MAC 0FF00h, *BR0+ AR2 = 0110 1110 (7th Value)
Bits, Bytes and Words
Definitions
• Bit = Binary digit = 0 or 1
• Byte = a sequence of 8 bits = 00000000, 00000001, ..., or
11111111
• Word = a sequence of N bits where N = 16, 32, 64 depending on
the computer
Immediate Addressing
Short Immediate (1- word)
Sr. No. 8-bit Constant 9-bit 13-bit Constant
Constant
1 ADD LDP MPY
2 ADRK
3 LACL
4 LAR
5 RPT
6 SBRK
7 SUB
Immediate Addressing
Long Immediate (2 - word) 16 bit constant
ADD AND APL
LACC LAR MPY
OR SUB RPTZ
SPLK XPL XOR
RPT CPL
SBRK OPL
Long Immediate Addressing with Dual Data Memory
Access
General syntax: BLDD source, destination
• BLDD #lk, dma Direct with long immediate source
• BLDD #lk, ind [, ARn] Indirect with long immediate source
• BLDD dma, #lk Direct with long immediate
destination
• BLDD ind, #lk [, ARn] Indirect with long immediate
destination
Long Immediate Addressing with Dual Data Memory
Access
• Operands
• dma: 7 LSBs of the data-memory address
• n: Value from 0 to 7 designating the next auxiliary register
• lk: 16-bit long immediate value
• ind: Select one of the following seven options:
*, *+, *–, *0+, *0–, *BR0+ , *BR0–
BLDD Instruction
Circular Addressing
• Convolution, Correlation & FIR filters use circular buffer in
memory to process most recent data.
• Five memory mapped registers control the Circular Buffer
Operation.
• CBSR1
• CBSR2
• CBSER1
• CBSER2
• CBCR Enables / Disables the circular buffer operation.
