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Digital Circuits and Systems: Spring 2015 Week 9

This document discusses ripple carry adders. It begins by explaining half adders and full adders, which are the basic building blocks. It then shows how multiple full adders can be cascaded to create an n-bit ripple carry adder. The performance of ripple carry adders is analyzed, showing that the propagation delay scales linearly with the number of bits. Finally, some exercises are proposed involving signed number comparison and absolute value generation.

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Sriram Murugan
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57 views11 pages

Digital Circuits and Systems: Spring 2015 Week 9

This document discusses ripple carry adders. It begins by explaining half adders and full adders, which are the basic building blocks. It then shows how multiple full adders can be cascaded to create an n-bit ripple carry adder. The performance of ripple carry adders is analyzed, showing that the propagation delay scales linearly with the number of bits. Finally, some exercises are proposed involving signed number comparison and absolute value generation.

Uploaded by

Sriram Murugan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Spring 2015 Week 9 Module 50

Digital Circuits and


Systems

Ripple Carry Adder

Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay


Adders and Subtracters
 The most basic arithmetic operation in a digital computer is
addition.
 Half Adder is a combination circuit that performs addition of 2
bits.

Inputs Outputs
a b Carry Sum
0 0 0 0
Sum  a b  a b  a  b
0 1 0 1
Carry  a b
1 0 0 1
1 1 1 0

Ripple Carry Adder 2


Half Adder

Sum  a b  a b  a  b
Carry  a b

 Half adders cannot accept a carry input and hence it is not possible
to cascade them to construct an n-bit binary adder.

Ripple Carry Adder 3


Full Adder
 Full Adder is a combinational circuit that forms the arithmetic sum of
three input bits. It is described by the following truth table:

Inputs Outputs
c b a Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 

Ripple Carry Adder 4


Full Adder Implementation - 1

Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 

ai bi
ai
si bi
Full
Adder
ci+1 ci
(FA)
ci+1
ci
Full Adder at bit i
si

Ripple Carry Adder 5


Full Adder Implementation - 2
 A full adder can be implemented using 2 half adders and an OR gate

ai
si bi

ci+1 ci

ai bi

Full
Adder
ci+1 ci
(FA)

si

Ripple Carry Adder 6


Performance of a Full Adder
 Use a 2-input NAND gate implementation of a 1-bit full adder.

Ripple Carry Adder 7


Ripple Carry Adder
 4-bit Binary Adder: ( Sum = A + B )
 A 4-bit binary adder can be implemented by cascading four 1-bit full
adders as follows:
 Inputs: A = (a3a2a1a0) Outputs: Sum = (s3s2s1s0)
B = (b3b2b1b0) Cout = c4
Cin = cin = c0

Ripple Carry Adder 8


Performance of an n-bit Ripple Carry
Adder

 Carry ripples from input co to output cn


 Worst case propagation delay for sum in terms of 2-input NAND gate
delay (1 gd) is given by,
t sum  5  i 1 2  3  5  2n  2  3  2n  4
n 2

 Worst case propagation delay for carry output is given by,


t carry  delay for cn 1  2  5  ni12 2  2  2n  3

 Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).

Ripple Carry Adder 9


Exercises

 Design a signed comparator for comparing two 4-bit 1’s


complement numbers A and B
 If A > B, the circuit should produce 1 as output, otherwise 0
 Design a signed comparator for comparing two 4-bit 2’s
complement numbers A and B
 If A > B, the circuit should produce 1 as output, otherwise 0
 Design an n-bit absolute (ABS) value generator for 2’s
complement represented numbers, i.e., for an n-bit input,
X, the output is |X|

Ripple Carry Adder 10


End of Week 9: Module 50

Thank You

Ripple Carry Adder 11

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