International Journal of Advanced Science and Research

International Journal of Advanced Science and Research

ISSN: 2455-4227
Impact Factor: RJIF 5.12
www.allsciencejournal.com
Volume 3; Issue 1; January 2018; Page No. 01-02

An improved carry save adder design

S Subha
Department of Information Technology and Engineering, School of Information Technology and Engineering, Vellore Institute of
Technology, Vellore, Tamil Nadu, India

Abstract
Binary addition is performed using full adders. Carry save adders are studied in literature and have wide applications in numerical
applications. This paper proposes binary addition algorithm. The input is two 32-bit numbers. The sum and carry of individual bits
are calculated. The results are added according to weightage to the bits using modified full adder logic. The result is n+1 bit
number. The proposed model is simulated with Quartus2 toolkit and compared with carry save adder logic. An improvement in
area by 27% with power saving of 8.5% with timing improvement of 6.8% in proposed model compared with traditional model is
observed.

Keywords: carry save adder, full adder, performance improvement

1. Introduction addition of two n-bit numbers using carry save addition

Computer ALU performs integer and floating point operations principle and modified full adder circuit. The proposed model
[1]
. The integer operations are add, subtract, multiplication and is simulated using Quartus 2 tookit. An improvement in area
division [2, 3]. Integer addition is performed using full adders. by 27% with power saving of 8.5% with timing improvement
A full adder has three inputs and two outputs. The outputs are of 6.8% in proposed model compared with traditional model is
sum and carry. Various full adder circuits/models are observed.
proposed in literature. Some of them are carry skip adder, The rest of paper is organized as follows. Section 2 gives
ripple carry adder, carry select adder, Carry save adder, mathematical background, section 3 proposed work, section 4
parallel prefix adder [2]. simulations, section 5 conclusion followed by references.
In carry save adder, two n-bit numbers are added to give sum
and carry. The sum and carry of individual bits are calculated 2. Mathematical Background
separately. The result is added according to their weights to Consider full adder. It takes three inputs A, B, C and gives
give the result. Wallace tree is one method to implement carry two outputs Sum and Carryout. The truth table of full adder is
save adders [2]. This paper proposes method to perform given below in Table 1.

Table 1: Full Adder Truth Table

A B C Sum Carryout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

From Table 1, the expressions for sum and carryout are given sum is 0010 and carry is 1001. The result is added as 0010 +
below: 10010. The final sum is 10100. This is represented below.
A: 1 0 1 1
Sum = a XOR b XOR b
B: 1 0 0 1
Carryout = ab + bc + ca (1)
Sum: 0 0 1 0
The carry save adder is one method to implement the adder Carry: 1 0 0 1
circuit. It takes two n-bit numbers and b. The sum and carry of Now add sum and carry according to weights of bits.
individual bits of the inputs is calculated. The result of bits of Sum: 0 0 1 0
same weights is added using full adders to get final result. As Carry: 1 0 0 1
an example consider two 4-bit numbers 1011 and 1001. The Result: 1 0 1 0 0

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International Journal of Advanced Science and Research

3. Proposed Model one, the sum is negated (taking XOR). If the a input is zero,
Consider two n-bit numbers a and b. Find the sum and carry of the cinput is made zero. Consider the i-th bit position. If the
bits in a and b. Let them be sum and carryout. Add the sum carry is one, cin is zero, carryout is sum and sum is not(sum).
and carryout according to bit weightage. The following If the carry is one, cin is one, carryout is one. If the carry is
algorithm is used for addition. zero, carryin is zero, cout is zero. If the carry is zero, carryin is
Algorithm Modified Carry Save Adder Algorithm: Given two one, carryout is sum and sum is not (sum). The end bits are
n- bit numbers this algorithm gives the sum of the two input special cases. The circuit was compared with carry save adder.
numbers a and b. The carry save adder model is called traditional model. The
1. Start simulation results are shown in Table 3. As seen from Table3
2. Do steps 3-5 for each bit in the inputs. there is improvement in area by 27% with power saving of
3. Intiialize sum = b, carry = b 8.5% with timing improvement of 6.8% in proposed model
4. If a = 1, sum = !b compared with traditional model.
5. If a = 0, carry = 0
6. Pair the sum and carry calculated according to their Table 3: Simulations Results
weights. Parameter Traditional Proposed %improvement
7. Do steps 7-8 for each set of inputs (sum, carry, cin) where Area 136/14448 99/14448 27.02%
cin is the carry from previous position bits addition. Power 85.80mW 78.50mW 8.5%
8. The result and carryout from the addition of (s, carry, cin) Timing 24.549ns 22.863 6.86%
is given by the Table1. The Sum and cout give the result
and carryout of the operation. The cout is calculated before 5. Conclusion
sum. The addition algorithm is adapted from [4]. The An improved algorithm for carry save adder is proposed in
carryout from bit-i is the cin in bit i+1 position. this paper. The algorithm initializes the results in various steps
to one of the operands before computation. The full adder
Table 2: Full Adder Logic algorithm proposed in [4] is used to calculated the final sum.
S Carry Cin Sum cout The proposed model is simulated using Quartus2 Toolkit. An
S 1 0 !s s improvement in area by 27% with power saving of 8.5% with
S 1 1 S 1 timing improvement of 6.8% in proposed model compared
S 0 0 S 0 with traditional model is observed.
S 0 1 !s s
6. References
9. The bits in position 0 and n need special attention. In bit 1. Behrooz Parhami. Computer Arithmetic Algorithms and
zero position, there is no input carry cin and Carry. The Hardware Design, Oxford University Press, 2000.
result is the value of S. In bit position n, there is no S 2. Israel Koren. Computer Arithmetic Algorithms, Prentice
input. The result is the sum of Carry and cin. Hall, NJ, 1999.
10. Stop: Initializations in steps 3-5 and initialization of result 3. Morris Mano, Computer System Architecture, 3rd Edition,
in step 7 to Sum reduces the computational time. For n-bit Prentice Hall, 2007.
addition, it takes O (n) for calculating the initial sum and 4. Subha S. A Gate Level Full Adder Design with Power
carry. It takes O (n) for performing step 7 in algorithm Saving, IJAER. 2015; 10(17):38384-38386
above. The overall time complexity is O (n).

Example: The steps in calculating sum of inputs 1011 and

1001 is given below:
A=1011
B = 10 0 1
Sum = 0 0 1 0
Carry: 1 0 0 1
Result [0] = sum [0] = 0
Result [1] = add (1, 1, 0) Here sum = !1 = 0 and cout = s = 1
Result [2] = add (0, 0, 1). Here sum = !s = 1 and cout = s = 0
Result [3] – add (0, 0, 0). Here sum = s= 0 and cout = 0
Result [4] = add (1, 0). Here sum = 1 and cout = 0
Hence result is 10100 with cout = 0.

4. Simulations
The proposed model was simulated in Quartus2 Toolkit. Input
of 32-bits was used for simulation. The circuit was written in
Verilog and synthesized. The logic of the code is given next.
Let the inputs be a and b. The sum is initialized to the b input.
The carry input is initialized to the sum input. If the a input is