SIMULATE OTRA USING POWER

EFFICIENT CMOS AND USE IT IN

VARIOUS CIRCUITS

JASPREET SINGH
075EC15

JATIN PHOGAT
076EC15

KAUTLIYA KUMAR
082EC15

MANISH MEENA

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 092EC15

INDEX

Introduction 2

The Proposed OTRA 3

Applications of OTRA 6

PSpice Code 7

Floating Gate MOS 9

Conclusion 11

References 12

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 1. Introduction

Analog multipliers find extensive application in the field of telecommunication, control,

instrumentation, measurement, and signal processing. A number of circuits are related to
analog multipliers.

Recently the OTRA has emerged as an alternate

analog building which inherits all the advantages
of current mode techniques. The OTRA is a high
gain current input voltage output device. The
input terminals of OTRA are internally
grounded, thereby eliminating response
limitations due to parasitic capacitances and resistances at the input. Several high
performance CMOS OTRA topologies have been proposed in the literature. In the recent
past OTRA has been extensively used as an analog building block for realizing a number
of analog signal processing and generation circuits.

Here a single OTRA based low voltage analog multiplier which does not use any external
passive components and hence is suitable for integration. The proposed circuit can be used
as a four quadrant multiplier without any change of topology. The workability of the
proposed multiplier is demonstrated through two applications, namely, a squarer and an
amplitude modulator.

OTRA is a three-terminal device, its port relations are characterized by the following
matrix:

where Rm is transresistance gain of OTRA. For ideal operations Rm approaches infinity

and forces the input currents to be equal. Thus OTRA must be used in a negative feedback
configuration.

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 2. The Proposed OTRA

The proposed OTRA presented in figure is based on the cascaded connection of the
modified differential current conveyor (MDCC) and a common source amplifier. The
MDCC provides the current differencing operation, whereas the common source amplifier
provides the high gain stage. The performance of the proposed circuit was verified by
PSpice simulations, with supply voltages ±2.5 V. The output voltage of the OTRA when
the non inverting input is scanned from -200 mA to +200 mA for different values of the
inverting input.
For the proposed OTRA, the input resistance is 5V, whereas the offset current is 51nA.

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For ideal operation, the transresistance gain approaches infinity and negative feedback
forces the two input currents to be equal. Practically, the transresistance gain is finite and
its effect should be considered. Also, the frequency limitations associated with the OTRA
should be considered.

For high frequency applications, the transresistance gain, Rm(s), can be expressed as:

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3. Applications of OTRA

 The OTRA is suitable for non-linearity cancellation, as the two

input terminals are virtually grounded.
 Amplifiers find many useful applications in modern analog VLSI
signal and information processing. Using linear passive resistors
to achieve amplification consumes a large area. In addition, they
cannot be electronically programmed to compensate for the
spread in their absolute values caused by random process
variations. A direct application of the OTRA is to implement a
Voltage Controlled Voltage Source (VCVS)
 Integrator-Current-mode and voltage-mode integrators
employing a single, virtually grounded capacitor and a single
OTRA are reported, respectively. The proposed integrator can be
tuned to achieve both ideal and lossy integration.
 Continuous time filters using op amps, transconductors and
switched capacitors are now widely accepted in industry where
they are used in applications involving direct signal processing,
especially for medium dynamic range applications.
 Tow Thomas Bi-quad filter.
 Quadrature Oscillator

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 4. PSpice Code

mo1 1 1 0 0 n w=100u l=2.5u

mo2 2 1 3 3 n w=100u l=2.5u
mo3 11 1 8 8 n w=100u l=2.5u
mo4 7 4 5 5 n w=10u l=2.5u
mo5 3 4 5 5 n w=30u l=2.5u
mo6 8 4 5 5 n w=30u l=2.5u
mo7 9 4 5 5 n w=10u l=2.5u
mo8 7 7 6 6 p w=50u l=2.5u
mo9 1 7 6 6 p w=50u l=2.5u
mo10 2 7 6 6 p w=50u l=2.5u
mo11 11 7 6 6 p w=50u l=2.5u
mo12 12 10 6 6 p w=100u l=2.5u
mo13 13 10 6 6 p w=100u l=2.5u
mo14 9 2 6 6 p w=50u l=0.5u
ra 10 0 10meg
vdd 6 0 DC 1.5
vss 0 5 DC 1.5
ip 8 13 DC 0
in 3 12 DC 0
*va 4 0 DC 1
vb 4 0 DC 0
.model p PMOS(VTO=-0.58 LEVEL=3 GAMMA=.76 PHI=.905 CGSO=1.38E-10
CGDO=1.38E-10 CGBO=3.4E-10 CJ=85E-5 JS=.38E-6 UO=100 TOX=1E-8 XJ=.1E-6
CJSW=4.67E-10 PB=.911 KAPPA=2 VMAX=113E3 THETA=.12)
.model n NMOS(VTO=0.62 LEVEL=3 UO=460.5 TOX=1E-8 JS=1.8E-6 XJ=.15E-6 PB=.761
PHI=.905 GAMMA=.69 CJ=76.4E-5 CJSW=5.6E-10 CGSO=1.38E-10 CGDO=1.38E-10
CGBO=3.4E-10 KAPPA=0.1 VMAX=130E3 THETA=.129)

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*.model p PMOS(VTO=-0.58)
*.model n NMOS(VTO=0.62)
*.model p PMOS(VTO=-0.58 LEVEL=3 UO=100 TOX=1E-8 TPG=1 JS=.38E-6 XJ=.1E-6
RS=886 RSH=1.81 LD=3E-8 ETA=0 VMAX=113E3 NSUB=2.08E17 PB=.911 PHI=.905
THETA=.12 GAMMA=.76 KAPPA=2
* AF=1 WD=1.4E-7 CJ=85E-5 MJ=.429 CJSW=4.67E-10 MJSW=.631 CGSO=1.38E-10
CGDO=1.38E-10 CGBO=3.4E-10 KF=1.08E-28 DELTA=0.81 NFS=.52E11 )
*.model n NMOS(VTO=0.62 LEVEL=3 UO=460.5 TOX=1E-8 TPG=1 JS=1.8E-6 XJ=.15E-
6 RS=417 RSH=2.73 LD=4E-8 ETA=0 VMAX=130E3 NSUB=1.71E17 PB=.761 PHI=.905
THETA=.129 GAMMA=.69 KAPPA=0.1
* AF=1 WD=1.1E-7 CJ=76.4E-5 MJ=.357 CJSW=5.6E-10 MJSW=.302 CGSO=1.38E-10
CGDO=1.38E-10 CGBO=3.4E-10 KF=3.07E-28 DELTA=0.42 NFS=1.2E11)
*.dc LIN vb -1.5 1.5 0.25
.dc LIN in -50u 50u 5u .ip -50u 50u 5u
.probe
.end

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 5. Floating Gate MOS
The floating-gate MOSFET (FGMOS) is a field-effect transistor, whose structure is similar
to a conventional MOSFET. The gate of the FGMOS is electrically isolated, creating a
floating node in DC, and a number of secondary gates or inputs are deposited above the
floating gate (FG) and are electrically isolated from it. These inputs are only capacitively
connected to the FG.
Since the FG is completely surrounded by highly resistive material, the charge contained
in it remains unchanged for long periods of time. Usually Fowler-Nordheim
tunnelling and hot-carrier injection mechanisms are used to modify the amount of charge
stored in the FG.
Some applications of the FGMOS are digital storage element
in EPROM, EEPROM and flash memories, neuronal computational element in neural
networks, analog storage element, digital potentiometers and single-transistor DACs.
An FGMOS can be fabricated by electrically isolating the gate of a standard MOS
transistor, so that there are no resistive connections to its gate. A number of secondary gates
or inputs are then deposited above the floating gate (FG) and are electrically isolated from
it. These inputs are only capacitively connected to the FG, since the FG is completely
surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a
floating node.
For applications where the charge of the FG needs to be modified, a pair of small extra
transistors are added to each FGMOS transistor to conduct the injection and tunneling
operations. The gates of every transistor are connected together; the tunneling transistor
has its source, drain and bulk terminals interconnected to create a capacitive tunneling
structure. The injection transistor is connected normally and specific voltages are applied
to create hot carriers that are then injected via an electric field into the floating gate.

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Large signal DC
The equations modeling the DC operation of the FGMOS can be derived from the
equations that describe the operation of the MOS transistor used to build the FGMOS. To
derive a set of equations that model the large signal operation of an FGMOS device, it is
necessary to find the relationship between its effective input voltages and the voltage at its
FG.
Small signal
An N-input FGMOS device has N−1 more terminals than a MOS transistor, and
therefore, N+2 small signal parameters can be defined: N effective
input transconductances, an output transconductance and a bulk transconductance.
Respectively:

where CT is the total capacitance seen by the floating gate. These equations show two
drawbacks of the FGMOS compared with the MOS transistor:

 Reduction of the input transconductance

 Reduction of the output resistance

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 6. Conclusion

A new realization of the Operational Transresistance Amplifier using FG-MOS is

presented. The OTRA provides a constant bandwidth virtually independent of the
gain. The main advantage of the OTRA is the ability to implement different analog
circuits without the need of resistors, as it can be used to cancel both the even and
odd non-linear terms associated with MOS transistors operating in the ohmic region.
The proposed applications, which employ this concept, are MOS-C amplifiers,
integrators, continuous time filters and oscillators. The effect of the finite
transresistance gain is considered and methods for compensation have been
proposed. PSpice simulations that confirm the theoretical analysis are included.

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References
[1] C. Toumazou, F. Lidgey, D. Haigh, Analogue IC Design: the CurrentMode Approach, Peter
Peregrinus 1990.
[2] J. Chen, H. Tsao, S. Liu, W. Chui, Parasitic-capacitance-insensitive current-mode filters
using operational transresistance amplifiers, IEE Proc. Circuits Devices and Systems 142 (3)
(1995) 186–192.
[3] J. Choma, Communication circuits: societal philosophies and evolving roles. IEEE Circuits
and Systems Society Newsletter 9(2) (1998)
[4] J. Brodie, A notch filter employing current differencing operational amplifier, International
Journal of Electronics 41 (5) (1976) 501–508.
[5] National Semiconductor Corp., Designing with a New Super Fast Dual Norton Amplifier,
Linear Applications Data Book, 1981.
[6] National Semiconductor Corp., The LM3900: A New Current Differencing ^ Quad of the
Input Amplifiers, Linear Applications Data Book, 1986
[7] J. Chen, H. Tsao, C. Chen, Operational transresistance amplifier using CMOS technology,
Electron. Lett. 28 (22) (1992) 2087–2088.
[8] H.O. Elwan, A.M. Soliman, CMOS differential current conveyors and applications for analog
VLSI, Analog Integrated Circuits and Signal Processing 11 (5) (1996) 35–45.
[9] M. Ismail, T. Fiez, Analog VLSI Signal and Information Processing, McGraw-Hill, New
York, 1994.
[10] H.O. Elwan, CMOS current mode circuits and applications for analog VLSI. M.Sc. thesis,
Cairo University, 1996.
[11] C. Mead, M. Ismail, Analog VLSI Implementation of Neural Systems, Kluwer Academic,
Boston, 1989.

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