8155{H)/8156(H)

2048-Bit Static MOS RAM with I/O Ports and Timer

DISTINCTIVE CHARACTERISTICS

• 256 word x 8-bits

• Single + 5 V power supply

• Completely static operation

• Internal address latch

• 2 programmable 8-bit 1/0 ports

• 1 programmable 6-bit 1/0 port

• Programmable l4-bit binary counterltimer

• Multiplexed address and data bus

GENERAL DESCRIPTION

The 8l55(H) and 8l56(H) are RAM and 1/0 chips to be used in the 8085AH MPU system. The RAM portion is designed with 2K bit static cells organized as 256 x 8. They have a maximum access time of 400ns to permit use with no wait states in 8085AH CPU. The 8l55H-2 and 8l56H-2 have maximum access times of 330ns for use with the 8085AH. The 1/0 portion consists of three general purpose

1/0 ports. One of the three ports can be programmed to be status pins, thus allowing the other two ports to operate in handshake mode.

A l4-bit programmable counterltimer is also included on chip to provide either a square wave or terminal count pulse for the CPU system depending on timer mode.

BLOCK DIAGRAM

10/11 B APORT~
V 8 PAa-PA7
.A t.. 256 X 8 ~ .,
ADa-A~ ,/ STAnC
" RAM B
PORTB
• .A ...
8 PBO"PB7
ALE ~

1m B
PORTC
WI!!' .A ...
6 PCa-Pes
RESET I TIMER I ~

TIMER ClK __f J ~VCC(+5v)
nMEROUf Vss(OV)
80003810
*8l55H = CE:, 8l56H = CE I publication # ~ Amendment

00934 C /0

Issue Date: ~rli 1987

3-246

co
CONNECTION DIAGRAM ....
'"
Top View '"
.-.
:J:
-
DIPs "
co
....
'"
01
PC3 vee .-.
:J:
PC4 PC2 -
TIMER IN PC1
RESET PCa
PCs PB7
TIMER OUT PB6
101M PBs
CE or c:;e PB4
1m PBJ
WR PB2
ALE PB1
ADo PBa
AD1 PA7
AD2 PA6
AD3 PAs
AD4 PA4
ADs PA3
ADs PA2
AD7 PA1
Vss PAa
CDOO5584 I
Note: Pin 1 is marked for orientation. 3-247

~ r------------------------------------------------------------------------------------,

~

if

.... GO .....

~ in

II)

....

GO

ORDERING INFORMATION

Commodity Products

AMO commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperatura Range

b. Package Type

c. Device Number

d. Speed Option

e. Optional Processing

~

_1-

B

e. OPTIONAL PROCESSING Blank - Standard Processing B - Burn~n

d. SPEED OPTION Blank - 2.5 MHz -2- 3 MHz

'------------- c. DEVICE NUMBER/DESCRIPTION 8155(H)/8156(H)

2048-Bil Static MOS RAM with 110 Ports and TImer

'------------------ b. PACKAGE TYPE

P - 4O-Pin Plastic DIP (PO 040) o - 40-Pin Ceramic DIP (CD 040)

'----------------------- •• TEMPERATURE RANGE'

Blank - Commercial (0 to + 70'C) I - Industrial (- 40 10 + 85'C)

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMO sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMO's standard military grade products.

Valid Combinations

'This device is also available in Military temperature range. See MaS Microprocessors and Peripherals Military Handbook (Order # 09275A/O) for electrical performance characteristics.

8155

8155H

8155-2

8155H-2

p. 0

8156

8156H

8156-2

8156H·2

8155B

8155HB

8155-2B

8155H-2B

0,10

8156B

8156HB

8156-2B

8156H-28

3-246

PIN DESCRIPTION
Pin No. Name 1/0 Description
4 RESET I The Reset signal is a pulse provided by the 8085AH to initialize the
system. Input high on this line resets the chip and initializes the three
lID ports to input mode. The width of RESET pulse should typically be
600ns. (Two 8085AH clock cycle times).
12-19 ADo·AD7 110 These are 3·state AddresslData lines that interlace with the CPU lower
8-bit AddresslData Bus. The 8·bit address is latched into the address
latch on the falling edge of the ALE. The address can be either for the
memory section or the 110 section depending on the polarity of the
101M input signal. The 8·bit data is either written into the chip or read
from the chip depending on the status of WRl"fE or READ input signal.
8 CE OR Cl: I Chip Enable: On the 8155(H) this pin is ~ and is active low. On the
8156(H) this pin is CE and is active high.
9 AD I Input Iowan this line with the Chip Enable active enables the ADo-7
buffers. If 101M pin is LOW, the RAM content will be read out to the
AD bus. Otherwise, the content of the selected lID port will be read to
the AD bus.
10 WR I Input Iowan this line with the Chip Enable active causes the data on
the AD lines to be written to the RAM or lID ports, depending on the
polarity of 101M.
11 ALE I Address Latch Enable: This oontrol signal latches the address on the
ADO.7 lines and the state of the Chip Enable and 101M into the chip at
the falling edge of ALE.
7 101M I 10/~ Select: This line selects the memory if LOW and selects
the 10 if HIGH.
21·28 PAQ·PA7 110 These 8 pins are general purpose lID pins. The inlout direction is
selected by programming the CommandlStatus Register.
29-36 PBo·PB7 lID These 8 pins are general purpose lID pins. The inlout direction is
selected by programming the CommandlStatus Register.
37·39, PCO'PCs lID These 6 pins can function as eithef input port, output port, or as control
I, 2, 5 signals for PA and PB. Programming is done through the CIS Register.
When PCo-s are used as control Signals, they will provide the following:
Pea·A INTR (Port A Interrupt)
PC,-A BF (Port A Buffer Full)
PC2"AS"m (Port A Strobe)
PC3-B INTR (Port B Interrupt)
PC4-B BF (Port B Buffer Full)
PCs'~ (Port B Strobe)
3 TIMER IN I This is the timer input to the counter timer.
6 TlMEFi 0 This pin is the timer output. This output can be either a square wave or
00f a pulse depending on the timer mode.
40 Vee + 5 volt supply.
20 VSS Ground reference. I

3-249

DETAILED DESCRIPTION The I/O portion contains four registers (Command/Status,
PAO.7, PBO·?, PCo.s). The IO/M (la/Memory Select) pin
The 8155(H)/8156(H) includes the following operational fea· selects the 1/0 or the memory (RAM) portion. Detailed
tures: descriptions of memory, 1/0 ports and timer functions will
• 2K Bit Static RAM organized as 256 x 8 follow.
• Two s-btt 1/0 ports (PA and PB) and one 6-bit 1/0 port (PC) The 8-bit address on the AD lines, the Chip Enable input, and
• 14·bit down counter 101M are all latched on chip at the falling edge of ALE. A LOW
on the 101M must be provided to select the memory section.

CE (Am8155/H) \ V \
OR
CE (Am81Y/H) I 1\ /

10111 \ lL ~

ADo-ADr X ADDRESS X OATA VALID
\

ALE

RDORYiA
WFOO8872
Note: For detailed timing diagram information, see ReadlWrite Cycle Timing Diagrams and Switching
Characteristics.
Figure 1. Memory Read/Write Cycle
PROGRAMMING INFORMATION 7 • 5 . 3 2 1 0
The Command/Status Register l not, TM~ 'E'1'"' 1..c.J. PCel zl p'J
The command register consists of eight latches, one for each L-,--' 12
Oemes PAo..7 } 0-' .....
bit. Four bits (0·3) define the mode of the ports. Two bits (4--5) Oelhte PBt>-7 1 - "'-
enable or disable the interrupt from Port C when il acts as
control port, and the last two bits (6-7) are for the timer. { 00 - ALT'
The CIS register contents can be altered at any lime by using Dofinoo PC,., I' ~ ALT2
01 = ALTg
the 1/0 address XXXXXOOO during a WRITE operation. The 10 = All 4
meaning of each bit of the command byte is defined as Enaole Port "'-
follows: Inlerrupt } I-En."
Enable Port B 0= Disable
... """.
00 = NOP - Do not affect COISlter operatioJ1.
01 = STOP - NQp if timer has no! S1arted: stop
COtIIling i1 the Iimel' is running .
10", STOP after Te - Stop imrneOia~ after
~ TIMER: CQW.4AND present rc is reached ~NOP it timer
has no! started).
11 = START - Load mode and CNT length and
SlartlTln'leOialelyaltefloading (it timer
is not presently running). If timer is rvnning,
SlaIt the new mode and em length irnrnediatety
alief present Te is reached.
DFOO3361
Figure 2. Command/Status Register Bit
Assignment 3·250

Reading the Command/Status Register

The status register consists of seven latches, one for each bit: six (0-5) for the status of the ports and one (6) lor the status of the timer.

The status of the timer and the I/O section can be polled by reading the CIS Register (Address XXXXXOOO). Status word format is shown below:

L- Port A In.rrupt Enable

L- Port Blrrterrupt Request

CD ...

CII

.2! :::r:

-.....

CD ... CII

~ :::r:

--

L Port B Butter Full/Empry (lnput/Outpul)

Control Input Mode Output Mode
BF LOW LOW
INTR LOW HIGH
S"FB I n put Control I nput Control The set and reset of INTR and BF with respect to m, vm and RD timing are shown in Strobed 1/0 Timing Diagrams.

To summarize, the register's assignments are:

L- Port B Inlerrupl Enabled

No. of
Address Pinouts Functions Bits
XXXXXOOO Internal CommandlStatus Register 8
XXXXXOOI PAO-? General Purpose 1/0 Port 8
XXXXX010 PBO-? General Purpose 1/0 Port 8
XXXXXOll PCO-5 General Purpose 1/0 Port or 6
Control Unes The following diagram shows how 1/0 Ports A and 8 are structured within the 8155(H) and 8156(H):

"Ii

D LATCIt_QI-----1...---.[> "---,

elK CUI

~

~

a WRfTI!L--+------I- .... 1...J H-@

~ ,...,POAT_+-ro--_--<>-"'=---+l_IIO_,,:,_'-_ ... )-<~ .=

I' I UUX o-ii-+ ........

~~:1_¥3)1 ....

~ j LATCH

READ PORT a 0

CLK

STI

L- Timefin~IThiebil:iS .. 1Ched1tigtl when terminal oount ill 1'NChed. It .. ... by fHding the CIS regiSter and by hardware res.t)

DF0033?O

Figure 3. Command/Status Register Status Word Format

Input/Output Section

The 1/0 section of the 8155(H)/8156(H) consists of four registers as described below.

• CommandlStatus Register (CIS) - This register is assigned the address XXXXXOOO. The CIS address serves a dual purpose.

When the CIS register is selected during WRITE operation, a command is written into the command register. The contents of this register are not accessible through the pins.

When the CIS (XXXXXOOO) is selected during a READ operation, the status information of the 1/0 ports and the timer becomes available on the ADO_? lines.

• PA Register - This register can be programmed to be either input or output ports, depending on the status of the contents of the CIS Register. Also, depending on the command, this port can operate in either the basic mode or the strobed mode (see timing diagram). The 1/0 pins assigned in relation to this register are pAc-? The address of this register is XXXXXOOI.

• PB Register - This register functions the same as PA Register. The 1/0 pins assigned are PBO-? The address of this register is XXXXX010.

• PC Register - This register has the address XXXXXOll and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control Signals for PA and PB properly programming the AD2 and AD3 bits of the CIS register.

When PCO-5 is used as a control port, 3 bits are assigned lor Port A and 3 for Port B. The first bit is an interrupt that the 8155(H) sends out. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. See Table 1.

When the' 'C" port is programmed to either AL T3 or AL T 4, the control signals for PA and PB are initialized as follows:

OUTPUT .......

I

AF003060

Figure 4. 8155(H)/8156{H) One Bit of Port A or Port B

Notes: 1. Output Mode 1

2. Simple Input Multiplexer Control

3. Strobed Input

4. = 1 for output mode. - 0 for input mode.

Read Port = (101M - 1) • (AD = 0) • (CE active) • (Port address selected)

Write Port = (101M = 1) • (WR = 0) • (CE active) • (Port

address selected)

Note in the diagram that when the 1/0 ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation when appropriately addressed.

Note also that the output latch is cleared when the port enters the input mode. The output latch cannot be loaded by writing to the port if the port is in the input mode. The result is that each time a port mode is changed from input to output, the output pins will go LOW. When the 8155(H)/8156(H) is RESET, the output latches are all cleared and all 3 ports enter the input mode.

When in the AL T 1 or AL T 2 modes, the bits of Port C are structured like the diagram above in the simple input or output mode, respectively.

Reading from an input port with nothing connected to the pins will provide unpredictable results.

3-251

Table 1. Table of Port Control Assignment

Pin ALT 1 ALT 2 ALT 3 ALT 4
PCO Input Port Output Port A INTR (Port A Interrupt) A INTR (Port A Interrupt)
PCl Input Port Output Port A BF (Port A Buffer Full) A BF (Port A Buffer Full)
PC2 Input Port Output Port A ~ (Port A Strobe) A g'f8 (Port A Strobe)
PC3 Input Port Output Port Output Port B I NTR (Port B Interrupt)
PC4 Input Port Output Port Output Port B BF (Port B Buffer Full)
PC5 Input Port Output Port Output Port B g'f8 (Port B Strobe) o

Timer Section

The Ii mer is a 14·bit down counter that counts Ihe "Iimer input" pulses and provides either a square wave or pulse when terminal count (TC) is reached.

The timer has the 1/0 address XXXXX100 for the low order byte of the register and the 1/0 address XXXXX10l for the high order byte of the register.

To program the timer, the COUNT LENGTH REG is loaded first, one byte at a time, by selecting the timer addresses. Bits o - 13 will specify the length of the next count. and bits 14 - 15 will specify the timer output mode. The value loaded into the count length register can have any value from 2H through 3FFFH in bits 0 - 13.

There are four modes to choose from:

o - Puts out LOW during second half of count

1 - Square wave

2 - Single pulse upon TC being reached

:3 - Repetitive single pulse every time TC is readied and automatic reload of counter upon TC being reached until instructed 10 stop by a new command loaded into CIS.

Bits 6 - 7 of the Command/Status Register Contents are used to start and stop the counter. There are four commands to choose from. (See the further description on Command/ Status Register.)

C/S7 C/S6

o 0

o 1

NOP - Do not affect counter operation. STOP - NOP if timer has not started; stop counting if the timer is running.

STOP AFTER TC - Stop immediately after present TC is reached (NOP if timer has not started).

START - Load mode and CNT length and start immediately after loading (if timer is not presently running). If timer is running, start the new mode and CNT length immediately after present TC is reached.

Te

TIMER MODE

MSB OS CNT LENGTH

TO

LSB OF CNT LENGTH

Figure 5. Timer Format

M2 and Ml define the timer mode as follows:

M2 M1 o 0 o

Puts out LOW during second half of count. Square wave, i.e., the period of the square wave equals the count length programmed with automatic reload at terminal count. Single pulse upon TC being reached. Automatic reload, i.e., single pulse every time TC is reached.

o

Note: In case of an asymmetric count, i.e., 9, larger half of the count will be HIGH, the larger count will stay active as shown in Figure 5.

WFOO7260

Note: 5 and 4 refer to the number of clock cycles in that time period.

Figure 6. Asymmetric Count

The counter in the BI55(H) is not initialized to any particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore, counting cannot begin following RESET until a START command is issued via the CIS register.

3-252

8185A Minimum Sy.tem Configuration

Figure 7 shows a minimum system using three chips, containing 256 Bytes RAM, 2K Bytes EPROM, 38 1/0 Pins, 1 Interval Timer, and 4 I nterrupt Levels.

I

As·15

-

-

en

en

'i

- .....

CD ....

.;

%

-

Figure 7. 8085AH Minimum System Configuration (Memory Mapped 1/0)

/ I-+------i

...

ALE

16K EPROM

8085AH

AF004690

ClK

WR Rii ALE CE~

RESET

READY

TIMER IN

RESET

_t

~ lATCHES

8158H

3-253

0010 flY~hlp ~y.\.m

Figure 8 shows a five-chip system containing 1.2SK Bytes RAM, 2K Bytes EPROM, 38 110 Pins, 1 Interval Timer, and 2 Interrupt Levels.

~/' 1" !
I~I- ~ PORT A W

I'll!
Ml ~
PORTB
AlE
8155H-2 fOV
DATAl PORTe
AOOR
.... v ..~
oV Tt.tER
.____. RESET OUT -
.
"8-1.18 AOOR :ow

I~ Ml ~
ADo·AD-, ADQP.IOATA AlE
CLK ... ~ PORT A
80ae 1(;:: "·'0
v 16K EPROM
...-- READY
MNiMi f--Ibc DATAl
ACOR
AlE I- t-l v ~
r01
- I- K>V
t-- t------ RESET PORTB
r-r- RST ®
'be ., ~LK WI\ I- r READY ~
I- 0l1oI I- i5lI
* READY f---- .--- I- Jsl1Lp~
! lin
RESET I-
8284
I~y~ ... ROY' I'IR
r Rli

~,
.... ALE
sl RESET leI- ~ 8K SRAM
(1)
I~I- CEo
I;f- ......
.100-7

1s 1
'v7V AF004700

Figure 8. 8088 Five-Chip System Configuration

3-254

AB50LUTE MAXIMUM RATINGS OPERATING RANGES
Storage Temperature ......................... -65°C to + 150°C Commercial (C) Devices
Vee with Respect to vss ...................... -0.5 to + 70 V Temperature (T A) .............................. ···· 0 to + 70·C
All Signal Voltages With Supply Voltage (Vecl
Respect to vss ............................. -0.5 V to +7.0 V 8155/8156 ........................................... 5 V ±5%
Power Dissipation ............................................. 1.5 W 8155H/8156H ...................................... 5 V ±10%
Stresses above those listed under ABSOLUTE MAXIMUM Supply Current (Ieel
RA TlNGS may cause permanent device failure. Functionality 815518156 ............................................. 180 mA
at or above these limits is not implied. Exposure to absolute 8155H/8156H ......................................... 125 mA
maximum ratings for extended periods may affect device Industrial (I) Devices
reliability. Temperature (TA) ............................... -40 to +85°C
Supply Voltage (Vecl .............................. 5 V ±10%
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameters Description Teat Conditions Min Max Units
VIL Input Low Voltage -0.5 0.8 Volts
VIH Input High Voltage 2.0 VCC+0.5 Volts
VOL Output Low Voltage IOL =2 mA 0.45 Volts
VOH Output High Voltage IOH = -400 I1A 2.4 Volts
IlL Input Leakage VIN = Vee to 0 V ±10 I1A
ILO Output Leakage Current 0.45 V ';;VOUT';;Vee ±10 I1A
8155. 8156 180 mA
Icc Vee Supply Current 8155H. 8156H 125 mA
8155H. 8155 +100 I1A
IlL (CE) Chip Enable Leakage 8156H. 8156 VIN = Vee to 0 V -100 I1A
SWITCHING TEST INPUT/OUTPUT WAVEFORM
2.'
2.0 +, r: 2.0
TEST POINTS
0.8 _; L 0.8
0.45
WFOO7340
Inputs are driven at 2.4 V for a Logic "1" and 0.45 V for a Logic "0". Timing measurements are made at
2.0 V for a Logic "1" and 0.8 V for a Logic "0".
SWITCHING TEST CIRCUIT
DEVICE
UNDER IJCL
TEST

-=-
TeOO2191
CL = 150pF
CL Includes Jig Capacitance CD

..... en en

~

-.....

CD ....

en en

:;

I

See Seeton 6 for Thermal CharactenstICs Information

3-255

SWITCHING CHARACTERISRICS over operating ranges unless otherwise specified
8155, 8156 8155-2, 8156-2
8155H, 8156H 8155H-2, 8156H-2
Parameters Description Min Max Min Max Units
tAL Address to Latch Setup Time 50 30 ns
tLA Address Hold Time after Latch 80 30 ns
tlC Latch to READ/WRITE Control 100 40 ns
tAD Valid Data Out Delay from READ Control 170 140 ns
tAD Address Stable to Data Out Valid 400 330 ns
tLD Latch to Data Out Valed 350 270 ns
twr WRITE to TIMER-IN (For Writes Which Start 360 200 ns
Counting)
tll Latch Enable Width 100 70 ns
tADF Data Bus Float After READ 0 100 0 80 ns
tCl READ/WRITE Control to Latch Enable 20 10 ns
tcu, WRITE Control to Latch Enable for CIS Register 125 125 ns
tee READ/WRITE Control Width 250 200 ns
tDW Data in to WRITE Setup Time 150 100 ns
two Data in Hold Time After WRITE 25 25 ns
tAV Recovery Time Between Controls 300 200 ns
twp WRITE to Port Output 400 300 ns
tPA Port Input Setup Time 70 50 ns
tAP Port Input Hold Time 50 10 ns
tS8F Strobe to Buffer Full 400 300 ns
Iss Strobe Width 200 150 ns
tABE READ to Buffer Empty 400 300 ns
tSI Strobe to INTR On 400 300 ns
tADI READ to INTR Off 400 300 ns
tpss Port Setup Time to Strobe 50 0 ns
tpHS Port Hold Time After Strobe 120 100 ns
tSBE Strobe to Buffer Empty 400 300 ns
tWBF WRITE to Buffer Full 400 300 ns
tWI WRITE to INTR Off 400 300 ns
tTL TIMER-IN to TIMER-OUT Low 400 300 ns
tTH TIMER-IN to TIMER-OUT High 400 300 ns
tADE Data Bus Enable from READ Control 10 10 ns
t, TIMER-IN Low Time 80 40 ns
t2 TIMER-IN High Time 120 70 ns 3-256

WF007273

SWITCHING WAVEFORMS

ALE

8155(H)/8156(H) Read Cycle

I

WFOO7283

8155(H)/8156(H) Write Cycle

3-257

SWITCHING WAVEFORMS (Cont'd.)

BF

Is ••

INTR

INPUT DATA

~PO~ ~~~ __ -+ __ ~~ __

WFOO7290
Strobed Input Mode
BF

mlm1

INTR
'WI
WIi

OUTPUT DATA
TO~
WFOO7301
Strobed Output Mode Input

Output

IRP1;:J

A6~~-1r-

INPUT ~ -"'I~\.. __

\ _{'~WP _-_--_

DATABUS' =====:x :_

OUTPUT

-----------------

D"TABUS- ------::x

------ .-------

WFOO7310

WFOO7320

"Data bus timing is shown in Read/Write Cycle diagrams.

Basic 1/0 Timing Waveform

3-258

TIiIIIfMIf (PULSE)

TiilP"lRiT (SQUARE WAVE)

SWITCHING WAVEFORMS (Cont'd.)

I

LOAD COUNTER FROM CLA --I

I 2 I 1 I

RELOAD COLWTER FROM CLR---l 3 I 2 I 1 I

"

TIMER IN

\ I

\ (NOTE 11 I

'- ~I

WFOO7330

Note 1: The timer output is periodic if in an automatic reload mode (M1 mode bit = 1).

Timer Output Waveform Countdown from 5 to 1

3·259