DMI ENGINEERING COLLEGE, ARALVAIMOZHI
DEPARTMENT OFCOMPUTER SCIENCE AND ENGINEERING
LESSON PLAN
NAME OF THE STAFF:M.PRINCY USHA
YEAR/BRANCH:III ECE
EC8552 COMPUTER ARCHITECTURE AND ORGANIZATION
UNIT I COMPUTER ORGANIZATION & INSTRUCTIONS 9
Basics of a computer system: Evolution, Ideas, Technology, Performance, Power wall,
Uniprocessors to Multiprocessors. Addressing and addressing modes. Instructions: Operations
and Operands, Representing instructions, Logical operations, control operations.
UNIT II ARITHMETIC 9
Fixed point Addition, Subtraction, Multiplication and Division. Floating Point arithmetic, High
performance arithmetic, Subword parallelism
UNIT III THE PROCESSOR 9
Introduction, Logic Design Conventions, Building a Datapath - A Simple Implementation
scheme - An Overview of Pipelining - Pipelined Datapath and Control. Data Hazards:
Forwarding versus Stalling, Control Hazards, Exceptions, Parallelism via Instructions.
UNIT IV MEMORY AND I/O ORGANIZATION 9
Memory hierarchy, Memory Chip Organization, Cache memory, Virtual memory. Parallel Bus
Architectures, Internal Communication Methodologies, Serial Bus Architectures, Mass storage,
Input and Output Devices.
UNIT V ADVANCED COMPUTER ARCHITECTURE 9
Parallel processing architectures and challenges, Hardware multithreading, Multicore and shared
memory multiprocessors, Introduction to Graphics Processing Units, Clusters and Warehouse
scale computers - Introduction to Multiprocessor network topologies.
TOTAL:45 PERIODS
OUTCOMES:
At the end of the course, the student should be able to
Describe data representation, instruction formats and the operation of a digital computer
Illustrate the fixed point and floating-point arithmetic for ALU operation
Discuss about implementation schemes of control unit and pipeline performance
Explain the concept of various memories, interfacing and organization of multiple
processors
Discuss parallel processing technique and unconventional architectures
TEXT BOOKS:
1. David A. Patterson and John L. Hennessey, ―Computer Organization and
Design‖, Fifth edition, Morgan Kauffman / Elsevier, 2014. (UNIT I-V)
2. Miles J. Murdocca and Vincent P. Heuring, ―Computer Architecture and
Organization: An Integrated approach‖, Second edition, Wiley India Pvt Ltd, 2015
(UNIT IV,V)
REFERENCES
1. V. Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, ―Computer
Organization―, Fifth edition, Mc Graw-Hill Education India Pvt Ltd, 2014.
2. William Stallings ―Computer Organization and Architecture‖, Seventh
Edition, Pearson Education, 2006.
Text Portions to be
Chapter /Page no.
Sl. (T)/Ref (R) Hrs covered on
Topics to be covered book
No. Unit needed CO
T R Hr Date
1
1. Basics of a computer system
Evolution, Ideas, T1 1.2/11,24 1
UNIT I COMPUTER ORGANIZATION &
2.
Technology,
1.6/28,1.7/
T1 1
3. Performance, Power wall 40-42
Uniprocessors to T1 1.8/43-45 1
INSTRUCTIONS
4.
Multiprocessors
Addressing and addressing T1 2
5.
modes.
Instructions: Operations and T1 2.2/63-72 2
6.
Operands,
Representing instructions 1
7. T1 2.5/80-86
Logical operations 1
8. T1 2.6/87-89
control operations. 1
9. T1 2.6/90-95
Fixed point Addition 3.2/178-
10. T1 1
181
11.
Fixed point Subtraction T1 3.2/178-
1
UNIT II ARITHMETIC
181
Fixed point Multiplication 3.3/183-
12. T1 1
188
Fixed point Division. 3.4/189-
13. T1 1
195
Floating Point arithmetic 3.5/196-
14. T1 3
199
High performance arithmetic 3.5/220-
15. T1 1
221
Subword parallelism 3.6/222-
16. T1 1
224
Introduction, Logic Design 4.2/248-
17. T1 1
Conventions 250
UNIT III THE PROCESSOR
18.
Building a Datapath T1 4.3/251-
1
258
A Simple Implementation 4.4/259-
19. T1 1
scheme 271
An Overview of Pipelining 4.5/272-
20. T1 1
285
Pipelined Datapath and 4.7/286-
21. T1 1
Control 302
22. Data Hazards: Forwarding T1 4.7/303- 1
versus Stalling 315
Control Hazards 4.8/316-
23. T1 1
324
Exceptions 4.9/325-
24. T1 1
331
Parallelism via Instructions 4.10/33234
25. T1 1
3
Memory hierarchy 5.2/378-
26. T1 1
UNIT IV MEMORY AND I/O ORGANIZATION
380
Memory Chip Organization 5.2/381-
27. T1 1
382
Cache memory 5.3/383-
28. T1 1
397
Virtual memory 5.7/427-
29. T1 1
453
Parallel Bus Architectures
30. T1 1
Internal Communication
31. T1 1
Methodologies
Serial Bus Architectures
32. T1 1
Mass storage
33. T1 1
Input and Output Devices
34. T1 1
Parallel processing 6.2/504-
35. T1 1
architectures and challenge 508
UNIT V ADVANCED COMPUTER
Hardware multithreading 6.4/516-
36. T1 2
518
ARCHITECTURE
Multicore and shared 6.5/519-
37. T1 2
memory multiprocessors 523
Introduction to Graphics 6.6/524-
38. T1 1
Processing Units 530
Clusters and Warehouse 6.7/531-
39. T1 2
scale computers 535
Introduction to
Multiprocessor network 6.8/536-
40. T1 1
topologies. 538
