A B C D E

COMPAL CONFIDENTIAL
1 MODEL NAME : AAL15 SKL-U+MEC1404 VC board 1

PCB NO : DA800140000
BOM P/N : 2015-07-09
GPIO MAP: REV : 1.0 (A00)
ZZZ
PCB @ : Nopop Component
DAZ1GG00100
PCB@
i3SKL2.3GR1@/i5SKL2.3GR1@/i7SKL2.5GR1@/SKL1.6G23R1@:CPU R1
PCB AAL15 LA-D071P LS-D071P/D072P/D073P
(LS-D071P/D072P/D073P/B844P/B845P/B915P)
i3SKL2.3GR3@/i5SKL2.3GR3@/i7SKL2.5GR3@/SKL1.6G23R3@:CPU R3
ZZZ
PCB
UMA@/DIS@ : UMA & DIS Type
2 DA800140000
MB@
DSX@/N_DSX@: DSX Mode 2

PCB 1G9 LA-D071P REV0 M/B 4 EMI@/ESD@/HDMI@EMI@/RF@ : EMI, ESD and RF Component
UC1
CPU R1 UC1
CPU R3 @EMI@/@ESD@/@RF@ : EMI, ESD and RF Nopop Component
i7-R1
SA000092P2L
i7SKL2.5GR1@
i7-R3
SA000092P3L
i7SKL2.5GR1@
CMC@ : XDP Component
FJ8066201930408 SR2EZ D1 2.5G BGA FJ8066201930408 SR2EZ D1 2.5G A31! CONN@ : Connector Component
100@/1000@/LAN_SW@ : LAN type
UC1 UC1

SA000092O2L SA000092O3L
i5-R1 i5-R3
i5SKL2.3GR1@

FJ8066201930409 SR2EY D1 2.3G BGA

i5SKL2.3GR3@

FJ8066201930409 SR2EY D1 2.3G A31!

3234@/3246@ : CODEC type
UC1

SA000092N3L
UC1

SA000092N4L
CRT@/HDMI@ : CRT/HDMI
3
i3-R1
i3SKL2.3GR1@
i3-R3
i3SKL2.3GR3@ TP_WAKE@/NOTP_WAKE@ : TouchPad wake 3

FJ8066201931104 SR2EU D1 2.3G BGA

UC1
FJ8066201931104 SR2EU D1 2.3G A31!
ODD@/NOZPODD@/ZPODD@ : ODD and Zero Power
SA00008Y40L
i5(2+3e)
ES0 SKL1.6G23@

FJ8066201930823 QJ57 J0 1.6G EXOR1@/MESOR1@ : GPU R1

EXOR3@/MESOR3@ : GPU R3
EXO@/MESO@ : GPU relative component
Layout Dell logo
2G_H@/2G_S@/2G_M@/4G_H@/4G_S@/4G_M@ : VRAM type
V_4G@ : 4G VRAM Support component
4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2014 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Cover Page
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Size Document Number Rev
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
REV: X00 1.0(A00)
PWB: 9HTP8
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-D071P
Date: Thursday, July 09, 2015 Sheet 1 of 64
A B C D E
 A B C D E

Tulip2_VC 14 Block Diagram DDR3L-SO-DIMM X2

Memory BUS (DDR3L)
BANK 0, 1, 2, 3
1 1333/1600MHz 1

DIS only P.20~P.21

USB2.0[1]
USB3.0[1]
USB1(USB3.0)
DDR3L P.30
VRAM(DDR3L) *8
1GB, 2GB (Reserve 4GB)
GPU PCIE x 4
USB2.0[2] Debug,IOB
P.30,P.39
P.61~P.62
INTEL
AMD USB2.0[3]
SMBUS Meso/Exo IOB P.30,P.39
Thermal
W83L771AWG-2 P.56~P.60
USB USB2.0[5]
CCD P.32

eDP Lane x 2
SKYLAKE_U USB2.0[6]
BT P.36
USB2.0[5]
2 eDP CONN USB2.0[7] Touch Screen 2
HDMI 1.4a DDI[1] P.32
USB2.0[7]
P.32
VGA/RTD2168-CGT
P.33~P.34
USB2.0[8] Card reader SD CARD
RTS5170-GR P.27
P.28

P.6~P.19 HD Audio I/F

I2C
Speaker
P.24

HDA CODEC Universal Jack

ALC3234-CG P.23 P.24

SATA(Gen3) x 1 Dig. MIC

Touch PAD

LPC
HDD P.24
PCIE[9] PCIE[5] P.38
P.35

3 LPC SATA(Gen1) x 1
3

debug ODD
port P.29 P.35
LAN
RTL8106E-CG / NGFF WLAN+BT SPI
RTL8111G-CG
P.25 AC 3160 P.36 W25R128FVSIQ
16MB P.8
USB2.0[6] Thermal
SMBUS
NCT7718 P.38
Transformer
P.26 KBC
PS2 MEC1404
Fan controller
P.29 APL5606AKI P.38 Fan CONN
P.38
RJ45 P.26

4
KB P.38 4

www.vinafix.com
KB-BL P.38 DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block diagram
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 2 of 64
A B C D E
 5 4 3 2 1

POWER STATES
Signal SLP SLP SLP ALWAYS SUS RUN
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# PLANE PLANE PLANE CLOCKS
State USB3.0-1 USB3.0 Port1 1 USB3.0 Port1

S0 (Full ON) / M0 HIGH HIGH HIGH ON ON ON ON

USB3.0-2 SSIC-1 N/A 2 IO/DB
USB3.0-3 SSIC-2 N/A 3 IO/DB
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON OFF OFF
USB3.0-4 N/A 4 N/A
S4 (Suspend to DISK) / M3 LOW LOW HIGH ON OFF OFF OFF USB3.0-5 PCIE-1 GPU 5 CCD

S5 (SOFT OFF) / M3 LOW LOW LOW ON OFF OFF OFF

USB3.0-6 PCIE-2 GPU 6 Card Reader
D D
PCIE-3 GPU 7 Touch Screen

PM TABLE PCIE-4 GPU 8 BT

+1.0V_PRIM
PCIE-5 WLAN 9 N/A
+RTC_CELL PCIE-6 LAN/GLAN 10 N/A
+1.35V_MEM
+1.8V_EDRAM
+1.0V_VCCSTG PCIE-7 SATA-0 SATA HDD
power +1.8V_PRIM
plane +VCC_CORE
+5VALWP +3VALW_PCH PCIE-8 SATA-1 SATA ODD
+VCC_GT
+3VALWP +1.0V_VCCST
+1.0VS_VCCIO PCIE-9 N/A
+5VALW
+VCC_SA
+3VALW PCIE-10 N/A
+VCC_EDRAM
State +1.0V_MPHYGT
+VCC_EOPIO PCIE-11 SATA-1* N/A
+1.0V_PRIM_CORE
+3.3V_ALW_DSW PCIE-12 SATA-2 N/A

S0 ON ON ON

S3 ON ON OFF

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist OFF OFF OFF

C C

Board ID & Model ID table

Item Pull-down Pull-up Voltage Board ID/Model ID
1 100 10.0 3.000 Pre-EVT

2 100 13.7 2.902 EVT

3 100 17.8 2.801 DVT1

4 100 22.1 2.703 DVT2

5 100 27.0 2.598

6 100 32.4 2.492
7 100 37.4 2.402
8 100 49.9 2.201
9 100 57.6 2.094
10 100 64.9 2.001
11 100 73.2 1.905
12 100 82.5 1.808
13 100 93.1 1.709
14 100 107.0 1.594
B B

15 100 120.0 1.500

16 100 137.0 1.392
17 100 154.0 1.299
18 100 200.0 1.100
19 100 232.0 0.994

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Port assignment
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 3 of 64
5 4 3 2 1
 5 4 3 2 1

PJP200 J13
CPU PWR SIO_SLP_S4# PJP202 DGPU_PWROK
RT8207PGQW EM5209VF
GPU PWR (PU200) +1.35VP +1.35V_MEM (U5602) +1.35V_MEM_GFX
Peripheral Device PWR PJP15

0.675V_DDR_VTT_ON PJP203 SIO_SLP_S3#

& Volume +1.0VS_VCCIO
+0.675VSP +0.675V_DDR_VTT SIO_SLP_S0#
TPS22961
ADAPTER (UZ19) +1.0V_VCCSTG_C PJP32

D MPHYP_PWR_EN +1.0V_VCCSTG D
TPS22961
(UZ20) +1.0V_MPHYGT
@+1.0V_PRIM_CORE_PG
@SIO_SLP_SUS# PJP302 PJP27
POK SIO_SLP_S4#
SYX196DQNC TPS22967
(PU301) +1VALWP +1.0V_PRIM (UZ21) +1.0V_VCCST_C +1.0V_VCCST

CHARGER 0ohm 0805

ISL95520HRZ +PWR_SRC (RC194) Volume +1.0V_PRIM_CORE
(PU703)
J11
DGPU_PWR_EN
EM5209VF
(U15) +0.95VSDGPU

0ohm 0805
USB_EN# (R5601) 5V_HDD_S0
AP22802BW5
PJP103 (U3504) USB30_VCCC
ALWON
BATTERY SY8286CRAC 0ohm 0805
(PU102) +5VALW (R5603) ODD_PWR_5V
USB_EN#
AP22802BW5
C
(U3505) USB20_VCCA SATA_ODD_PWRGT C
TPS2001CDGNR
VL (U5601)
SY8286BRAC PJP21
(PU100) EM5209VF SIO_SLP_S3#
RB551V-30 FUSE 1.1A_6V
(UZ2) +5VS (D5501) (F5501) 5V_HDMI_CRT_S0_R
ALWON

J14 FUSE 0.5A_13.2V

3D_CAM_EN (F6201) +5V_KB_BL
TPS22967DSGR
(UX1) +5V_CAM

EDP_VDD_EN
PJP102 PJP13 or LCDVDD_EN
ISL95857HRTZ AOZ5019QI SIO_SLP_S3# LCD_TST
(PU602) (PU604) EM5209VF RT9724GB
U23@
+3VALW (UZ2) +3VS (U5201) LCDVDD

PJP23
ISL95808HRZ AOZ5019QI AOZ5019QI
(PU606) (PU603) (PU605) PJP23 0ohm 0805
+3VLP (NON-DS3)
+3VALW_PCH (R5809) +3.3V_WLAN
BAS40C
(D2501) SY6288C10CAC PCH_ALW_ON
IMVP_VR_ON

PJP22 J12
B +RTC_VCC (UZ3) DGPU_PWR_EN B
EM5209VF
+5VS

+5VS

(DS3)
(U5602) +3VGS
PJP401
SIO_SLP_S3#
TPS62134ARGT
+RTC_CELL (PU401) Premium +1.0VS_VCCIO
+VCC_SA +VCC_CORE +VCC_GT
@SIO_SLP_SUS# PJP402
POK
TPS62134ARGT
(PU402) Premium +1.0V_PRIM_CORE
(DS3)
(NON-DS3)
PJP1200
ISL62771HRTZ SIO_SLP_S3#
(PU1100) TPS62134CRGT
(PU1200)U23@ +VCC_EDRAM

PJP1201
DGPU_PWR_EN

SIO_SLP_S3#
TPS62134CRGT
(PU1201)U23@ +VCC_EOPIO

@SIO_SLP_SUS# PJP502 J10

POK DGPU_PWR_EN
TPS62134ARGT EM5209VF
(PU501) +1.8VALWP +1.8V_PRIM (U15) +1.8VGS
A +VGA_CORE (DS3)
(NON-DS3) A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power rails
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 4 of 64
5 4 3 2 1
 5 4 3 2 1

1k ohm 2.2k ohm

+3VALW_PCH +3VALW_EC
1k ohm 2.2k ohm
R7 202
SMBCLK PCH_SMBCLK PCH_SMBCLK
R8 DMN66D 200 DIMMA
SMBDATA 1k ohm PCH_SMBDAT PCH_SMBDAT
202
D +3VALW_PCH D
1k ohm PCH_SMBCLK DIMMB
SKL-U R9
200
PCH_SMBDAT
SML0_SMBCLK
W2 2
SML0_SMBDATA PCH_SMBCLK
3 DP to VGA
DIS@
1k ohm 45.3k ohm PCH_SMBDAT

+3VALW_PCH DIS@ +3VGS

1k ohm 45.3k ohm
W3 U7
SML1CLK DMN66D GPU_THM_SMBCLK DMN66D VGA_SMB_CK3 VGA_SMB_CK3 dGPU
V3 U8
SML1DATA GPU_THM_SMBDAT VGA_SMB_DA3 VGA_SMB_DA3
MESO@
2.2k ohm 0 ohm 3

+3VS MESO@ VGA_SMB_CK3_R Thermal

U6 U7 0 ohm 4 (GPU)
2.2k ohm
VGA_SMB_DA3_R
I2C_SCL_TP
C C
GPU_THM_SMBCLK 2N7002 THM_SML1_CLK Thermal
I2C_SDA_TP
@ (SYSTEM)
2.2k ohm GPU_THM_SMBDAT THM_SML1_DATA

+3VALW_EC @
2.2k ohm

GPU_THM_SMBCLK

GPU_THM_SMBDAT
12 11

SMB02_CLK SMB02_DATA

4.7k ohm 2.2k ohm

TP_VDD +3VS
4.7k ohm 2.2k ohm
3
I2C_SCL_TP I2C_SCL_TP_Q
2N7002 2
B KBC I2C_SDA_TP I2C_SDA_TP_Q TP CONN
B
8

MEC 1404 4.7k ohm CLK_TP_SIO

7
TP_VDD DAT_TP_SIO
4.7k ohm
78
GPIO114
CLK_TP_SIO
79
GPIO115
DAT_TP_SIO

4.7k ohm

+3VALW_EC
4.7k ohm
9 100 ohm 6
SMB01_CLK
PBAT_CHG_SMBCLK 100 ohm CLK_SMB
SMB01_DATA 8 5 BATT
CONN
PBAT_CHG_SMBDAT DAT_SMB
0 ohm 3
A A

0 ohm 4 Charger

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMbus Block diagram
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 5 of 64
5 4 3 2 1
 5 4 3 2 1

+3VS
UC1A SKL-U

2 1 PCH_HDMI_CLK E55 C47

RC175 2.2K_0402_5% <33,34> HDMI_CRT_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TX0_DN <32>
2 1 PCH_HDMI_DATA <33,34> HDMI_CRT_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TX0_DP <32>
RC178 2.2K_0402_5% <33,34> HDMI_CRT_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TX1_DN <32>
2 1 WLAN_RADIO_DIS# <33,34> HDMI_CRT_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TX1_DP <32>
D RE439 10K_0402_5% <33> HDMI_DATA0# G53 DDI1_TXN[2] EDP_TXN[2] B45 D
<33> HDMI_DATA0 F56 DDI1_TXP[2] EDP_TXP[2] A47 +3VALW_PCH
<33> HDMI_CLK# G56 DDI1_TXN[3] EDP_TXN[3] B47
<33> HDMI_CLK DDI1_TXP[3] EDP_TXP[3] SIO_EXT_SMI# 2 1
C50 E45 Change "SIO_EXT_SMI#" 10K_0402_5% RC239
DDI2_TXN[0] DDI EDP_AUXN EDP_AUX_DN <32>
D50 EDP F45 PU to "+3VALW_PCH" For SW
DDI2_TXP[0] EDP_AUXP EDP_AUX_DP <32> Reserve "+3VS" PU
C52 +3VS
D52 DDI2_TXN[1] B52 2015/5/19 Jason
A50 DDI2_TXP[1] EDP_DISP_UTIL SIO_EXT_SMI# 2 @ 1
B50 DDI2_TXN[2] G50 PCH_DPB_AUXN 10K_0402_5% RC236
D51 DDI2_TXP[2] DDI1_AUXN F50 PCH_DPB_AUXN <34>
PCH_DPB_AUXP CPU_DP2_AUXN 2 @ 1
C51 DDI2_TXN[3] DDI1_AUXP E48 PCH_DPB_AUXP <34>
CPU_DP2_AUXN 100K_0402_5% RC179
DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXP PCH_DPB_AUXN 2 1
DDI2_AUXP G46 CPU_DP3_AUXN Jason 6/24 100K_0402_5% RC181
DISPLAY SIDEBANDS DDI3_AUXN F46 PAD~D @ T1
CPU_DP3_AUXP Short Pad
DDI3_AUXP PAD~D @ T2
PCH_HDMI_CLK L13
<33> PCH_HDMI_CLK PCH_HDMI_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_HDMI_HPD 1 @ 2 HDMI_CRT_DET PCH_DPB_AUXP 2 1
<33> PCH_HDMI_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 HDMI_CRT_DET <33,34>
L7 RC385 0_0402_5% 100K_0402_5% RC182
N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_AUXP 2 1
N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 CPU_CRT_HPD 1 SIO_EXT_SMI#
@ 2 <29>
100K_0402_5% @ RC180
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 RC386 0_0402_5% EDP_HPD 2 1
N11 GPP_E17/EDP_HPD EDP_HPD <32>
100K_0402_5% @ RC1
N12 GPP_E22/DDPD_CTRLCLK R12 L_BKLT_EN_EC HDMI_CRT_DET 2 1
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 L_BKLT_EN_EC <29> 100K_0402_5% @ RC312
RC2 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 L_BKLT_CTRL <32> L_BKLT_EN_EC 2 1
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN EDP_VDD_EN <32>
1 OF 20 100K_0402_5% RC390
SKL-U_BGA1356
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C

SKL_ULT
UC1I

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7 WLAN_RADIO_DIS#
CSI2_DP4 GPP_D4/FLASHTRIG WLAN_RADIO_DIS# <36>
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
SKL-U_BGA1356 9 OF 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (1/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 6 of 64
5 4 3 2 1
 5 4 3 2 1

DDR3L, Ballout for side by side(Non-Interleave)

SKL-U
UC1B SKL-U UC1C

AU53 DDR_A_CLK#0
<20> DDR_A_D[0..15] DDR0_CKN[0] DDR_A_CLK#0 <20> <20> DDR_A_D[16..31]
DDR_A_D0 AL71 AT53 DDR_A_CLK0 DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR0_DQ[0] DDR0_CKP[0] DDR_A_CLK0 <20> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_CLK#0 <21>
DDR_A_D1 AL68 AU55 DDR_A_CLK#1 DDR_A_D17 AF64 AN46 DDR_B_CLK#1
AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK#1 <20> AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK#1 <21>
DDR_A_D2 DDR_A_CLK1 DDR_A_D18 DDR_B_CLK0
AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK0 <21>
D DDR_A_D3 DDR_A_D19 DDR_B_CLK1 D
AL70 DDR0_DQ[3] BA56 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D4 DDR_A_CKE0 DDR_A_D20
AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE0 <20> AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56
DDR_A_D5 DDR_A_CKE1 DDR_A_D21 DDR_B_CKE0
AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE1 <20> AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE0 <21>
DDR_A_D6 DDR_A_CKE2 DDR_A_D22 DDR_B_CKE1
AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 PAD~D @ T3 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE1 <21>
DDR_A_D7 DDR_A_CKE3 DDR_A_D23 DDR_B_CKE2
DDR0_DQ[7] DDR0_CKE[3] PAD~D @ T4 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] PAD~D @ T5
DDR_A_D8 AR70 DDR_A_D24 AF70 AP53 DDR_B_CKE3
DDR0_DQ[8] DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] PAD~D @ T6
DDR_A_D9 AR68 AU45 DDR_A_CS#0 DDR_A_D25 AF68
DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#0 <20> DDR1_DQ[9]/DDR0_DQ[25]
DDR_A_D10 AU71 AU43 DDR_A_CS#1 DDR_A_D26 AH71 BB42 DDR_B_CS#0
DDR0_DQ[10] DDR0_CS#[1] DDR_A_CS#1 <20> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 <21>
DDR_A_D11 AU68 AT45 DDR_A_ODT0 DDR_A_D27 AH68 AY42 DDR_B_CS#1
AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT0 <20> AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_CS#1 <21>
DDR_A_D12 DDR_A_ODT1 DDR_A_D28 DDR_B_ODT0
AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <20> AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT0 <21>
DDR_A_D13 DDR_A_D29 DDR_B_ODT1
AU70 DDR0_DQ[13] BA51 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
DDR_A_D14 DDR_A_MA5 DDR_A_D30
AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA5 <20> AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDR_A_D15 DDR_A_MA9 DDR_A_D31 DDR_B_MA5
<20> DDR_A_D[32..47] BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA9 <20> <20> DDR_A_D[48..63] AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA5 <21>
DDR_A_D32 DDR_A_MA6 DDR_A_D48 DDR_B_MA9
AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA6 <20> AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA9 <21>
DDR_A_D33 DDR_A_MA8 DDR_A_D49 DDR_B_MA6
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA8 <20> DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA6 <21>
DDR_A_D34 AW63 AW52 DDR_A_MA7 DDR_A_D50 AP65 BB48 DDR_B_MA8
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_MA7 <20> DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA8 <21>
DDR_A_D35 AY63 AY55 DDR_A_BS2 DDR_A_D51 AN65 AP48 DDR_B_MA7
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BS2 <20> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_MA7 <21>
DDR_A_D36 BA65 AW54 DDR_A_MA12 DDR_A_D52 AN66 AP52 DDR_B_BS2
DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA12 <20> DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BS2 <21>
DDR_A_D37 AY65 BA54 DDR_A_MA11 DDR_A_D53 AP66 AN50 DDR_B_MA12
BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_MA11 <20> AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA12 <21>
DDR_A_D38 DDR_A_MA15 DDR_A_D54 DDR_B_MA11
BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA15 <20> AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_MA11 <21>
DDR_A_D39 DDR_A_MA14 DDR_A_D55 DDR_B_MA15
BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA14 <20> AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_MA15 <21>
DDR_A_D40 DDR_A_D56 DDR_B_MA14
AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_MA14 <21>
DDR_A_D41 DDR_A_MA13 DDR_A_D57
BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA13 <20> AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDR_A_D42 DDR_A_CAS# DDR_A_D58 DDR_B_MA13
AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CAS# <20> AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA13 <21>
DDR_A_D43 DDR_A_WE# DDR_A_D59 DDR_B_CAS#
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_WE# <20> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# <21>
DDR_A_D44 BB61 AU50 DDR_A_RAS# DDR_A_D60 AN61 AY44 DDR_B_WE#
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_RAS# <20> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_WE# <21>
DDR_A_D45 AY61 AU52 DDR_A_BS0 DDR_A_D61 AP61 AW44 DDR_B_RAS#
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BS0 <20> DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_RAS# <21>
DDR_A_D46 BA59 AY51 DDR_A_MA2 DDR_A_D62 AT60 BB44 DDR_B_BS0
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_MA2 <20> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BS0 <21>
DDR_A_D47 AY59 AT48 DDR_A_BS1 DDR_A_D63 AU60 AY47 DDR_B_MA2
<21> DDR_B_D[0..15] AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_BS1 <20> <21> DDR_B_D[16..31] AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_MA2 <21>
DDR_B_D0 DDR_A_MA10 DDR_B_D16 DDR_B_BS1
AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA10 <20> AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_BS1 <21>
DDR_B_D1 DDR_A_MA1 DDR_B_D17 DDR_B_MA10
AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA1 <20> AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA10 <21>
DDR_B_D2 DDR_A_MA0 DDR_B_D18 DDR_B_MA1
C AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA0 <20> AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA1 <21> C
DDR_B_D3 DDR_A_MA3 DDR_B_D19 DDR_B_MA0
BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA3 <20> AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA0 <21>
DDR_B_D4 DDR_A_MA4 DDR_B_D20 DDR_B_MA3
BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <20> AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA3 <21>
DDR_B_D5 DDR_B_D21 DDR_B_MA4
DDR0_DQ[37]/DDR1_DQ[5] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <21>
DDR_B_D6 BA37 AM70 DDR_A_DQS#0 DDR_B_D22 AP37
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] DDR_A_DQS#0 <20> DDR1_DQ[38]/DDR1_DQ[22]
DDR_B_D7 BB37 AM69 DDR_A_DQS0 DDR_B_D23 AR37 AH66 DDR_A_DQS#2
DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS0 <20> DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_A_DQS#2 <20>
DDR_B_D8 AY35 AT69 DDR_A_DQS#1 DDR_B_D24 AT33 AH65 DDR_A_DQS2
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDR_A_DQS#1 <20> DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_A_DQS2 <20>
DDR_B_D9 AW35 AT70 DDR_A_DQS1 DDR_B_D25 AU33 AG69 DDR_A_DQS#3
AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS1 <20> AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS#3 <20>
DDR_B_D10 DDR_A_DQS#4 DDR_B_D26 DDR_A_DQS3
AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS#4 <20> AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS3 <20>
DDR_B_D11 DDR_A_DQS4 DDR_B_D27 DDR_A_DQS#6
BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS4 <20> AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS#6 <20>
DDR_B_D12 DDR_A_DQS#5 DDR_B_D28 DDR_A_DQS6
BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS#5 <20> AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS6 <20>
DDR_B_D13 DDR_A_DQS5 DDR_B_D29 DDR_A_DQS#7
BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS5 <20> AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS#7 <20>
DDR_B_D14 DDR_B_DQS#0 DDR_B_D30 DDR_A_DQS7
BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS#0 <21> AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_A_DQS7 <20>
DDR_B_D15 DDR_B_DQS0 DDR_B_D31 DDR_B_DQS#2
<21> DDR_B_D[32..47] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_B_DQS0 <21> <21> DDR_B_D[48..63] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS#2 <21>
DDR_B_D32 AY31 AY34 DDR_B_DQS#1 DDR_B_D48 AU27 AR38 DDR_B_DQS2
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_B_DQS#1 <21> DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS2 <21>
DDR_B_D33 AW31 BA34 DDR_B_DQS1 DDR_B_D49 AT27 AT32 DDR_B_DQS#3
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_B_DQS1 <21> DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#3 <21>
DDR_B_D34 AY29 BA30 DDR_B_DQS#4 DDR_B_D50 AT25 AR32 DDR_B_DQS3
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_B_DQS#4 <21> DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS3 <21>
DDR_B_D35 AW29 AY30 DDR_B_DQS4 DDR_B_D51 AU25 AR25 DDR_B_DQS#6
BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS4 <21> AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS#6 <21>
DDR_B_D36 DDR_B_DQS#5 DDR_B_D52 DDR_B_DQS6
BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS#5 <21> AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS6 <21>
DDR_B_D37 DDR_B_DQS5 DDR_B_D53 DDR_B_DQS#7
BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 <21> AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS#7 <21>
DDR_B_D38 DDR_B_D54 DDR_B_DQS7
BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <21>
DDR_B_D39 DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D55 DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_A_PAR DDR_B_D56 AT22 DDR1_DQ[55] AN43
AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR PAD~D @ T7 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDR_B_D41 DDR_B_D57 DDR_B_PAR
DDR0_DQ[57]/DDR1_DQ[41] DDR1_DQ[57] DDR1_PAR PAD~D @ T8
DDR_B_D42 AY25 AY67 +DDR_VREF_CA DDR_B_D58 AU21 AT13 DDR_DRAMRST#
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR1_DQ[58] DRAM_RESET# DDR_DRAMRST# <20>
DDR_B_D43 AW25 AY68 +DDR_VREF_A_DQ DDR_B_D59 AT21 AR18 SM_RCOMP0
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR1_DQ[60] DDR_RCOMP[1]
DDR_B_D45 BA27 DDR_B_D61 AP22 DDR CH - B AU18 SM_RCOMP2
DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]

SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
B B

Buffer with Open Drain Output For VTT power control

DDR3 COMPENSATION SIGNALS
+1.35V_MEM
+3VS SM_RCOMP0 RC5 1 2 121_0402_1%
0.1U_0402_16V7K 2 1 CC57
1

SM_RCOMP1 RC6 1 2 80.6_0402_1%

UC14 RC123
1 5 100K_0402_5% SM_RCOMP2 RC7 1 2 100_0402_1%
NC VCC
DDR_VTT_CNTL 2
A
2

4
3 Y 0.675V_DDR_VTT_ON <44> CAD Note:
GND Trace width=12~15 mil, Spacing=20 mils
74AUP1G07GW_TSSOP5 Max trace length= 500 mil

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (2/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 7 of 64
5 4 3 2 1
 5 4 3 2 1

+3VS

SPI_MOSI= SPI_IO0 QC2A

SPI_MISO= SPI_IO1

2
DMN66D0LDW-7_SOT363-6
PCH EDS R0.7 p.235~236 SKL-U
UC1E SMBCLK 6 1
PCH_SMBCLK <20,21,34>
SPI - FLASH

5
SMBUS, SMLINK QC2B
PCH_SPI_CLK_R1 AV2 DMN66D0LDW-7_SOT363-6
PCH_SPI_D1_R1 AW3 SPI0_CLK R7 SMBCLK SMBDATA 3 4
SPI0_MISO GPP_C0/SMBCLK PCH_SMBDAT <20,21,34>
PCH_SPI_D0_R1 AV3 R8 SMBDATA
PCH_SPI_D2_R1 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 PCH_SMB_ALERT# +3VALW_PCH
PCH_SPI_D3_R1 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0_R1 AU3 SPI0_IO3 R9 SML0_SMBCLK
D AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA D
SPI0_CS1# GPP_C4/SML0DATA

2
AU1 W1 GPP_C5 QC5A DSX@
+3VS SPI0_CS2# GPP_C5/SML0ALERT# DMN66D0LDW-7_SOT363-6
W3 SML1CLK SML1CLK 1 6
SPI - TOUCH GPP_C6/SML1CLK V3 SML1DATA GPU_THM_SMBCLK <29,38,57>
GPP_C7/SML1DATA
1

5
ONE_DIMM# M2 AM7 GPP_B23 QC5B DSX@
10K_0402_5%

M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# DMN66D0LDW-7_SOT363-6

@ RC267

J4 GPP_D2/SPI1_MISO SML1DATA 4 3
GPP_D3/SPI1_MOSI GPU_THM_SMBDAT <29,38,57>
V1
V2 GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
2

+3VS M1 LPC N_DSX@

ONE_DIMM# GPP_D0/SPI1_CS# AY13 SML1CLK 1 2 GPU_THM_SMBCLK
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_LAD0 <29>
RC0801 N_DSX@ 0_0402_5%
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_LAD1 <29>
1

BB13 SML1DATA 1 2 GPU_THM_SMBDAT

10K_0402_5%

10K_0402_5% LPC_LAD2 <29>

G3 GPP_A3/LAD2/ESPI_IO2 AY12 RC0802 0_0402_5%
RC13

CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_LAD3 <29>

G2 BA12
RC268

G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT#/LPCPD# LPC_LFRAME# <29>

CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# EMI@ RC16 1 2 22_0402_5%
CLK_DP2VGA <34>
2

+3VS
AW13 AW9 PCI_CLK_LPC0 EMI@ RC18 1 2 22_0402_5%
<29> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_PCI_LPC_MEC <29>
PCI_CLK_LPC1 EMI@ RC22 1 2 22_0402_5%
AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# CLK_PCI_LPDEBUG <29> PCH_SMBDAT 2 1
<29> SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <29>
2.2K_0402_5% RN19
DIMM Detect +3VS RC21 1 2 10K_0402_1% PCH_SMBCLK 2 1
SKL-U_BGA1356 5 OF 20 2.2K_0402_5% RN20
+3VALW_PCH
HIGH 1 DIMM
LOW 2 DIMM
SMBCLK 1 2
RC355 1 CMC@ 2 1K_0402_1% PCH_SPI_D0_R1 RC12 1K_0402_5%
<14> XDP_SPI_SI 1 2
SMBDATA
RC354 1 CMC@ 2 1K_0402_1% PCH_SPI_D2_R1 Reserve for RF RC14 1K_0402_5%
C <14> XDP_SPI_IO2 1 2 C
SML1CLK
RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP CLK_PCI_LPC_MEC 2 1 RC15 1K_0402_5%
12P_0402_50V8J @EMI@ SML1DATA 1 2
CC4 RC17 1K_0402_5%
PCH_SPI_CLK_0_R SML0_SMBCLK 1 2
CLK_PCI_LPDEBUG 2 1 RC19 1K_0402_5%
12P_0402_50V8J @EMI@ SML0_SMBDATA 1 2
2

CC5 RC20 1K_0402_5%

33_0402_5%

+3.3V_SPI SUS_STAT#/LPCPD# 1 2
RC29
@EMI@

@ RC369 8.2K_0402_5%
PCH_SPI_D1_R1 RC317 1 2 33_0402_5% PCH_SPI_D1_0_R
PCH_SPI_D1_0_R <29> +3VS
PCH_SPI_D0_R1 RC318 1 2 33_0402_5% PCH_SPI_D0_0_R
PCH_SPI_D0_0_R <29>
1

1 2 PCH_SPI_CS#0_R1 PCH_SPI_CLK_R1 RC319 1 2 33_0402_5% PCH_SPI_CLK_0_R

RC339 4.7K_0402_5% PCH_SPI_D3_R1 RC320 1 2 33_0402_5% PCH_SPI_D3_0_R PCH_SPI_CLK_0_R <29>
33P_0402_50V8J

1 2 PCH_SPI_D2_R1 PCH_SPI_D2_R1 RC327 1 2 33_0402_5% PCH_SPI_D2_0_R

2

RC30 1K_0402_5% CLKRUN# 1 2

CC8
@EMI@

1 @ 2 PCH_SPI_D3_R1 RC27 8.2K_0402_5%

RC31 1K_0402_5%
1

1 2 PCH_SPI_D3_R1
RC316 1K_0402_5% +3VALW_PCH

PCH_SMB_ALERT# 1 @ 2
RC23 8.2K_0402_5%

TLS CONFIDENTIALITY
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the HIGH ENABLE
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI LOW(DEFAULT) DISABLE
B B
flash device on the platform has HOLD functionality disabled by default.
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms +3VALW_PCH
with ES and SKL S/H platforms with pre-ES1/ES1 samples.

GPP_C5 1 @ 2
+3.3V_SPI RC25 10K_0402_5%

CC9
1 2
EC interface
Short Pad
128Mb Flash ROM 0.1U_0402_25V6 HIGH ESPI
UC5
PCH_SPI_CS#0_R1 RC37 1 @ 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 LOW(DEFAULT) LPC
<29> PCH_SPI_CS#0_R1 PCH_SPI_D1_0_R RC329 1 2 15_0402_1% PCH_SPI_D1_0_R3 2 /CS VCC 7 PCH_SPI_D3_0_R3 RC331 1 2 15_0402_1% PCH_SPI_D3_0_R
PCH_SPI_D2_0_R RC330 1 2 15_0402_1% PCH_SPI_D2_0_R3 3 IO1 IO3 6 PCH_SPI_CLK_0_R3 RC332 1 2 15_0402_1% PCH_SPI_CLK_0_R
4 IO2 CLK 5 PCH_SPI_D0_0_R3 RC333 1 2 15_0402_1% PCH_SPI_D0_0_R
GND IO0 +3VALW_PCH
W25Q128FVSIQ_SO8 Modify Value to 150k for WW52 MOW
2015/03/03 Jason
Main: GPP_B23 1 CMC@ 2
RC365 150K_0402_5%
SA00005VV10, S IC FL 128M W25Q128FVSIQ SOIC8P SPI ROM
2nd:
SA00008KK00, S IC FL 128M GD25B128CSIGR SOP 8P 3.3V EXI BOOT STALL BYPASS
SA00006PD00, S IC FL 128M EN25QH128A-104HIP SOP 8P
Jason 2015/03/04 HIGH ENABLE
LOW(DEFAULT) DISABLE
A A

DELL CONFIDENTIAL/PROPRIETARY

www.vinafix.com
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (3/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 8 of 64
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH

UC1F SKL-U
KB_DET# 1 2
LPSS ISH
RC288 10K_0402_5%
RTC_DET# 1 2
AN8 RC384 10K_0402_5%
AP7 GPP_B15/GSPI0_CS# P2 CAM_DETECT SIO_EXT_WAKE# 1 2
GPP_B16/GSPI0_CLK GPP_D9 CAM_DETECT <64>
VRAM_ID1 AP8 P3 DGPU_HOLD_RST# RC387 10K_0402_5%
GPP_B17/GSPI0_MISO GPP_D10 DGPU_HOLD_RST# <56>
NRB_BIT AR7 P4
GPP_B18/GSPI0_MOSI GPP_D11 P1 RTC_DET#
AM5 GPP_D12 RTC_DET# <22>
DBC_EN
<32> DBC_EN AN7 GPP_B19/GSPI1_CS# M4
D 3D_CAM_EN_PCH D
FW_UPDATE_PCH AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL
GPP_B22/GSPI1_MOSI N1 DGPU_HOLD_RST# 1 2
AB1 GPP_D7/ISH_I2C1_SDA N2 RC383 10K_0402_5%
BLUETOOTH_EN AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
<36> BLUETOOTH_EN GPP_C9/UART0_TXD
W4 AD11
+3VS <35> SATA_ODD_PWRGT GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA
BOARD_ID2 AB3 AD12
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
UART_2_CRXD_DTXD AD1
For 3D-CAM & always POP UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD U1 DGPU_PWR_EN
2015/Jason AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 DGPU_PWR_EN <40,52>
<29> SIO_EXT_WAKE# AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
LPSS_UART2_CTS#
1 2 CAM_DETECT GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 +3VS
RC293 10K_0402_5% GPP_D16/ISH_UART0_CTS#/SML0BALERT#
U7 AC1
<38> I2C_SDA_TP GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD
1 2 BLUETOOTH_EN U6 AC2 Add RC359 10kohm PU and
<38> I2C_SCL_TP GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD

1
RC292 10K_0402_5% AC3 Change RC358 to UN-POP for SW request
U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
2 1 UART_2_CRXD_DTXD U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS# RC359
RC62 49.9K_0402_1% GPP_C19/I2C1_SCL AY8 PROJECT_ID1
2015/04/28 Jason 10K_0402_5%
AH9 GPP_A18/ISH_GP0 BA8 PROJECT_ID2
GPP_F4/I2C2_SDA GPP_A19/ISH_GP1

2
2 1 UART_2_CTXD_DRXD AH10 BB7 DGPU_PWR_EN
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 KB_DET# <38>
RC63 49.9K_0402_1% BOARD_ID3
GPP_A21/ISH_GP3

2
AH11 AY7
2 1 LPSS_UART2_CTS# AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 VRAM_ID2 @
RC382 49.9K_0402_1% GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 RC358
GPP_A12/BM_BUSY#/ISH_GP6 PANEL_SIZE_ID <32>
AF11 10K_0402_5%
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

1
SKL-U_BGA1356 6 OF 20
C C

+3VS
3D@
3D_CAM_EN_PCH 1 2
3D_CAM_EN <29,64>
DX2 RB751S40T1G_SOD523-2

1
3D@
FW_UPDATE_PCH 1 2 @ @
FW_UPDATE <29,64>
RC370 RC372
DX3 RB751S40T1G_SOD523-2 10K_0402_5% 10K_0402_5%
For 3D-CAM 2015/Jason

2
PROJECT_ID1
PROJECT_ID2
Reserve for TULIP/VanGogh MB switch

1
@ @
RC371 RC373
10K_0402_5% 10K_0402_5%
+3VALW_PCH

2
1 2 NRB_BIT
Win7 Debug solution
@ RC186 4.7K_0402_5%
Option 2 : For Open Chassis Platforms +3VS
NO REBOOT STRAP
+5VALW JWDB1
HIGH No REBOOT 6
LOW(DEFAULT) REBOOT ENABLE GND

1
5
GND @ @
B
Weak IPD 4 RC374 RC376 B
UART_2_CTXD_DRXD 3 4 10K_0402_5% 10K_0402_5%
UART_2_CRXD_DTXD 2 3
2

2
1 BOARD_ID2
1 BOARD_ID3
CVILU_CI1804M1VRA-NH
Reserve for MB Platform(SKL) switch

1
CONN@
@ @
RC375 RC377
10K_0402_5% 10K_0402_5%

2
+3VS

1
@ @
RC378 RC379
10K_0402_5% 10K_0402_5%
2

2
VRAM_ID1
VRAM_ID2
Reserve for VRAM Type switch
1

1
@ @
RC380 RC381
A 10K_0402_5% 10K_0402_5% A
2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (4/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 9 of 64
5 4 3 2 1
 5 4 3 2 1

PEG_HTX_C_GRX_P[0..3]
<56> PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3]
<56> PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3]
<56> PEG_GTX_C_HRX_P[0..3] UC1H SKL-U
PEG_GTX_C_HRX_N[0..3]
<56> PEG_GTX_C_HRX_N[0..3]
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN USB3_PRX_CTX_N0 <30>
G8
H13 USB3_1_RXP C13 USB3_PRX_CTX_P0 <30>
PEG_GTX_C_HRX_P0
D PEG_GTX_C_HRX_N0 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_CRX_N0 <30> ---> Port 1, USB3.0 D
PEG_HTX_C_GRX_P0 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_CRX_P0 <30>
PEG_HTX_C_GRX_N0 A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
PEG_GTX_C_HRX_P1 G11 USB3_2_RXP/SSIC_1_RXP B13
PEG_GTX_C_HRX_N1 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
PEG_HTX_C_GRX_P1 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
PEG_HTX_C_GRX_N1 C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB3_CRX_DTX_N3 <64>
H10
H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_CRX_DTX_P3 <64>
PEG_GTX_C_HRX_P2
GPU ---> PEG_GTX_C_HRX_N2 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_CTX_DRX_N3 <64> 3D CAMERA
PEG_HTX_C_GRX_P2 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_CTX_DRX_P3 <64>
PEG_HTX_C_GRX_N2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PEG_GTX_C_HRX_P3 G15 USB3_4_RXP C15
PEG_GTX_C_HRX_N3 F15 PCIE4_RXN USB3_4_TXN D15
PEG_HTX_C_GRX_P3 B19 PCIE4_RXP USB3_4_TXP
PEG_HTX_C_GRX_N3 A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB_PN1 <30>
AB10
<36> PCIE_PRX_WLANTX_N5
F16 USB2P_1 USB_PP1 <30> -----> Port 1, USB3.0 (Port 1)
E16 PCIE5_RXN AD6
<36> PCIE_PRX_WLANTX_P5 PCIE5_RXP USB2N_2 USB_PN2 <30>
C19 AD7
WLAN ---> <36> PCIE_PTX_WLANRX_N5_C D19 PCIE5_TXN USB2P_2 USB_PP2 <30> -----> Port 2, USB2.0 (IOB)
<36> PCIE_PTX_WLANRX_P5_C PCIE5_TXP AH3
USB2N_3 USB_PN3 <30>
G18 AJ3
<25>
<25>
PCIE_PRX_LANTX_N6
PCIE_PRX_LANTX_P6
F18 PCIE6_RXN USB2P_3 USB_PP3 <30> -----> Port 3, USB2.0 (IOB)
D20 PCIE6_RXP AD9
GLAN ---> <25> PCIE_PTX_LANRX_N6 C20 PCIE6_TXN USB2N_4 AD10
<25> PCIE_PTX_LANRX_P6 PCIE6_TXP USB2P_4
F20 AJ1
<35> SATA3_PRX_HDDTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB_PN5 <32>
E20 AJ2
SATA HDD ---> <35> SATA3_PRX_HDDTX_P0
B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB_PP5 <32> ----->CCD
C <35> SATA3_PTX_HDDRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 C
<35> SATA3_PTX_HDDRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB_PN6 <27>
AF7
<35> SATA_PRX_ODDTX_N1 G21 USB2P_6 USB_PP6 <27> -----> Card Reader
F21 PCIE8_RXN/SATA1A_RXN AH1
SATA ODD ---> <35> SATA_PRX_ODDTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB_PN7 <32>
<35> SATA_PTX_ODDRX_N1 D21 AH2
<35> SATA_PTX_ODDRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB_PP7 <32> -----> Touch Screen
PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USB_PN8 <36>
E22 AF9
E23 PCIE9_RXN USB2P_8 USB_PP8 <36> -----> BT
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10 +3VALW_PCH
C23 PCIE10_TXN AB6 USBCOMP RC44 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC366 1 2 1K_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC393 1 2 1K_0402_5% RPC3
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC#6_7 4 5
+3VS PCIE_RCOMPP A9 USB_OC#0_1 USB_OC#0_1 3 6
D56 GPP_E9/USB2_OC0# C9 USB_OC#0_1 <31> 2 7
USB_OC#2_3 USB_OC#2_3
<14> XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC#2_3 <31> 1 8
USB_OC#4_5 Reserve USB_OC#4_5
RC245 1 2 10K_0402_5%<14> XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC#6_7 Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3# 10K_8P4R_5%
E28 J1
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SIO_EXT_SCI# HDD_DEVSLP <35>
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_SCI# <29>
D24 J3 SATA_ODD_DA# +3VS
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SATA_ODD_DA# <35>
E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATA_ODD_PRSNT# SATA_LED# 1 2
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA_ODD_PRSNT# <35>
RC248 10K_0402_5%
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SIO_EXT_SCI# 1 2
B PCIE12_TXP/SATA2_TXP H1 SATA_LED# RC237 10K_0402_5% B
GPP_E8/SATALED# SATA_LED# <29,37> SATA_ODD_DA# 2 1
RC356 10K_0402_5%
SKL-U_BGA1356 8 OF 20

+3VALW_PCH

SATA_ODD_PRSNT# 1 2
RC246 10K_0402_5%

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (5/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 10 of 64
5 4 3 2 1
 5 4 3 2 1

CC21
1 2

12P_0402_50V8J

2
1M_0402_1%

3
4
UC1J SKL_ULT

RC46
YC1
CLOCK SIGNALS SUSCLK 24MHZ_12PF_X3G024000DC1H
SUSCLK <36>

1
2
D42 SUSCLK 1 2 RC295
<56> CLK_PEG_VGA CLKOUT_PCIE_N0
C42 RC48 1K_0402_5% XTAL24_IN 0_0402_5% CC22
<56> CLK_PEG_VGA# CLKOUT_PCIE_P0
AR10 XTAL24_OUT 1 @ 2 XTAL24_OUT_R 1 2
GPU---> <57> PEG_CLKREQ#
RC189 1 2 10K_0402_5% GPP_B5/SRCCLKREQ0#
+3VS
B42 12P_0402_50V8J
D <36> CLK_PCIE_WLAN_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N
Short Pad D
<36> CLK_PCIE_WLAN_P1 AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 PAD~D @ T4943
WLAN---> CLK_ITPXDP_P Jason 6/24
<36> CLK_PCIE_WLAN_REQ# 1 2 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P PAD~D @ T4944
+3VS RC47
D41 BA17 SUSCLK
<25> CLK_PCIE_LAN_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK PAD~D @ T4939
CC23
<25> CLK_PCIE_LAN_P2 CLKOUT_PCIE_P2
AT8 E37 XTAL24_IN PCH_RTCX1 1 2
LAN---> <25> CLK_PCIE_LAN_REQ#
RC50 1 2 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT PCH_RTCX2
+3VS XTAL24_OUT
D40 6.8P_0402_50V8C
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5

1
RC59 1 @ 2 10K_0402_5% AT10 RC52 2.7K_0402_1% YC2
+3VS GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 RC54 32.768KHZ_9PF_X1A000141000200
B40 RTCX1 AM20 PCH_RTCX2 20ppm / 9pF
CLKOUT_PCIE_N4 RTCX2 10M_0402_5%
A40 ESR <50kohm (MAX)
CLKOUT_PCIE_P4

2
RC51 1 @ 2 10K_0402_5% AU8 AN18 SRTCRST# RC56 1 2 20K_0402_5% RC296
+3VS GPP_B9/SRCCLKREQ4# SRTCRST# +RTC_CELL

1
AM16 0_0402_5% CC26
E40 RTCRST# CC24 1 2 1U_0402_6.3V6K 1 @ 2 PCH_RTCX2_R 1 2
E38 CLKOUT_PCIE_N5
RC190 1 @ 2 10K_0402_5% AU7 CLKOUT_PCIE_P5 Jason 6/24 6.8P_0402_50V8C
+3VS GPP_B10/SRCCLKREQ5# PCH_RTCRST# RC57 1 2 20K_0402_5%
Short Pad
CC25 1 2 1U_0402_6.3V6K SJ10000LV00, S CRYSTAL 32.768KHZ 12.5PF 9H03200042
32.768kHz/12.5pF with 18pF
SKL-U_BGA1356 10 OF 20 SJ10000PW00, S CRYSTAL 32.768KHZ 9PF X1A000141000200
+3VS 32.768kHz/9pF with 5.6pF
1 2
1 2 Change CC23, CC26 for YC2 2nd source.
<29> RTCRST_ON
Jason 5/29
5

1
Change CC23, CC26 CPN for Material Shortage.
SHORT PADS~D

2
PCH_PLTRST# 1 R1902 Jason 6/2
P

IN1 4 PCH_PLTRST#_EC CMOS1 JP@ Change CC23, CC26 for YC2 2nd source.

G
O PCH_PLTRST#_EC <25,29,32,36,56> 10KR2J-3-GP
2 Jason 7/6
IN2 CMOS1 must take care short & touch risk on layout placement
1
G

UC7 3 1

2
C SN74AHC1G08DCKR_SC70-5 RC65 C

D
CMOS1
3

100K_0402_5%
Q1901 Always Open
& Not Solder
2

2N7002K_SOT23-3

+3.3V_ALW_DSW 2015/5/19 Modify

Jason +RTC_CELL
1 @ 2 PCH_PCIE_WAKE# +3VALW
RC67 1K_0402_5%
2 1 H_CPUPWRGD INTRUDER# 1 2
CC1101 100P_0402_50V8J 1 2 LAN_WAKE# SIO_SLP_LAN# 1 2 RC69 330K_0402_5%
@ESD@ RC70 10K_0402_5% @ RC68 10K_0402_5%
+3VALW
+3VS +3.3V_ALW_DSW
Close to CPU side 1 2
8/21 can change to 10K for merge to RP
1 2
SYS_RESET# VRALERT#
RC291 10K_0402_5% PCH_BATLOW# 1 2 RC73 10K_0402_5%
RC72 8.2K_0402_5%
2 @ 1 PCH_DPWROK AC_PRESENT 1 2 +3.3V_ALW_DSW
RC1101 100K_0402_5% RC243 10K_0402_5% Buffer with Open Drain Output For VTT power control
+3VALW_PCH SIO_PWRBTN# 2 @ 1
RC1102 100K_0402_5% +3VALW
1 2 ME_SUS_PWR_ACK UC1K SKL-U
@ RC74 10K_0402_5% 0.1U_0402_16V7K 2 1 CC299
SYSTEM POWER MANAGEMENT
AT11 UC17
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17> 1 5
SIO_SLP_S3# RC1103
AN10 GPD4/SLP_S3# BA16 SIO_SLP_S3# <17,29,40,41,46,51> NC VCC
PCH_PLTRST# 10K_0402_1%
<14> PCH_RSMRST#_Q B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,29,44> 1 2 2
SYS_RESET# SIO_SLP_S3#
B 1 2 10K_0402_5% AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <42> A 4 B
RC75 PCH_RSMRST#_Q ALL_SYS_PWRGD
RSMRST# Y

1
AN15 SIO_SLP_SUS#_R RC76 1 2 43K_0603_1% 3
H_CPUPWRGD_R RC77 1 @ 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_LAN# SIO_SLP_SUS# <29,45,46,47> CC1103 GND
T9 @ PAD~D PROCPWRGD SLP_LAN# PAD~D @ T4938
H_VCCST_PWRGD RC78 1 2 60.4_0402_1% VCCST_PWRGD B65 BB17 SIO_SLP_WLAN# 1U_0402_6.3V6K 74AUP1G07GW_TSSOP5
VCCST_PWRGD GPD9/SLP_WLAN# PAD~D @ T4945

2
AN16 SIO_SLP_A#
B6 GPD6/SLP_A# PAD~D @ T4937
<29> SYS_PWROK BA20 SYS_PWROK BA15
<29> RESET_OUT# PCH_PWROK GPD3/PWRBTN# SIO_PWRBTN# <29>2
RC344 1 DSX@ 2 0_0402_5% PCH_DPWROK BB20 AY15 AC_PRESENT 1
<43,45,46,47> POK DSW_PWROK GPD1/ACPRESENT ACAV_IN <29,42>
PCH_RSMRST#_Q RC216 1 2 0_0402_5% AU13 PCH_BATLOW# RB751S40T1G_SOD523-2 DZ4
N_DSX@ AR13 GPD0/BATLOW#
<29> 1ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK
Buffer with Open Drain Output For VTT power control
2 SUSACK#_R AP11
<29> SUSACK# GPP_A15/SUSACK# +3VALW +1.0V_VCCST
RC346 DSX@ 0_0402_5% AU11 PME#
GPP_A11/PME# PAD~D @ T115
2015/5/19 Modify RC395 1 2 0_0402_5% PCH_PCIE_WAKE# BB15 AP16 INTRUDER#
<25,29> PCIE_WAKE# WAKE# INTRUDER# 0.1U_0402_16V7K 2 CC298
Jason RC391 1 @ 2 0_0402_5% LAN_WAKE# AM15 1
<29> EC_WAKE# GPD2/LAN_WAKE#

2
AW17 AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# MPHYP_PWR_EN <18> UC16 RC71
GPD7/RSVD GPP_B2/VRALERT# 1 5
NC VCC 1K_0402_5%
connect to VCCMPHYGTAON_1P0 enable pin
SKL-U_BGA1356 11 OF 20 ALL_SYS_PWRGD 2
A

1
4 H_VCCST_PWRGD
3 Y
+3VS GND
74AUP1G07GW_TSSOP5

2
RC388
Iris2 use 1D35V_VTT_PWRGD 1K_0402_5%
POK
RSMRST circuit +3VALW
@ CZ34
Need to confirm sequence

1
1 2 1 @ 2 ALL_SYS_PWRGD
<46> 1VS_VCCIO_PWRGD ALL_SYS_PWRGD <29>
1

RC389 0_0402_5%
1U_0402_6.3V6K

1M_0402_5%
1

0.1U_0402_10V7K 1 @ 2 1 @ 2
A <44> 1.35V_VTT_PWRGD IMVP_VR_ON <48,49> A
RC392 0_0402_5% RC345 0_0402_5%
CC266

RC220

Short Pad @ Jason 6/24 Short PadJason 6/24

2

<29> PCH_RSMRST# 1
P

IN1
2

4 PCH_RSMRST#_Q SIO_SLP_S3# 1 2
POK 2 O
IN2 DELL CONFIDENTIAL/PROPRIETARY
G

DZ5 RB751S40T1G_SOD523-2
UZ6
3

SN74AHC1G08DCKR_SC70-5
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (6/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 11 of 64
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST

1 @ 2 H_CATERR#
RC79 49.9_0402_1%
1 2 H_THERMTRIP#
RC80 1K_0402_5%
+1.0V_VCCSTG

1 2 H_PROCHOT#
RC83 1K_0402_5% UC1D SKL-U

H_CATERR# D63
+3VS <29,41,42,48> H_PROCHOT# <29> PECI_EC A54 CATERR#
8/19 DG0.9
D H_PROCHOT# 1 2 H_PROCHOT#_R C65 PECI D
PROCHOT# JTAG
1 2 TOUCHPAD_INTR#_D RC84 T4946@
499_0402_1% H_THERMTRIP# C63
PAD~D A65 THERMTRIP# B61
RC272 10K_0402_5% CPU_XDP_TCK0
1 2 TOUCH_SCREEN_PD# SKTOCC# PROC_TCK D60 CPU_XDP_TCK0 <14>
@ SOC_XDP_TDI
C55
CPU MISC PROC_TDI A61 SOC_XDP_TDI <14>
RC277 10K_0402_5% T4942@ XDP_OBS0_R SOC_XDP_TDO
PAD~D BPM#[0] PROC_TDO SOC_XDP_TDO <14>
1 2 DGPU_PWROK T4941@ XDP_OBS1_R D55 C60 SOC_XDP_TMS
PAD~D BPM#[1] PROC_TMS SOC_XDP_TMS <14>
RC360 10K_0402_5% T10 @ XDP_OBS2_R B54 B59 SOC_XDP_TRST#
PAD~D BPM#[2] PROC_TRST# SOC_XDP_TRST# <14>
T11 @ XDP_OBS3_R C56
PAD~D BPM#[3] B56
A6 PCH_JTAG_TCK D59 PCH_JTAG_TCK1 <14>
SOC_XDP_TDI
TOUCH_SCREEN_PD# 1 @ 2 TOUCH_SCREEN_PD#_R A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO
<32> TOUCH_SCREEN_PD# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59
RC394 0_0402_5% TOUCHPAD_INTR#_D SOC_XDP_TMS
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST#
GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
CPU_POPIRCOMP AT16 JTAGX
PCH_POPIRCOMP AU16 PROC_POPIRCOMP
EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP

1
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
SKL-U_BGA1356 4 OF 20

RC88

RC89

RC90

RC91
2

2
DZ3
C RB751S40T1G_SOD523-2 C
1 2 TOUCHPAD_INTR#_D
<29,38> TOUCHPAD_INTR#

UC1G SKL-U

AUDIO

RC92 1 2 33_0402_5% HDA_SYNC BA22

<23> HDA_CODEC_SYNC 1 2 AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93 33_0402_5% HDA_BIT_CLK
<23> HDA_CODEC_BITCLK 1 2 BB22 HDA_BLK/I2S0_SCLK
ME_FWP_EC RC94 33_0402_5% HDA_SDOUT SDIO/SDXC
<23> HDA_CODEC_SDOUT 1 2 BA21 HDA_SDO/I2S0_TXD
<29> ME_FWP_EC RC223 1K_0402_5%
<23> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
‧LOW = ENABLE -->ME lock, can't update ME RC95 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
‧HIGH = DISABLE -->ME un-lock, can update ME <23> HDA_CODEC_RST# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
HDA_CODEC_BITCLK I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 KB_LED_BL_DET <38>
1 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
CC27 AK10 GPP_F2/I2S2_TXD BA9
B GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 B
22P_0402_50V8J GPP_A16/SD_1P8_SEL
2
H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
Close to RC93 GPP_D20/DMIC_DATA0
D8 AF13
DGPU_PWROK C8 GPP_D17/DMIC_CLK1 GPP_F23
<29,40,52> DGPU_PWROK GPP_D18/DMIC_DATA1
AW5
<23> SPKR GPP_B14/SPKR

SKL-U_BGA1356 7 OF 20

+3VALW_PCH +3VALW_PCH

1 2 SPKR 1 2 HDA_SDOUT
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5%

A
TOP SWAP STRAP Flash Descriptor Security override A

HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (7/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 12 of 64
5 4 3 2 1
 5 4 3 2 1

D D

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S SKL-U
UC1T SKL-U
RESERVED SIGNALS-1
1 2 CFG0 SPARE
@ RC113 10K_0402_1% <14> CFG0 CFG0 E68 BB68
B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 AW69 F6
<14> CFG1 CFG1
D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6 E3
<14> CFG2 CFG[2] RSVD_AW68 RSVD_E3
CFG3 D67 AK13 +1.8V_PGPPF AU56 C11
<14> CFG3 CFG[3] RSVD_TP_AK13 PAD~D @ T14 RSVD_AU56 RSVD_C11
<14> CFG4 CFG4 E70 AK12 AW48 B11
CFG[4] RSVD_TP_AK12 PAD~D @ T15 RSVD_AW48 RSVD_B11
<14> CFG5 C68 C7 A11
D68 CFG[5] BB2 RC361 1 @ 2 0_0402_5% U12 RSVD_C7 RSVD_A11 D12
Stall reset sequence <14> CFG6 CFG[6] RSVD_BB2 RSVD_U12 RSVD_D12
<14> CFG7 C67 BA3 U11 C12
F71 CFG[7] RSVD_BA3 H11 RSVD_U11 RSVD_C12 F52
HIGH(DEFAULT) No stall(Normal Operation) <14> CFG8 CFG[8] RSVD_H11 RSVD_F52
<14> CFG9 G69
LOW stall <14> CFG10 F70 CFG[9] AU5
G68 CFG[10] TP5 AT5 PAD~D @ T128
<14> CFG11 CFG[11] TP6 PAD~D @ T129
<14> CFG12 H70 SKL-U_BGA1356 20 OF 20
G71 CFG[12]
<14> CFG13 CFG[13]
1 2 CFG1 <14> CFG14 H69 D5
@ RC112 10K_0402_1% G70 CFG[14] RSVD_D5 D4
<14> CFG15 CFG[15] RSVD_D4
1 2 CFG3 B2
@ RC110 10K_0402_1% E63 RSVD_B2 C2
<14> CFG16 CFG[16] RSVD_C2
<14> CFG17 F63
CFG[17] B3
E66 RSVD_B3 A3
<14> CFG18 CFG[18] RSVD_A3
<14> CFG19 F66
C 1 2 CFG4 CFG[19] AW1 C
RC109 10K_0402_1% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 CMC@ 1 E8 RSVD_E1 E2
+1.0V_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> XDP_ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
T16 @ PAD~D BA70 AY4
RSVD_TP_BA70 TP1 PAD~D @ T126
T17 @ PAD~D BA68 BB3
RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM# PM_ZVM# <46,51>
F65 AW71
ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
B VSS_G65 RSVD_TP_AW70 PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1
MSM_N <51>
2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
RC120 100K_0402_5%

SKL-U_BGA1356 19 OF 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (8/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 13 of 64
5 4 3 2 1
 5 4 3 2 1

D D

PRIMARY CMC CONN

+1.0V_PRIM +1.0V_XDP
+3.3V_SPI CMC@
RPC2 CMC@
SOC_XDP_TDO 1 8 XDP_TDO RC352 1 2 0_0603_5%
1 <12> SOC_XDP_TDO
RC9 CMC@2 1K_0402_5% XDP_SPI_SI CPU_XDP_TCK0 2 7 XDP_TCK0
<12> CPU_XDP_TCK0
PCH_JTAG_TCK1 3 6 XDP_TCK1
<12> PCH_JTAG_TCK1
SOC_XDP_TMS 4 5 XDP_TMS
<12> SOC_XDP_TMS
+1.0V_VCCSTG 0_0804_8P4R_5% JPCMC1 CMC_DEBUG_36P
+1.0V_XDP
CMC@ OBS DATA JTAG/RC/HOOKS
RC350 2 CMC@ 1 51_0402_5% SOC_XDP_TMS RPC4
C SOC_XDP_TDI 1 8 XDP_TDI 1 22 C
<12> SOC_XDP_TDI <13> CFG0 DATA_0 VCCOBS_AB
RC351 2 CMC@ 1 51_0402_5% SOC_XDP_TDI SOC_XDP_TRST# 2 7 XDP_TRST# 3
<12> SOC_XDP_TRST# 3 6 <13> CFG1 5 DATA_1
Place to CPU side XDP_ITP_PMODE XDP_HOOK6
<13> XDP_ITP_PMODE <13> CFG2 DATA_2
RC349 2 CMC@ 1 51_0402_5% SOC_XDP_TDO 4 5 7
<13> CFG3 DATA_3
9 28 XDP_TRST#
<13> CFG4 DATA_4 XDP_TRST*
0_0804_8P4R_5% 11 29 XDP_TDI
<13> CFG5 DATA_5 XDP_TDI
13 30 XDP_TMS
<13> CFG6 15 DATA_6 XDP_TMS 32 XDP_TCK0
<13> CFG7 DATA_7 XDP_TCK0 31
CMC@ XDP_TCK1
RPC15 17 XDP_TCK1 35 XDP_TDO
+1.0V_XDP 1 8 <13> CFG17 21 DATA_CLK_1P XDP_TDO
XDP_SPI_SI XDP_HOOK3
<8> XDP_SPI_SI 2 7 <13> CFG16 DATA_CLK_1N 33
XDP_SPI_IO2 XDP_PRSENT_PCH
<8> XDP_SPI_IO2 3 6 2 XDP_PREQ* 34 XDP_PREQ# <10>
<13> CFG8 DATA_8 XDP_PRDY* XDP_PRDY# <10>
RC353 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE CFG3 4 5 XDP_PRSENT_CPU 4
<13> CFG9 DATA_9
6 27 XDP_HOOK0
<13> CFG10 DATA_10 HOOK_0
0_0804_8P4R_5% 8 25 XDP_HOOK3
<13> CFG11 DATA_11 HOOK_3
10 26 XDP_HOOK6
2 1 0_0402_5% <13> CFG12 12 DATA_12 HOOK_6
RC43 @ XDP_PRSENT_CPU
<13> CFG13 DATA_13
PCH_RSMRST#_Q RC158 1 CMC@ 2 1K_0402_5% XDP_HOOK0 14 24 XDP_PRSENT_PCH
<11> PCH_RSMRST#_Q <13> CFG14 DATA_14 XDP_PRSNT_PCH*
RC347 2 @ 1 0_0402_5% XDP_PRSENT_PCH 16 23 XDP_PRSENT_CPU
<13> CFG15 DATA_15 XDP_PRSNT_CPU*
CMC@ 18 19
<13> CFG19 DATA_CLK_2P GND
RC35 2 1 51_0402_1% CPU_XDP_TCK0 20 36
<13> CFG18 DATA_CLK_2N <MT> GND
Place to CPU side
RC348 2 @ 1 51_0402_5% PCH_JTAG_TCK1

INTEL_CMC_PRIMARY
CONN@

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (9/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 14 of 64
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L SKL-U BSC(Backside cap) : Place on secondary side, underneath the package
CPU POWER 1 OF 4

A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37 ESD Request
VCC_AM33 VCC_K37

1
AM35 K38

100_0402_1%
AM37 VCC_AM35 VCC_K38 K40
AM38 VCC_AM37 VCC_K40 K42

RC140
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43

2
+VCC_CORE_G0 K32 E32 VCCSENSE
T122 @ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <48>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <48>
T123 @ PAD~D RSVD_AK32

1
B63 H_CPU_SVIDALRT#

100_0402_1%
AB62 VIDALERT# A63 VIDSCLK
+VCC_EDRAM VCCOPC_AB62 VIDSCK VIDSCLK <48> +1.0V_PRIM +VCC_CORE
P62 D64 VIDSOUT

RC141
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20 1 2
VCCSTG_G20

2
Jason 6/25 H63 @ESD@ CC283 22U_0603_6.3V6M
+1.8V_PRIM VCC_OPC_1P8_H63
ShortPad
1 @ 2 G61 1 2
RC232 0_0603_5% VCC_OPC_1P8_G61 Jason 6/25 @ESD@ CC284 22U_0603_6.3V6M
AC63 RC143
<51> VCC_EDRAM_SENSE AE63 VCCOPC_SENSE 0_0603_5%
<51> VSS_EDRAM_SENSE VSSOPC_SENSE +1.0V_PRIM +3VS
+1.0V_VCCSTG_R 1 @ 2 +1.0V_VCCSTG
+VCC_EOPIO AE62
AG62 VCCEOPIO 1 2
VCCEOPIO ShortPad @ESD@ CC285 22U_0603_6.3V6M
AL63
<51> VCCEOPIO_SENSE AJ62 VCCEOPIO_SENSE
<51> VSSEOPIO_SENSE VSSEOPIO_SENSE +1.0V_PRIM +1.35V_MEM
C C
SKL-U_BGA1356 12 OF 20 1 2
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e @ESD@ CC286 22U_0603_6.3V6M
(w/ on package cache)

+VCC_EDRAM +VCC_EOPIO
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1
CC180

CC184

CC187
CC183

CC288

CC289

CC290

CC291

CC292

2 2 2 2 2 2 2 2 2

B B

+1.0V_VCCST
SVID ALERT
1
56_0402_1%
RC152

CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
2

2 1 H_CPU_SVIDALRT#
<48> VIDALERT_N
220_0402_5% RC153

+1.0V_VCCST
SVID DATA
100_0402_1%
1

CAD Note: Place the PU resistors close to CPU

RC157

RC208close to CPU 300 - 1500mils

A A
2

VIDSOUT
<48> VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (10/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 15 of 64
5 4 3 2 1
 5 4 3 2 1

+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V

+VCC_GT +VCC_GT

UC1M SKL-U

D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69
AA67 VCCGT VCCGT R70
AA69 VCCGT VCCGT R71
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
AC67 VCCGT VCCGT W64
AC68 VCCGT VCCGT W65
AC69 VCCGT VCCGT W66
AC70 VCCGT VCCGT W67
AC71 VCCGT VCCGT W68
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GT
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
J56 VCCGT VCCGTX_AK43 AK45
J58 VCCGT VCCGTX_AK45 AK46
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
K50 VCCGT VCCGTX_AK50 AK52
K52 VCCGT VCCGTX_AK52 AK53
K53 VCCGT VCCGTX_AK53 AK55
K55 VCCGT VCCGTX_AK55 AK56
K56 VCCGT VCCGTX_AK56 AK58
K58 VCCGT VCCGTX_AK58 AK60
K60 VCCGT VCCGTX_AK60 AK70
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
L64 VCCGT VCCGTX_AL46 AL50
L65 VCCGT VCCGTX_AL50 AL53
VCCGTX for SKYLAKE-U 2+3e only
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50 +VCC_GT
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
VCCGT VCCGTX_AM56
1

1
N63 AM58
100_0402_1%

100_0402_1%
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
RC161

@ RC340
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
2

VCC_GT_SENSE J70 AK62 VCCSENSE_VCCGTUS

<48> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61 VSSSENSE_VCCGTUS
<48> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1

SKL-U_BGA1356 13 OF 20
100_0402_1%

100_0402_1%

B B
RC163

@ RC341
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (11/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 16 of 64
5 4 3 2 1
 5 4 3 2 1

Jason 6/25
+1.35V_MEM_CPUCLK ShortPad +1.35V_MEM
RC231
0_0603_5% +1.0VS_VCCIO
1 @ 2 VDDQ: 8.45A
+1.35V_MEM 1.35V in DDR3L,
1.2V in LPDDR3 and DDR4 BSC BSC
D
BSC PSC D

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CC248

CC249
1 1 1 1 1 1
@ CC174

@ CC175

CC176

CC177

CC178

CC179

CC181

CC182

CC185

CC186
2 2 2 2 2 2
2 2 2 2 2 2 +1.0VS_VCCIO
UC1N SKL-U
CPU POWER 3 OF 4

AU23 AK28
BSC PSC AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
PSC
AU42 VDDQ_AU35 VCCIO AL42
22U_0603_6.3V6M

BB23 VDDQ_AU42 VCCIO AM28

1 1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

BB32 VDDQ_BB23 VCCIO AM30

BB41 VDDQ_BB32 VCCIO AM42 +VCC_SA
@ CC256

@ CC257

@ CC255

CC293

CC294

CC295

1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.35V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
2 2 2 2 2 2 BB51 VDDQ_BB47 AK23

CC252

CC253

CC250

CC251
VDDQ_BB51 VCCSA AK25
VCCSA G23 2 2 2 2
PSC BSC AM40 VCCSA G25
VDDQC VCCSA G27
A18 VCCSA G28 +1.0VS_VCCIO
10U_0402_6.3V6M

1U_0402_6.3V6K
VCCST VCCSA J22
1 1 VCCSA
A22 J23
CC296

CC194

VCCSTG_A22 VCCSA J27

VCCSA

1
AL23 K23

100_0402_1%
2 2 VCCPLL_OC VCCSA K25

RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28
C VCCPLL_K21 VCCSA K30 C
PSC VCCSA

2
AM23 VCCIO_SENSE
VCCIO_SENSE VCCIO_SENSE <46>
AM22 VSSIO_SENSE
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <46>
1
1U_0402_6.3V6K

H21
VSSSA_SENSE H20
CC195

BSC VCCSA_SENSE

1
100_0402_1%

100_0402_1%
2
SKL-U_BGA1356 14 OF 20

RC166

RC167
+1.35V_MEM 1 2
1
1U_0402_6.3V6K

+VCC_SA
RC168 100_0402_1%
CC199

2
+1.0V_VCCST

2 PSC PJP15
Always Short
0.1U_0402_10V7K

1
1U_0402_6.3V6K
CC297

1 VSA_SEN- <48> +1.0V_VCCSTG_C Imax : 3 A +1.0VS_VCCIO

VSA_SEN+ <48>
PJP15 PJP@
CC202

2 1 2
2 1 2
JUMP_43X79 1
CZ1701
0.1U_0402_25V6
@
2
POP option with Volume

B B

+1.0V_VCCST source +1.0V_VCCSTG source +1.0V_VCCSTG

PJP32
PJP27 Always Short

1
+1.0V_PRIM
Always Short PJP32 PJP@
UZ19 PAD-OPEN1x3m
RZ1701 UZ21 PJP27 PJP@ 1
22.1K_0402_1% 2 1 2 VIN1
+1.0V_VCCST VIN2
1 2 EN_1.0V_VCCST_ON 3
<11,29,44> SIO_SLP_S4# ON

2
+5VALW 7 6 +1.0V_VCCSTG_C 1 2
1 7 +1.0V_VCCST_C PAD-OPEN1x1m VIN thermal VOUT
1 VIN VOUT 3 CZ82 @
CZ1703 2 8 1 2 VBIAS 0.1U_0402_10V7K
+1.0V_PRIM VIN VOUT 1
0.1U_0402_10V7K @ CZ78 0.1U_0402_10V7K 4 5

1U_0402_6.3V6K

0.1U_0402_10V7K
2 1 ON GND
RZ75

CZ87

CZ86
0_0402_5%

@
4 1 @ 2 2 TPS22961DNYR_WSON8
+5VALW VBIAS 2
5
6 GND 9 +3VALW 4.4mohm/6A
CT GND TR=12.5us@Vin=1.05V
1

5
TPS22967DSGR_SON8_2X2
CZ70 1 +1.0V_VCCSTG +1.0V_VCCST
<11,29,40,41,46,51> SIO_SLP_S3#

P
IN1 4 VCCSTG_EN 1 2 VCCSTG_EN_R
470P_0402_50V7K O
2

2 RZ1702 49.9K_0402_1% 1 1 @ 2
<11> SIO_SLP_S0# IN2
G
RC238 0_0603_5%
UC15 1 2 CZ1702
3

SN74AHC1G08DCKR_SC70-5 0.1U_0402_10V7K
DZ1701 2 pop option with UZ21
A RB751S40T1G_SOD523-2 A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (12/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 17 of 64
5 4 3 2 1
 5 4 3 2 1

close UC1.AL1 and <120mil +1.0V_MPHYGT

+1.0V_PRIM
Imax : 2.57A +1.0V_MPHYAON +1.0V_PRIM
+1.0V_PRIM_CORE
ShortPad +1.0V_PRIM_CORE close UC1.K17 and <120mil close UC1.AB19 and <400mil Jason 6/25
Jason 6/25 PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM
1 @ 2 RC309 0_0603_5%
RC194 0_0805_5% +3.3V_PGPPB 1 @ 2
1 1 1 1 close UC1.AG15 and <120mil

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
RC194 POP option for Volume +3.3V_PGPPC +3.3V_PGPPE
ShortPad

@ CC205

@ CC206
+1.0V_APLLEBB

CC203

CC204
1

1U_0402_6.3V6K
+1.0V_MPHYAON UC1O SKL-U RC310 0_0603_5%

@ CC265
2 2 2 2
close UC1.T16 and <400mil
RC299 0_0603_5% 1 1 1 @ 2

1U_0402_6.3V6K

1U_0402_6.3V6K
CPU POWER 4 OF 4
1 @ 2

@ CC207

@ CC208
D AB19 2 D
8/28 schematic review AB20 VCCPRIM_1P0 AK15
ShortPad
ShortPad +1.0V_CLK6 P18 VCCPRIM_1P0 VCCPGPPA AG15
+3.3V_1.8V_PGPPA 2 2
RC300 0_0603_5% VCCPRIM_1P0 VCCPGPPB Y16
close UC1.AF18 and <400mil VCCPGPPC
1 @ 2 AF18 Y15
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
AF19 T16
V20 VCCPRIM_CORE VCCPGPPE AF16
ShortPad +1.0V_DTS V21 VCCPRIM_CORE VCCPGPPF AD15
+1.8V_PGPPF +3VALW_PCH
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
RC301 0_0603_5%
1 @ 2 AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
close UC1.V19 and <120mil
K17 T1 +1.8V_PRIM
ShortPad 1

1U_0402_6.3V6K
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
+1.0V_CLK1 L1

@ CC209
RC302 0_0603_5% VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
1 @ 2 +1.0V_MPHYGT N15
N16 VCCMPHYGT_1P0_N15 AK17 +RTC_CELL 2
1

1U_0402_6.3V6K
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3VALW_PCH
N17
ShortPad +1.0V_CLK3
close UC1.N15 and CC210 <400mil, CC211 <120mil
P15 VCCMPHYGT_1P0_N17 AK19

CC212
RC303 0_0603_5% P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
1 @ 2 1 1 1 1

47U_0805_6.3V6M

1U_0402_6.3V6K

0.1U_0402_10V7K

1U_0402_6.3V6K
K15 BB10

@ CC210
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
L15
ShortPad

CC211

CC270

CC213
VCCAMPHYPLL_1P0 close UC1.BB10 and <120mil
A14 1

0.1U_0402_10V7K
2 2 VCCCLK1 +1.0V_CLK1 2 2
Jason 6/25 V15
+1.0V_APLL VCCAPLL_1P0 K19

CC214
+1.8V_PRIM +3VALW_PCH VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF +1.0V_PRIM AB17
RC304 0_0603_5% Y18 VCCPRIM_1P0_AB17 L21 2
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
1 @ 2
+3.3V_ALW_DSW AD17 N20 +1.0V_CLK4
AD18 VCCDSW_3P3_AD17 VCCCLK4

8.2P_0402_50V8D
ShortPad +3.3V_1.8V_PGPPG
close UC1.AJ19 and <400mil 1
AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6

CC215
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
Change CC215 to 8.2p for RF team. RF@
C 1 @ 2 Jason 6/1 AJ19 A10 C
RC234 0_0603_5% 2 VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM AJ16 AN11 CORE_VID0 <46> 1

1U_0402_6.3V6K
+3VALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0 AN13

@ CC216
GPP_B1/CORE_VID1 CORE_VID1 <46>
RC235 0_0603_5% close UC1.AF20 and <400mil AF20
1 @ 2 AF21 VCCSRAM_1P0
+3VALW_PCH T19 VCCSRAM_1P0 2
1
Take care!!! Note1 on Page 19
1U_0402_6.3V6K

T20 VCCSRAM_1P0
ShortPad
@ CC217

+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0

RC211 0_0603_5% AJ21
1 @ 2 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
+1.8V_PRIM ShortPad Jason 6/25 N18
VCCAPLLEBB
1 @ 2 1 close UC1.N18 and <120mil
1U_0402_6.3V6K

RC212 0_0603_5% SKL-U_BGA1356 15 OF 20

CC218

+3VALW_PCH +3.3V_PGPPB
RC305 0_0603_5% 2
1 @ 2

ShortPad +3.3V_PGPPC
RC306 0_0603_5% Jason 6/25 Jason 6/25
1 @ 2
+1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM ShortPad +1.0V_CLK2 +1.0V_PRIM ShortPad +1.0V_CLK5 +3VALW_PCH
ShortPad close UC1.K15, UC1.L15 and <100mil RC170 RC171 close UC1.AK17 and <120mil
+3.3V_PGPPD 0_0603_5% 0_0603_5%
RC307 0_0603_5% 1 @ 2 1 @ 2 1 @ 2
1 @ 2 close UC1.K15 and <120mil
1 RC169 1 1 1 close UC1.L19 and <100mil 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K
47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K
B 0_0603_5% B
ShortPad
@ CC219

@ CC220

@ CC221

CC223
+3.3V_PGPPE
ShortPad
@ CC281

@ CC264

CC224
RC308 0_0603_5% close UC1.K19 and <100mil
1 @ 2 2 Jason 6/25 2 2 2 2 2 2

ShortPad
Jason 6/25

ShortPad Jason 6/25

RC213
0_0603_5%
+3.3V_SPI +1.0V_PRIM ShortPad
RC172
+1.0V_APLL
+1.0V_PRIM
Jason 6/25
ShortPad +1.0V_CLK4
+1.0V_MPHYGT source +1.0V_PRIM
Jason 6/25
RC368
0_0603_5%
+1.0V_MPHYGT

1 @ 2 0_0603_5% RC173 +1.0V_PRIM 1 @ 2

1 @ 2 0_0603_5%
Jason 6/25 1 @ 2
UZ20 @
ShortPad
8.2P_0402_50V8D

0.1U_0603_25V7K

close UC1.V15 and <100mil 1 1

1
CC1801

CC225

close UC1.N20 and <100mil 1

47U_0805_6.3V6M

+3VALW RC214 +3.3V_ALW_DSW RF@ @ 2 VIN1 +1.0V_MPHYGT

@ CC226

0_0603_5% VIN2
1 @ 2 Change CC1801 to 8.2p for RF team. 2 2 +5VALW 7 6
Jason 6/1 2 VIN thermal VOUT
1

0.1U_0402_10V7K
3
ShortPad VBIAS
22U_0603_6.3V6M
@ CC279

22U_0603_6.3V6M
@ CC280

CZ85
1 1 1 1

1U_0402_6.3V6K

0.1U_0402_10V7K
Jason 6/25 4 5

CZ84
ON GND 2

CZ88
@
2 2 2 2 TPS22961DNYR_WSON8
+3VALW +1.8V_PRIM +1.0V_PRIM +1.0V_PRIM_CORE @ 4.4mohm/6A
TR=12.5us@Vin=1.05V
1 1 1 1
47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M

A <11> MPHYP_PWR_EN A
CC271

CC272

CC273

CC274

2 2 2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (13/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 18 of 64
5 4 3 2 1
 5 4 3 2 1

Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation

UC1P SKL-U UC1Q SKL-U R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
AJ20 VSS VSS AR28 B22 VSS VSS E46
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS

SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (14/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 19 of 64
5 4 3 2 1
 5 4 3 2 1

<7> DDR_A_DQS#[0..7]

<7> DDR_A_D[0..63] +DDR_VREF_A_DQ0 +1.35V_MEM

Reverse Type +1.35V_MEM
JDIMM1
<7> DDR_A_DQS[0..7]
1 2
3 VREF_DQ VSS 4

2.2U_0402_6.3V6M
DDR_A_D1
<7> DDR_A_MA[0..15] VSS DQ4
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D5 7 DQ0 DQ5 8
DQ1 VSS

1
9 10

@ CD5
DDR_A_DQS#0
D 11 VSS DQS0# 12 DDR_A_DQS0 D
13 DM0 DQS0 14
Note: VSS VSS

2
Check voltage tolerance of DDR_A_D3 15 16 DDR_A_D6
DDR_A_D7 17 DQ2 DQ6 18 DDR_A_D2 +1.35V_MEM
VREF_DQ at the DIMM socket 19 DQ3 DQ7 20
DDR_A_D9 21 VSS VSS 22 DDR_A_D13
DDR_A_D8 23 DQ8 DQ12 24 DDR_A_D12
Layout Note: DQ9 DQ13

1
25 26

470_0402_1%
27 VSS VSS 28
Place near JDIMM1 DDR_A_DQS#1
29 DQS1# DM1 30

RD2
DDR_A_DQS1 DDR_DRAMRST#_R
31 DQS1 RESET# 32
DDR_A_D10 33 VSS VSS 34 DDR_A_D15
DQ10 DQ14

2
35 36

0.1U_0402_25V6
DDR_A_D11 DDR_A_D14 RD29
37 DQ11 DQ15 38 0_0402_5%
39 VSS VSS 40 1 2

ESD@
DDR_A_D35 DDR_A_D32 @ DDR_DRAMRST#
DQ16 DQ20 <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>

1
+1.35V_MEM 41 42

CD6
DDR_A_D37 DDR_A_D36
43 DQ17 DQ21 44
45 VSS VSS 46
Short Pad
DDR_A_DQS#4
DQS2# DM2

2
DDR_A_DQS4 47 48 Jason 6/24
49 DQS2 VSS 50
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_A_D39
DDR_A_D38 51 VSS DQ22 52 DDR_A_D33
DQ18 DQ23
1

1
DDR_A_D34 53 54
55 DQ19 VSS 56
CD7

CD2

CD3

CD8

CD9

CD4

CD10

CD11
DDR_A_D40 CAD NOTE
DDR_A_D44 57 VSS DQ28 58 DDR_A_D41
DQ24 DQ29 PLACE THE CAP NEAR TO DIMM RESET PIN
2

2
DDR_A_D45 59 60
61 DQ25 VSS 62 DDR_A_DQS#5
63 VSS DQS3# 64 DDR_A_DQS5
65 DM3 DQS3 66
DDR_A_D42 67 VSS VSS 68 DDR_A_D47 +1.35V_MEM
DDR_A_D46 69 DQ26 DQ30 70 DDR_A_D43
71 DQ27 DQ31 72
VSS VSS

1
1.8K_0402_1%
RD4
+1.35V_MEM DDR_A_CKE0 73 74 DDR_A_CKE1
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7>
75 76
C
77 VDD VDD 78 DDR_A_MA15 +DDR_VREF_A_DQ0 +DDR_VREF_A_DQ C
NC A15

2
DDR_A_BS2 79 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 1 2

DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 RD5 2_0402_1%
A9 A7
1

87 88
@ CD13

@ CD16

@ CD17

@ CD19

@ CD20

0.022U_0402_16V7K
VDD VDD
1

+ 89 90
CD12

CD14

CD15

CD18

1.8K_0402_1%
DDR_A_MA8 DDR_A_MA6
A8 A6

1
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4

1
93 94

RD6

CD21
VDD VDD
2

DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
A1 A0

2
99 100
VDD VDD

2
DDR_A_CLK0 101 102 DDR_A_CLK1
<7> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <7>

1
103 104

24.9_0402_1%
DDR_A_CLK#0 DDR_A_CLK#1
<7> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <7>
105 106

RD7
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112
VDD VDD

2
DDR_A_WE# 113 114 DDR_A_CS#0
<7> DDR_A_WE# WE# S0# DDR_A_CS#0 <7>
DDR_A_CAS# 115 116
<7> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <7>
117 118
DDR_A_MA13 119 VDD VDD 120
Layout Note: <7> DDR_A_CS#1 DDR_A_CS#1 121 A13 ODT1 122
DDR_A_ODT1 <7>
123 S1# NC 124 +DDR_VREF_A_CA
Place near 125 VDD VDD 126
JDIMM1.203,204 127 TEST
VSS
VREF_CA
VSS
128
129 130

2.2U_0402_6.3V6M
DDR_A_D30 DDR_A_D31
131 DQ32 DQ36 132

@ CD23
DDR_A_D26 DDR_A_D25
DQ33 DQ37

1
133 134
DDR_A_DQS#3 135 VSS VSS 136
DDR_A_DQS3 137 DQS4# DM4 138
DQS4 VSS

2
139 140 DDR_A_D28
DDR_A_D27 141 VSS DQ38 142 DDR_A_D24
DDR_A_D29 143 DQ34 DQ39 144
B +0.675V_DDR_VTT 145
147
DQ35
VSS
VSS
DQ44
146
148
DDR_A_D20 DDR3L SODIMM ODT GENERATION B
DDR_A_D21 DDR_A_D16
DDR_A_D17 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#2 9/17 delete ODT Genertation, connect directly to CPU
153 VSS DQS5# 154 refer 546765_2014WW37_SkylakeU_Y_MOW_Rev_1_0
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_DQS2
155 DM5 DQS5 156
1 1 1 1 VSS VSS
1

157 158
CD24

CD25

CD26

CD27

@ CD28

DDR_A_D19 DDR_A_D18
159 DQ42 DQ46 160
CD29

DDR_A_D22 DDR_A_D23
161 DQ43 DQ47 162
VSS VSS
2

2 2 2 2 DDR_A_D48 163 164 DDR_A_D53

DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D52
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS VSS 170
DDR_A_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D61
DDR_A_D56 181 VSS DQ60 182 DDR_A_D60
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D63 191 VSS VSS 192 DDR_A_D58
193 DQ58 DQ62 194
Short Pad DDR_A_D62
195 DQ59 DQ63 196
DDR_A_D59

1 @ 2 197 VSS VSS 198

RD15 0_0402_5% 199 SA0 EVENT# 200
+3VS VDDSPD SDA PCH_SMBDAT <8,21,34>
1 @ 2 201 202
SA1 SCL PCH_SMBCLK <8,21,34>
RD16 0_0402_5% +0.675V_DDR_VTT
203 204 +0.675V_DDR_VTT
VTT VTT
Short Pad 205 206
2.2U_0402_6.3V6M

0.1U_0402_10V7K

207 GND1 GND2 208

1 BOSS1 BOSS2
1

@ CD31

CD32

A A
FOX AS0A621-J4RB-7H
2

2
CONN@

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DDR3L
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 20 of 64
5 4 3 2 1
 5 4 3 2 1

+DDR_VREF_B_DQ0
Standard Type
<7> DDR_B_DQS#[0..7] +1.35V_MEM +1.35V_MEM
JDIMM2
<7> DDR_B_D[0..63]
1 2
3 VREF_DQ VSS 4 DDR_B_D1
<7> DDR_B_DQS[0..7] VSS DQ4
5 6

2.2U_0402_6.3V6M
DDR_B_D5 DDR_B_D4
DDR_B_D0 7 DQ0 DQ5 8
<7> DDR_B_MA[0..15] DQ1 VSS
D Note: 9 10 DDR_B_DQS#0 D
VSS DQS0#

1
11 12

@ CD33
Check voltage tolerance of DDR_B_DQS0
13 DM0 DQS0 14
VREF_DQ at the DIMM socket 15 VSS VSS 16 +1.35V_MEM
DDR_B_D2 DDR_B_D7
DQ2 DQ6

2
DDR_B_D3 17 18 DDR_B_D6
19 DQ3 DQ7 20
VSS VSS

1.8K_0402_1%
1
DDR_B_D9 21 22 DDR_B_D13
DDR_B_D8 23 DQ8 DQ12 24 DDR_B_D12
25 DQ9 DQ13 26

RD18
DDR_B_DQS#1 27 VSS VSS 28
DDR_B_DQS1 29 DQS1# DM1 30 DDR_DRAMRST#_R +DDR_VREF_A_CA +DDR_VREF_CA
Layout Note: DQS1 RESET# DDR_DRAMRST#_R <20>

2
31 32
VSS VSS
Place near JDIMM2 33 34

0.1U_0402_25V6
DDR_B_D11 DDR_B_D14
DDR_B_D10 35 DQ10 DQ14 36 DDR_B_D15 1 2
DQ11 DQ15

1
37 38

ESD@
RD19 2_0402_1%
39 VSS VSS 40

CD35

0.022U_0402_16V7K
DDR_B_D33 DDR_B_D37
41 DQ16 DQ20 42

1.8K_0402_1%
DDR_B_D36 DDR_B_D32
DQ17 DQ21

1
43 44
VSS VSS

1
45 46

RD20

CD36
DDR_B_DQS#4
DDR_B_DQS4 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D34
VSS DQ22

2
+1.35V_MEM DDR_B_D39 51 52 DDR_B_D35
DQ18 DQ23

2
DDR_B_D38 53 54 CAD NOTE
DQ19 VSS

1
55 56

24.9_0402_1%
DDR_B_D40 PLACE THE CAP NEAR TO DIMM RESET PIN
57 VSS DQ28 58

RD21
DDR_B_D42 DDR_B_D41
59 DQ24 DQ29 60
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_B_D43
61 DQ25 VSS 62 DDR_B_DQS#5
VSS DQS3#
1

1
63 64 DDR_B_DQS5
DM3 DQS3

2
65 66
CD37

CD38

CD39

CD40

CD41

CD42

CD43

CD44 67 VSS VSS 68

DDR_B_D44 DDR_B_D46
DQ26 DQ30
2

DDR_B_D45 69 70 DDR_B_D47
71 DQ27 DQ31 72
VSS VSS

DDR_B_CKE0 73 74 DDR_B_CKE1
C <7> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <7> +1.35V_MEM C
75 76
77 VDD VDD 78 DDR_B_MA15
NC A15

1
79 80

1.8K_0402_1%
DDR_B_BS2 DDR_B_MA14
+1.35V_MEM <7> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11

RD22
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88 +DDR_VREF_B_DQ0 +DDR_VREF_B_DQ
VDD VDD

2
89 90
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

DDR_B_MA8 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 1 2
VDD VDD
1
@ CD46

@ CD47

95 96
@ CD49

@ CD52

@ CD53

DDR_B_MA3 DDR_B_MA2 RD23 2_0402_1%

A3 A2
1

+ 97 98
CD45

CD48

CD50

CD51

0.022U_0402_16V7K
DDR_B_MA1 DDR_B_MA0
99 A1 A0 100

1.8K_0402_1%
VDD VDD

1
DDR_B_CLK0 101 102 DDR_B_CLK1
<7> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <7>
2

1
103 104

RD24

CD54
DDR_B_CLK#0 DDR_B_CLK#1
<7> DDR_B_CLK#0 CK0# CK1# DDR_B_CLK#1 <7>
105 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>

2
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>

2
111 112
113 VDD VDD 114

24.9_0402_1%
DDR_B_WE# DDR_B_CS#0
<7> DDR_B_WE# WE# S0# DDR_B_CS#0 <7>

1
DDR_B_CAS# 115 116
<7> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <7>
117 118

RD25
DDR_B_MA13 119 VDD VDD 120
A13 ODT1 DDR_B_ODT1 <7> +DDR_VREF_A_CA
DDR_B_CS#1 121 122
<7> DDR_B_CS#1 S1# NC
123 124
VDD VDD

2
125 126
127 TEST VREF_CA 128
129 VSS VSS 130

2.2U_0402_6.3V6M
DDR_B_D21 DDR_B_D16
DDR_B_D20 131 DQ32 DQ36 132 DDR_B_D17
133 DQ33 DQ37 134

@ CD56
Layout Note: VSS VSS

1
DDR_B_DQS#2 135 136
DQS4# DM4
Place near DDR_B_DQS2 137
139 DQS4 VSS
138
140 DDR_B_D18
JDIMM2.203,204 VSS DQ38

2
DDR_B_D23 141 142 DDR_B_D19
B DDR_B_D22 143 DQ34 DQ39 144 B
145 DQ35 VSS 146 DDR_B_D28
DDR_B_D24 147 VSS DQ44 148 DDR_B_D29
DDR_B_D25 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#3
153 VSS DQS5# 154 DDR_B_DQS3
+0.675V_DDR_VTT 155 DM5 DQS5 156
DDR_B_D26 157 VSS VSS 158 DDR_B_D31
DDR_B_D27 159 DQ42 DQ46 160 DDR_B_D30
161 DQ43 DQ47 162
DDR_B_D52 163 VSS VSS 164 DDR_B_D53
165 DQ48 DQ52 166
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_D49 DDR_B_D48
167 DQ49 DQ53 168
@ CD61

1 1 1 1 VSS VSS
1

169 170
CD57

CD58

CD59

CD60

CD62

DDR_B_DQS#6
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_B_D50
VSS DQ54
2

2 2 2 2 DDR_B_D55 175 176 DDR_B_D51

DDR_B_D54 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_B_D61
DDR_B_D56 181 VSS DQ60 182 DDR_B_D60
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#7
187 VSS DQS7# 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS VSS 192 DDR_B_D62
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
+3VS Short Pad 197 VSS VSS 198
RD27 199 SA0 EVENT# 200
+3VS VDDSPD SDA PCH_SMBDAT <8,20,34>
2 @ 1 201 202
SA1 SCL PCH_SMBCLK <8,20,34>
0_0402_5% +0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT
VTT VTT
1

205 206
207 GND1 GND2 208
2.2U_0402_6.3V6M

0.1U_0402_10V7K

RD28
@

0_0402_5% BOSS1 BOSS2

A 1 A
1

@ CD63

CD64
2

FOX AS0A621-J4SB-7H
Short Pad CONN@
2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DDR3L
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 21 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = Other

Mind the voltage rating of the caps.
+19VB
+19VB

2
@
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

@
SCD1U25V2KX-GP

SC1KP50V2KX-1GP

@
SC1KP50V2KX-1GP

@
SCD1U25V2KX-GP
Screw hole/FD/EMI stop

1
@
SCD1U25V2KX-GP

SC1KP50V2KX-1GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

SC1KP50V2KX-1GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

1
EC9740

EC9741

EC9742

EC9747

EC9748

EC9749
2

2
EC9701

EC9702

EC9703

EC9704

EC9708

EC9705

EC9706

EC9707

EC9709

EC9710
H1 H2 H3 H4 H5 H6 H7
H_3P2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2 H_3P0

D D

@ @ @ @ @ @ @
1

1
+1.35V_MEM_GFX

1
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
HGPU3 HGPU2 HGPU1
HCPU1 HCPU2 HCPU3

1
H_3P3 H_3P3 H_3P3

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP
H_3P7 H_3P7 H_3P4

2
EC9717

EC9711

EC9712

EC9713

EC9716

EC9715

EC9714

2
EC9746

EC9750

EC9751

EC9752

EC9753

EC9754
@ @ @
@ @ @
1

1
+5VS
H8 H9 +1.35V_MEM_GFX
H_4P0N H_3P0X3P8N
@ @

1
@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP
1

1
@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP
2

2
EC9720

EC9719

EC9718

EC9723

EC9721

EC9722

EC9724
FD1 FD2 FD3 FD4 FD5 FD6

2
EC9727

EC9725

EC9726

EC9730

EC9728

EC9729

EC9731
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1

C C

SPR1 SPR2 SPR3 +17.4V_BATT+ +VGA_CORE AUD_AGND

SPRING-31-GP SPRING-24-GP-U SPRING-13-GP-U +3VS +5VALW
@ @ @
1

1
@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SC1U10V2KX-1GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SCD1U25V2KX-GP

@
SC1KP50V2KX-1GP
2

2
EC9758

EC9759

EC9760

EC9761

EC9755

EC9756

EC9757

EC9737

EC9735

EC9736

EC9738

EC9734

EC9732

EC9733

EC9739

EC9744

EC9743

EC9745
Main Func = RTC

+RTC_VCC +3VLP +RTC_CELL +3VALW +RTC_CELL

D2502 @
B 1 +RTC_VCC B
AFTP2502
@ 2 1
D2501
RTC1
2
RB551V-30_SOD323-2
R2502 1 2015/5/19 Modify
1KR2J-1-GP Jason
2 1 2 1 RTC_PWR 3
- +

1
@ C2503
BAS40C-2-GP SCD47U6D3V2KX-GP
2

LOTES_AAA-BAT-054-K01 2nd = 75.00040.C7D

CONN@
3rd = 75.00040.A7D
1

R2504
2

10MR2J-L-GP
G
2

3 1 RTC_DET# <9>
S

Q2505
2N7002K_SOT23-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC/Screw hole/EMI caps
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 22 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

D D

<24> LINE1_VREFO_R MIC2_VREFO <24>

<24> LINE1_VREFO_L AUD_AGND

moat

SC2D2U6D3V2MX-GP
Jason 6/24 Reserved for ALC3234
Short Pad <24> AUD_HP1_JACK_L

SC4D7U6D3V3KX-GP
+3VS +3V_DVDD 1 2
R2701
<24> AUD_HP1_JACK_R
EC2707 @ 0_0402_5% Short Pad

1
1 2
1
0_0402_5%
2
HDA27 3246@ EC2706
1
@
2
0_0402_5% Short Pad
@ R2711
moat EC2705 @ 0_0402_5% Short Pad

1 C2705
1 2
SC1U10V2KX-1GP 100KR2J-1-GP EC2704
1
@
2
0_0402_5% Short Pad
25mA Short Pad
C2701 C6214 C2704 EC2703 @ 0_0402_5%

C2702
1

1
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
1 2 Jason 6/25

2
+5V_AVDD
ShortPad +5VS ESD@ => @
Jason 6/25
ALC3246-CG-GP

2
Close pin9 R2703 AUD_AGND

LDO1_CAP 2
1.5A
SA00008GJ00 0_0603_5%

1
C2703 1 @ 2

AUD_VREF
+5V_AVDD

CPVEE
SC1U10V2KX-1GP
+5VS +5V_PVDD

CBN
AUD_AGND C2710

1
1 2 0_0805_5%
C2711 R2706 @ ShortPad

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1 @ 2
+3V_1.8V_CPVDD Layout Note:

2
R2702 0_0805_5% Place close to Pin 26 ESD@ => @

36

35

34

33

32

31

30

29

28

27

26

25
Jason 6/25
ShortPad C2706 C2707 C2708 C2709 HDA27
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

CPVEE

LDO1-CAP
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R

MIC2-VREFO

AVDD1

AVSS1
HPOUT-L/PORT-I-L

LINE1-VREFO-L

VREF
1 @ 2
R2704 0_0805_5%
2

2
ShortPad CBP 37 24 Layout Note:
AUD_AGND AUD_AGND
CBP LINE2_L/PORT-E-L
Jason 6/25 Tied at point only under
38 23
AUD_AGND AVSS2 LINE2_R/PORT-E-R Codec or near the Codec
1 2 SC10U6D3V3MX-GP 39 22
AUD_AGND C2712 LDO2_CAP
LDO2-CAP LINE1_L/PORT-C-L LINE1_L <24> moat +3VALW +RTC_CELL
40 21
Layout Note: Layout Note: +1.8V_AVDD AVDD2 LINE1_R/PORT-C-R LINE1_R <24> R2713 1 2 0_0402_5%
Close pin41 Close pin46 41 20 V3D3_STB R2712 1 @ 2 0_0402_5%
+5V_PVDD PVDD1 NC#20
C AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP C
<24> AUD_SPK_L+ SPK-OUT-L+ MIC-CAP AUD_AGND
Layout Note: AUD_SPK_L- 43 18
Speaker trace width >40mil @ 2W4ohm speaker power<24> AUD_SPK_L- SPK-OUT-L- MIC2_R/PORT-F-R/SLEEVE SLEEVE <24> Layout Note:
AUD_SPK_R- 44 17 Width>40mil, to improve Headpohone Crosstalk noise
<24> AUD_SPK_R- SPK-OUT-R- MIC2_L/PORT-F-L/RING RING2 <24>
+3V_DVDD +1.8V_PRIM +3V_1.8V_CPVDD 45 16 1 3246@ 2
Change it to sharp will be better.
AUD_SPK_R+ MONO_PC_BEEP_R AUD_PC_BEEP
<24> AUD_SPK_R+ SPK-OUT-R+ MONO-OUT R6516 0R2J-2-GP
Add 2 vias (>0.5A) when trace layer change.
R2705 1 3246@ 2
Short Pad +5V_PVDD
46 15 JDREF @ R2707 1 2 20KR2F-L-GP
AUD_AGND
0R2J-2-GP Jason 6/24 PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3

GPIO0/DMIC-DATA

GPIO1/DMIC-CLK
R2710 1 2 0R2J-2-GP C6213 C6215 R2708 1 @ 2 0_0402_5% PD# 47 14
<29> EC_MUTE# PDB MIC2/LINE2_JD/JD2
1

1
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

3234@ +3V_DVDD
COMBO-GPI 48 13 AUD_SENSE_A 1 2 AUD_SENSE

SDATA-OUT
SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE <24> R2722

LDO3-CAP
1 @ 2 R2709

SDATA-IN
+3V_DVDD

DVDD-IO
2

PCBEEP
RESET#
R6512 100KR2J-1-GP 49 200KR2F-L-GP AUD_SENSE_A 2 1
GND Layout Note:

DVDD

SYNC
DVSS

BCLK
Close pin36 Place close to Pin 13 100KR2J-1-GP

1
moat
@
ALC3234-CG-GP 3234@ C2901

10

11

12
SCD1U16V2KX-3GP

0_0402_5%

2
+3V_DVDD
1 2
AUD_PC_BEEP_R @ AUD_PC_BEEP
moat

LDO3_CAP
TP2702 1 AUD_AGND
+3V_DVDD R6514

2
DMIC_DATA_R C2717 0_0402_5%

C2718

C2719
1

1
moat
EC2701
SC10P50V2JN-4GP

C2716

SCD1U16V2KX-3GP

@
SC4D7U6D3V3KX-GP Short Pad

HDA_CODEC_RST#_R
1

1
@

2
3234@=>

1
+1.8V_PRIM +1.8V_AVDD Jason 6/24

R6513
Short Pad
2

2
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP
Q6205 Jason 6/24
LN2306LT1G_SOT23-3 R6511
0_0402_5%
1 3 1 @ 2
D

Short Pad Short Pad

Jason 6/24 3234@=>@
1

R2714 1 @ 2 0_0402_5% DMIC_DATA_R Jason 6/24

G

<32> DMIC_DATA
2

C2715 Jason 6/24

SC4D7U6D3V3KX-GP R2716 1 @ 2 0_0402_5% DMIC_CLK_R
+3VS <32> DMIC_CLK
2

Short Pad
Close pin40 Short Pad R2719 1 @ 2 CODEC_SDOUT_R
<12> HDA_CODEC_SDOUT
2

B 0_0402_5% Jason 6/24 B

AUD_AGND @ C2723 Short Pad R2720 1 @ 2 CODEC_BITCLK_R
SC22P50V2JN-4GP <12> HDA_CODEC_BITCLK 0_0402_5% Jason 6/24
1

R2718 1 2 33_0402_5% HDA_CODEC_SDIN0

<12> HDA_SDIN0
Close pin3 <12> HDA_CODEC_SYNC
HDA_CODEC_SYNC

HDA_CODEC_RST# 1 @ 2
<12> HDA_CODEC_RST#
R6515 D2701
0_0402_5% 3
<12> SPKR
C2720
1 AUD_PC_BEEP_C 1 2 1 2AUD_PC_BEEP
Short Pad
RE33 1KR2J-1-GP
2
Azalia I/F EMI
3234@=>@ <29> BEEP SCD1U16V2KX-3GP
Jason 6/24

1
BAT54C-7-F_SOT23-3
R2717
10KR2J-3-GP
HDA_CODEC_SDOUT
HDA_CODEC_BITCLK

2
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
@

@
2

2
EC2708

EC2709

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CODEC ALC3234/3246
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P 1.0(A00)

Date: Thursday, July 09, 2015 Sheet 23 of 64

5 4 3 2 1
 5 4 3 2 1

Main Func = Audio

Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power

EMI@ => @ SPK1

2 1 Jason 6/25 1 5
D
<23> AUD_SPK_R+ ShortPad R2904 2
@
1
0_0603_5% AUD_SPK_R+_C
2 1 G5 D
<23> AUD_SPK_R- ShortPad R2903 2
@
1
0_0603_5% AUD_SPK_R-_C
3 2
<23> AUD_SPK_L+ ShortPad R2902 2
@
1
0_0603_5% AUD_SPK_L+_C
4 3
<23> AUD_SPK_L- ShortPad R2901 @ 0_0603_5% AUD_SPK_L-_C
4 CONN Pin Net name
6 Pin1 SPK_R+
G6
ACES_50224-0040N-001_4P Pin2 SPK_R-

3
CONN@
Pin3 SPK_L+

AZ5125-02S.R7G_SOT23-3

AZ5125-02S.R7G_SOT23-3
1

1
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
Pin4 SPK_L-
DA13 DA14

2
EC2901

EC2902

EC2903

EC2904
@ESD@ @ESD@

1
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

C C

RE35 Universal Jack (Moved to I/O Board)

1 RE36 2
<23> MIC2_VREFO 1 2 EMI@ => @
Jason 6/25
2.2K_0402_5%
2.2K_0402_5% 2 1 0_0603_5%
<23> RING2
R2908 1 2 10R2F-L-GP
R2906
2
@
1 0_0603_5%
ShortPad RING2_R
RING2_R <39>
<23> AUD_HP1_JACK_L 1 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
AUD_HP1_JACK_L1 R2907 @ ShortPad AUD_PORTA_L_R_B AUD_PORTA_L_R_B <39>
<23> LINE1_L C2907 10U_0603_10V6M R2912 1 2 4K7R2J-2-GP JACK_PLUG
<23> LINE1_VREFO_L JACK_PLUG <39>
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 R2909 2 @ 1 0_0603_5% ShortPad AUD_PORTA_R_R_B AUD_PORTA_R_R_B <39>
<23> AUD_HP1_JACK_R 1 2 LINE1-L_R R2921 1 2 1KR2J-1-GP 2 1 0_0603_5%
<23> LINE1_R C2908 10U_0603_10V6M R2913 1 2 4K7R2J-2-GP
R2911 @ ShortPad SLEEVE_R
SLEEVE_R <39>
<23> LINE1_VREFO_R

R2920 @

EC2908

EC2907

R2919 @

EC2906

EC2905
1

1
<23> SLEEVE

1
SC100P50V2JN-3GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP
2

2
10KR2J-3-GP

10KR2J-3-GP
2

2
Layout Note: Jason 6/25
B
Close to HDA27 ShortPad B
R2923
0_0603_5%
JACK_PLUG 10 mils 1 @ 2 10 mils
AUD_AGND AUD_AGND AUD_SENSE <23>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPKR/JACK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 24 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

Layout:
For RTL8111G(S) C3021: colse to Pin8
* Place C3021 to C3024 close to each VDD10 pin--3, 8, 22, 30 C3022 close to Pin30

LAN CHIP (10/100/1000M & 10/100M co-lay)

For RTL8106E C3023: close to Pin3
* Place C3021,C3022 close to each VDD10 pin-- 8, 30 C3024: close to Pin22

R3001
REGOUT 1 2 VDD10
D C3002,R3001: 0R3J-0-U-GP D
Only for

LAN_SW@ C3012

LAN_SW@ C3019

LAN_SW@ C3023

LAN_SW@ C3024
SCD1U16V2KX-3GP
1000@
RTL8111 LDO mode.
1000@
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
R3032 C3014
L3001 2K49R2F-GP LAN_TXP_C_PCH_RXP6 1 2 SCD1U16V2KX-3GP
PCIE_PRX_LANTX_P6 <10>
1

1
1 2 RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CGT 1 2 LAN_TXN_C_PCH_RXN6 1 2 SCD1U16V2KX-3GP
PCIE_PRX_LANTX_N6 <10>
IND-4D7UH-242-GP C3016
C6205
LAN_SW@ PCIE_PTX_LANRX_P6_C 1 2 SCD1U16V2KX-3GP
PCIE_PTX_LANRX_P6 <10>
2

2
1 2 SCD1U16V2KX-3GP
C3002

C3021

C3022
71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003 PCIE_PTX_LANRX_N6_C
PCIE_PTX_LANRX_N6 <10>
C6206

SWR mode LDO mode SWR mode LDO mode CLK_PCIE_LAN_P2 <11>
CLK_PCIE_LAN_N2 <11>

3D3V_LAN_S5

LANXOUT
10/100/1000M 10/100/1000M 10/100M 10/100M

LANXIN
VDD10
LED0 1 TP3003 TPAD14-OP-GP

RSET
LED1 1 TP3002 TPAD14-OP-GP
Layout: LED2 1 TP3001 TPAD14-OP-GP
For RTL8111G(S) LOM30 1000@
* Place C3007 and C3008 close to each VDD33 pin-- 11, 32
100@

32
31
30
29
28
27
26
25
For RTL8106E LOM30
* Place C3003 and C3008 close to each VDD33 pin-- 23, 32

(GPO) LED1/GPO
AVDD33

AVDD10
CKXTAL2
CKXTAL1
LED0

(LED1) LED2
RSET
33
GND
ShortPad RTL8111G-CG QFN 32P E-LAN CTRL
3D3V_LAN_S5 VDDREG
R3006 SA00005V700
0_0603_5% C3018 1 2
40 mils 1 @ 2 1
(NC) REGOUT
24 REGOUT SC1U10V2KX-1GP
<26> LAN_MDI0P 2 MDIP0 23 VDDREG C3025 1 2 SCD1U16V2KX-3GP
<26> LAN_MDI0N MDIN0 (DVDD33) VDDREG
1

3 22 +3VS
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

LAN_SW@

LAN_SW@
Jason 6/25 VDD10 VDD10
AVDD10 (NC) (NC) DVDD10
1

4 21
LAN_SW@

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
PCIE_WAKE#
<26> LAN_MDI1P MDIP1 LANWAKE# PCIE_WAKE# <11,29>
5 20 2 1
100@

C3008: close to Pin32 ISOLATE#

<26> LAN_MDI1N MDIN1 ISOLATE#
2

1
6 19
C3007

C3008

C3009

C3010
C3007: close to Pin11 (071.08106.0003) PLT_RST#_LAN R3014
<26> LAN_MDI2P MDIP2 (NC) PERST#
2

1
7 18
C3003

LAN_TXN_C_PCH_RXN6 1KR2J-1-GP
C3003: close to Pin23 <26> LAN_MDI2N VDD10 8 MDIN2 (NC) HSON 17 LAN_TXP_C_PCH_RXP6 R3015
AVDD10 HSOP
2

2
15KR2J-1-GP

AVDD33 (NC)

REFCLK_N
REFCLK_P
MDIP3 (NC)
MDIN3(NC)
X5R

CLKREQ#

2
HSIN
HSIP
C C
RTL8106E-CG_QFN32 Manual: 071.08106.0003

9
10
11
12
13
14
15
16
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
3D3V_LAN_S5 RTL8106E-CG (071.08106.0003): 10/100M <70mW.
3D3V_LAN_S5
<26> LAN_MDI3P
<26> LAN_MDI3N
1

1
@

C3004 C3005 3D3V_LAN_S5

10K_0402_5%
RE37

10K_0402_5%
RE38

CLK_LAN_REQ2#_R

1
PCIE_PTX_LANRX_P6_C
@ @ PCIE_PTX_LANRX_N6_C
CLK_PCIE_LAN_P2
2Q402_1 2

2
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
CLK_PCIE_LAN_N2

@ Layout: 3D3V_LAN_S5
Q3003 LMBT3904LT1G-GP 3D3V_LAN_S5
C3004: close to Pin32
3 1 PLT_RST#_LAN
<11,29,32,36,56> PCH_PLTRST#_EC C3005: close to Pin11

1
C3011

@ R3003
10KR2J-3-GP
1 @ 2 LANXOUT 1 2

10KR2J-3-GP
1
@ R3004
R3016 10P_0402_50V8J

2
0_0402_5% 3D3V_LAN_S5 rise time must be controlled

CLK_LAN_REQ#_EN
Jason 6/24 between 0.5 mS and 100 mS.
Short Pad

2
+3VALW 3D3V_LAN_S5 X3001
Q3004 XTAL-25MHZ-181-GP
NTK3139PT1G_SOT723-3
85mA 3 1
S

2
@
Q3002 LMBT3904LT1G-GP
1

1 3
SCD1U16V2KX-3GP
@ C3017

CLK_LAN_REQ2#_R
G

<11> CLK_PCIE_LAN_REQ#
1

B C3013 R3021 B
1
SCD1U16V2KX-3GP

10KR2J-3-GP C3015
2

SC1U10V2KX-1GP C3001 1 @ 2
R3022
2

LANXIN 1 2
2

1 2 PM_LAN_ENABLE_R R3005
10P_0402_50V8J 0_0402_5%
LAN_ENABLE_R_C

Jason 6/24
20KR2J-L2-GP
<29> LAN_EN Short Pad
1

R3023
2

100KR2J-1-GP
G
2

3 1
1.0V Source
R3001 C3002 C3023 C3024 C3007 L3001 C3012 C3019 C3009 C3010 C3003
S

Q3001
2N7002K_SOT23-3

RTL8111G-CGT LDO
O O O O O X X X X X X
(71.08111.U03)

RTL8111GUS-CG
(71.08111.W03)/ SWR X X O O O O O O O O X
RTL8106EUS-CG
(71.08106.003)

A RTL8106E-CG A

(071.08106.0003) LDO X X X X X X X X X X O

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8106/8111
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P 1.0(A00)

Date: Thursday, July 09, 2015 Sheet 25 of 64

5 4 3 2 1
 5 4 3 2 1

Main Func = LAN

LAN TransFormer (10/100/1000M & 10/100M co-lay)

EU3101
LAN_MDI0P 1 9 LAN_MDI0P
D D
LAN_MDI0N 2 8 LAN_MDI0N

MCT1 LAN_MDI1P 4 7 LAN_MDI1P

MCT3
MCT2 LAN_MDI1N 5 6 LAN_MDI1N
MCT0

<25> LAN_MDI3N XF3102 @

1 2 3
EC3108@ SC10P50V2JN-4GP 6 7 MDO3-
5 TD- TX- 8 MDO3+
TD+ TX+

2
2
2
2
4 9

R3104
R3103
R3102
R3101
<25> LAN_MDI3P MCT0 @ESD@
1 2 TDCT TXCT
EC3107@ SC10P50V2JN-4GP EU3102
3 10 MCT1 LAN_MDI2P 1 9 LAN_MDI2P
2 RDCT RXCT 11

75_0603_5%
75_0603_5%
75_0603_5%
75_0603_5%
<25> LAN_MDI2N MDO2-
RD- RX-

1
1
1
1
1 2 1 12 MDO2+ LAN_MDI2N 2 8 LAN_MDI2N
EC3106@ SC10P50V2JN-4GP RD+ RX+
LAN_MDI3P 4 7 LAN_MDI3P

MCT
<25> LAN_MDI2P NS14-1 LF 10/100 BASE-TX
1 2 LAN_MDI3N 5 6 LAN_MDI3N
EC3105@ SC10P50V2JN-4GP

1
C3101 3
SC100P3KV8JN-2-GP

2
LANGND @ESD@
C C

<25> LAN_MDI1N XF3101 @

1 2
EC3104@ SC10P50V2JN-4GP 1 12 MDO1-
2 RD+ RX+ 11 MDO1+
3 RD- RX- 10 MCT2 LANGND
<25> LAN_MDI1P RDCT RXCT
1 2
EC3103@ SC10P50V2JN-4GP
4 9 MCT3 RJ45
5 TDCT TXCT 8 MDO0-
LOM_TCT

<25> LAN_MDI0N TD+ TX+

1 2 6 7 MDO0+
EC3102@ SC10P50V2JN-4GP TD- TX-

<25> LAN_MDI0P NS14-1 LF 10/100 BASE-TX

1 2 MDO0+ 1 10
EC3101@ SC10P50V2JN-4GP TX0+ GND
MDO0- 2 9
TX0- GND
MDO1+ 3
RX1+
1

C3106
SCD01U50V2KX-1GP MDO2+ 4
TX2+
Layout note: Layout note:
2

MDO2- 5
30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs. TX2-
MDO1- 6
RX1-
Follow Reference Schematic 0.01uF~0.4uF
MDO3+ 7
TX3+
MDO3- 8
B TX3- B

XF3102 SANTA_130456-661
CONN@
SP050007K00
1000@
Main:
S X'FORM_ NS14-1 LF 10100 BASE-TX SP050007K00, S X'FORM_ HD-081-A LAN
XF3101 2nd:
SP050008L00, S X'FORM_ NS681677 LAN
SP050007K00 Jason 2015/04/27

S X'FORM_ NS14-1 LF 10100 BASE-TX

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XFOM&RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 26 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = Card Reader

The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA

+3VS 3D3V_CARD_S0
D D

SDREFG 1 2

1
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
C3206

C3203

C3205
1 2 V18 SC1U10V2KX-1GP

2
C3201
SC1U10V2KX-1GP For EMI
Layout: close to U3201
EMI@

24

23
4

7
Short Pad U3201 EC3201 1 2

SDREG
3V3_IN
V18

CARD_3V3

XD_D7
XD_CD#
R3202 Jason 6/24 SC10P50V2JN-4GP
0_0402_5%
<28> SD_WP 1 @ 2 SD_WP_5170 8 15 SD_CLK_5170 R3201 1 EMI@ 2 SD_CLK <28>
9 SP1 SP8 16 33R2J-2-GP
10 SP2 SP9 18
<28> SD_D1 SP3 SP10 SD_CMD <28>
<28> SD_D0 11 19
C 12 SP4 SP11 20 C
SP5 SP12 SD_D3 <28>
<28> SD_CD# 13 21 SD_D2 <28>
14 SP6 SP13 22
SP7 SP14

GPIO0
RREF

GND
DM
DP
RTS5170-GR-GP

2
3

17

25
RREF
USB_PN6_R

1
USB_PP6_R CR_GPIO0 1 TP3201 3D3V_CARD_S0

R3203
6K2R2F-GP

1
@
SCD1U16V2KX-3GP

SCD01U50V2KX-1GP
B B

2
R3204

C3202

C3204
0R2J-2-GP EMI@
1 2

TR3201
<10> USB_PN6 3 4 USB_PN6_R

<10> USB_PP6 2 1 USB_PP6_R

MCM1012B900F06BP_4P
@EMI@
USB2.0 90ohm
R3205 Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
0R2J-2-GP
1 2
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)
EMI@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5170
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 27 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = Card Reader

3D3V_CARD_S0

D D

3D3V_CARD_S0

CARD1
SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

SC10U10V5KX-2GP
400mA
1

1
4 NP1

@
VDD NP1 NP2
Short Pad Jason 6/24 NP2
2

2 2
C3301

C3302

C3303 <27> SD_CMD

5 CMD 12
<27> SD_CLK CLK 12
<27> SD_CD# R3301 1 @ 2 0_0402_5% SD_CD_R# 10 13
11 CD 13 14
<27> SD_WP WP 14 15
7 15
<27> SD_D0 DAT0
<27> SD_D1 8
9 DAT1 3
<27> SD_D2 DAT2 VSS
<27> SD_D3 1 6
CD/DAT3 VSS

CARDBUS11P-SKT-8-GP
C CONN@ C

2rd = 020.I0002.0001
For EMI Reserved SD_CMD 1 AFTP3302
SD_CLK 1 AFTP3303
SD_CD_R# 1 AFTP3304
SD_WP SD_WP 1 AFTP3305
SD_D0 1 AFTP3306
SD_D1 1 AFTP3307
SD_D0 SD_D2 1 AFTP3308
SD_D3 1 AFTP3309
3D3V_CARD_S0 1 AFTP3310
SD_CD_R#

SD_CMD

SD_D3

B SD_D2 B

SD_D1
EC3301

EC3302

EC3303

EC3304

EC3305

EC3306

EC3307
SC4D7P50V2BN-GP

SC4D7P50V2BN-GP

SC4D7P50V2BN-GP

SC4D7P50V2BN-GP

SC4D7P50V2BN-GP

SC4D7P50V2BN-GP

SC4D7P50V2BN-GP
1

@ @ @ @ @ @ @
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5170
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 28 of 64
5 4 3 2 1
 5 4 3 2 1

RPE2 10K_8P4R_5%
+3VALW Jason 6/25 +3VALW_EC UE1 EC@ RE345 EC@ SD034100280 10K_0402_1% +3VALW_EC +3VALW_EC
+3VALW
5 4 KSI0 RE343 SD034137280 13.7K_0402_1%
6 3 0_0603_5% SD034178280 17.8K_0402_1% Model ID Board ID
KSI1
EC Chip CPN

1
7 2 KSI2 2 @ 1 SD034221280 22.1K_0402_1%
8 1 KSI3 SD034270280 27K_0402_1% R2446 RE345
ShortPad Ra Ra

10U_0603_6.3V6M

0.1U_0402_10V7K

1000P_0402_50V7K
@EMI@

1000P_0402_50V7K
@EMI@

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1 1 2 2 SD034324280 32.4K_0402_1% 100K_0402_1% 100K_0402_1%

1
RPE3 10K_8P4R_5% MEC1404-NU-D0_VTQFP128_14X14 22.1K_0402_1% SD034374280 37.4K_0402_1% DIS@ @

CE89

CE62

CE65

CE66

CE67

CE68

CE69
SD034499280 49.9K_0402_1%

2
5 4 KSI4 SA000084410 SD034221280 SD034576280 57.6K_0402_1% MODEL_ID BOARD_ID

2
6 3 KSI5 2 2 1 1 SD034649280 64.9K_0402_1%
7 2

CE63

CE64
KSI6 RE345 For SD00000B180 73.2K_0402_1% 1 1

2
8 1

0.1U_0402_10V7K
C2403

0.1U_0402_10V7K
CE70
KSI7 Board ID Select SD000002780 82.5K_0402_1%
SD034931280 93.1K_0402_1% Rb R2407 Rb
SD034107380 107K_0402_1% 100K_0402_1% RE347
1 8 2 2
2 7
KSO0 ShortPad SD034120380 120K_0402_1% UMA@ 100K_0402_1%
KSO1 Pre-EVT 10K SD034137380 137K_0402_1%

1
3 6 KSO2 RE349 +3VALW_EC RE348 EVT 13.7K SD034154380 154K_0402_1%
D D
4 5 KSO3 0_0603_5% 0_0402_5% DVT1 17.8K SD034200380 200K_0402_1%
2 @ 1 +RTC_CELL_VBAT 2 @ 1 DVT2 22.1K SD034232380 232K_0402_1%
RPE4
+RTC_CELL Pilot TBD
1
1
100K_8P4R_5%
8
Jason 6/25 Short Pad SD034100380 100K_0402_1% EC_AGND EC_AGND
KSO4 CE73
2 7 KSO5 0.1U_0402_10V7K Jason 6/24
3 6 KSO6 2

122

103
4 5 KSO7 CE71

43
82

19
65
5
UE1 @
RPE5 54 1 2 +3VALW_EC

VBAT

VTR
VTR
VTR
VTR
VTR
VTR
100K_8P4R_5% VTR_33_18
1 8 KSO10 PECI_EC PBAT_CHG_SMBDAT 1 2
0.1U_0402_25V6 PECI_EC <12>
2 7 KSO11 KSO0 2 RE424 4.7K_0402_5%
GPIO027/KSO00/PVT_IO1

1
3 6 KSO12 KSO1 14 8 PBAT_CHG_SMBDAT PBAT_CHG_SMBCLK 1 2
GPIO015/KSO01/PVT_nCS GPIO007/SMB01_DATA/SMB01_DATA18 PBAT_CHG_SMBDAT <41,42>
4 5 KSO13 KSO2 15 9 PBAT_CHG_SMBCLK RE425 4.7K_0402_5%
GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 PBAT_CHG_SMBCLK <41,42>
KSO3 16 11 GPU_THM_SMBDAT GPU_THM_SMBDAT 1 2
GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 GPU_THM_SMBDAT <8,38,57>
RPE6 KSO4 37 12 GPU_THM_SMBCLK DE8 @ RE426 2.2K_0402_5%
GPIO045/BCM_nINT1/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 GPU_THM_SMBCLK <8,38,57>
100K_8P4R_5% KSO5 38 89 AZ5125-01H.R7G_SOD523-2 GPU_THM_SMBCLK 1 2
GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 SYS_PWROK <11>
1 8 KSO8 <38> KSI[0..7] KSO6 39 91 @ @ RE427 2.2K_0402_5%
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 L_BKLT_EN_EC <6>
2 7 KSO15 KSO7 50 96 PCIE_WAKE# 2 1
GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 SIO_SLP_SUS# <11,45,46,47>
3 6 KSO14 KSO8 46 97 PBAT_PRES# RE354 10K_0402_5%
<38> KSO[0..16] GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18 PBAT_PRES# <41,42>

2
4 5 KSO16 KSO9 68 RE441 1 2 10K_0402_5% +3VS TOUCHPAD_INTR# 1 2
KSO10 72 GPIO102/KSO09/CR_STRAP 40 FAN1_TACH RE440 100K_0402_5%
GPIO106/KSO10 GPIO050/TACH0 FAN1_TACH <38> 1
RPE7 KSO11 74 41 LID_CL_SIO#
100K_8P4R_5% KSO12 75 GPIO110/KSO11 GPIO051/TACH1 CE76 VREF_CPU
GPIO111/KSO12 +1.0V_PRIM
2 1 76 44 1 2
KSO9 KSO13
MEC1404 RESET_OUT#

0.1U_0402_25V6
KB_LED_PWM <38> 100P_0402_50V8J
RE389 100K_0402_5% KSO14 77 GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0 45 2 RE367 10K_0402_5%
GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 BEEP <23>

1
2 1 USB_EN# KSO15 86 ME_FWP_EC 1 2
92 GPIO125/KSO15 47

CE77
RE388 100K_0402_5% KSO16 @ RE357 1K_0402_5%
GPIO132/KSO16 GPIO056/PWM3 DGPU_PWROK <12,40,52>
2 1 BAT1_LED# 93 34 PCH_RSMRST# 1 2
<38> CAP_LED# GPIO140/KSO17 GPIO030/BCM_nINT0/PWM4 SUSACK# <11>

2
RE408 100K_0402_5% 35 RE355 10K_0402_5%
GPIO031/BCM_DAT0/PWM5 EC_WAKE# <11>
2 1 BAT2_LED# KSI0 98 36
GPIO143/KSI0/nDTR GPIO032/BCM_CLK0/PWM6 PS_ID <41>
RE409 100K_0402_5% KSI1 99 4 PCIE_WAKE#
GPIO144/KSI1/nDCD GPIO002/PWM7 PCIE_WAKE# <11,25>
2 1 PCH_ALW_ON KSI2 6
RE390 100K_0402_5% KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT1_LED#
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT1_LED# <37>
KSI4 104 106 BAT2_LED#
GPIO147/KSI4/nDSR GPIO156/LED1 BAT2_LED# <37>
C KSI5 105 70 SIO_SLP_S3# C
GPIO150/KSI5/nRI GPIO104/LED2 SIO_SLP_S3# <11,17,40,41,46,51>
KSI6 107 +3VALW
KSI7 108 GPIO151/KSI6/nRTS 80 ME_FWP_EC
GPIO152/KSI7/nCTS GPIO116/TFDP_DATA/UART_RX ME_FWP_EC <12>
81
HOST_DEBUG_TX <36> Short Pad
HOST_DEBUG_TX Jason 6/24
GPIO117/TFDP_CLK/UART_TX

1
78

100K_0402_5%
<38> CLK_TP_SIO GPIO114/PS2_CLK0
79 90 PTP_DIS#_R RE434 2 @ 1 0_0402_5% PTP_DIS#
<38> DAT_TP_SIO GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK PTP_DIS# <38>
52 94 1 2 43_0402_1%

RE25
PECI_MEC1404 RE353 PECI_EC
<11> SIO_PWRBTN# GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT
PCH_RSMRST# 88
<11> PCH_RSMRST# GPIO127/PS2_DAT1B 95 VREF_CPU RE26
VREF_CPU

2
LPC_LAD0 59 0_0402_5%
<8> LPC_LAD0 GPIO040/LAD0
LPC_LAD1 60 101 ICSP_CLK @ RE435 2 1 0_0402_5% EC_MUTE# LID_CL_SIO# 2 @ 1
<8> LPC_LAD1 GPIO041/LAD1 GPIO145/ICSP_CLOCK LID_CLOSE# <32,37>
LPC_LAD2 61 102 ICSP_DAT @ RE436 2 1 0_0402_5% PTP_DIS#
<8> LPC_LAD2 GPIO042/LAD2 GPIO146/ICSP_DATA
62 87 Short Pad

0.047U_0402_16V4Z
@EMI@
CE78
@EMI@
R2455
<8> LPC_LAD3
LPC_LAD3
58 GPIO043/LAD3 ICSP_MCLR
ICSP_CLR
Jason 6/24
Short Pad
<8> LPC_LFRAME# LPC_LFRAME#
GPIO044/nLFRAME

1
56 119 2 1 0_0402_5%

CE8
0.1U_0402_10V7K 0_0402_5% PCH_PLTRST#_EC EC_MUTE#_R RE433 @ EC_MUTE# Jason 6/24
<11,25,29,32,36,56> PCH_PLTRST#_EC GPIO064/nLRESET BGPO/GPIO004 EC_MUTE# <23>
2 1 1 2 57 120 1 2 +3VLP
@
63 GPIO034/PCI_CLK SYSPWR_PRES/GPIO003 121 RE356 1K_0402_5%
<8> CLK_PCI_LPC_MEC <8> CLKRUN# GPIO067/nCLKRUN VCI_OUT/GPIO036 ALWON <43>

2
55 126 VCI_IN1 RE437 1 2 100K_0402_5% +RTC_CELL
<8> SERIRQ GPIO063/SER_IRQ nVCI_IN1/GPIO162
10 127 POWER_SW_IN#
<6> SIO_EXT_SMI# GPIO011/nSMI/nEMI_INT nVCI_IN0/GPIO163

1
49 128

100K_0402_5%
<38> TP_PW_EN# GPIO060/KBRST VCI_OVRD_IN/GPIO164 ACAV_IN <11,42>
53
<8> SIO_RCIN# GPIO061/nLPCPD +3VALW_EC
66 23

RE358
3D_CAM_EN_EC
<10> SIO_EXT_SCI# GPIO100/nEC_SCI GPIO160/DAC_0 24 +RTC_CELL
GPIO161/DAC_1 FAN1_DAC_1 <38>
RE413 1 2 15_0402_1% EC_SPI_CLK 32 22

0.1U_0402_25V6
<8> PCH_SPI_CLK_0_R GPIO126/SHD_SCLK DAC_VREF

2
RE414 1 2 15_0402_1% EC_SPI_MOSI 28
<8> PCH_SPI_D0_0_R GPIO133/SHD_IO0

1
1 2 29 85

100K_0402_5%
RE416 15_0402_1% EC_SPI_MISO CMP_VOUT0
<8> PCH_SPI_D1_0_R GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VOUT0 <43>
1 2 30 20 1 2

CE79

RE31
R2405 @ 0R2J-2-GP SATA_LED#_R CMP_VIN0 @
<10,37> SATA_LED# GPIO135/SHD_IO2 GPIO020/CMP_VIN0 VCIN0_PH <38>
31 25 VCREF0 RE394 0_0402_5%
<37> SATA_LED#_R <11> RTCRST_ON GPIO136/SHD_IO3 GPIO165/CMP_VREF0

2
2 @ 1 EC_SPI_CS0# 27 Short Pad Jason 6/24
<8> PCH_SPI_CS#0_R1 GPIO123/SHD_nCS 83 H_PROCHOT_EC
GPIO120/CMP_VOUT1

2
RE410 67 21
<11,17,44> SIO_SLP_S4# GPIO101/SPI_CLK GPIO021/CMP_VIN1 GPU_PWR_LEVEL <57>
0_0402_5% 69 26 POWER_SW_IN# 1 2
<42> AC_DIS GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK LCD_TST <32> +3VALW POWER_SW#_MB <37>
Short Pad PCH_ALW_ON 71 +3VALW RE428 10K_0402_5%
<40> PCH_ALW_ON GPIO105/SPI_IO1
42 118 RE385 1 2 10K_0402_5%

1U_0402_6.3V6K
<11> ME_SUS_PWR_ACK CMP_STRAP0
GPIO052/SPI_IO2 GPIO024/CMP_STRAP0

1
Jason 6/24 <12,38> TOUCHPAD_INTR# TOUCHPAD_INTR# 33 117
GPIO062/SPI_IO3 GPIO023/ADC6/A20M PANEL_BKEN_EC <32>

1
3 116

CE12
<25> LAN_EN GPIO001/SPI_nCS/32KHZ_OUT GPIO022/ADC5 SIO_EXT_WAKE# <9>
109 MODEL_ID RE396
GPIO153/ADC4

2
B 13 110 I_ADP_R FW_UPDATE_EC 10K_0402_1% B
<31> USB_EN# nRESET_IN/GPIO014 GPIO154/ADC3
<11> ALL_SYS_PWRGD ALL_SYS_PWRGD RE438 2@ 1 0_0402_5% RUNPWROK 48 111 BOARD_ID
GPIO057/VCC_PWRGD GPIO155/ADC2
VSS_VBAT

RESET_OUT# 73 113 2 @ 1 0_0402_5%

<11> RESET_OUT# GPIO107/nRESET_OUT GPIO122/ADC1 I_SYS <42,48>

2
VR_CAP
Short Pad 114 I_BATT_R VCREF0
Jason 6/24 MEC_XTAL2 125 GPIO121/ADC0 115 RE442
AVSS

0.1U_0402_25V6
XTAL2 ADC_VREF
VSS
VSS
VSS
VSS
VSS

1
MEC_XTAL1 2 @ 1 MEC_XTAL1_R 123 For 3D-CAM 2015/Jason +3VALW_EC
XTAL1

1
RE397
+3VALW

CE91
RE366

0.1U_0402_25V6
10K_0402_1%
124

84
51
17
64
100

EC_AGND 112

18

+3VS
0.1U_0402_10V7K

0_0402_5% MEC1404-NU-TR_VTQFP128_14X14

2
1
Short Pad

1
CE81
1 @ T4931
32 KHz Clock
CE85

Jason 6/24 RE404

EC_AGND 2
Jason 6/25 100K_0402_5%
Y1 RE398
2 MEC_XTAL1 1 2 MEC_XTAL2 0_0603_5% VR_CAP 1 2

2
2 @ 1 RE399 300_0402_5%
5

32.768KHZ_9PF_X1A000141000200 C5224 1U_0603_16V7 I_ADP_R 1 2 CMP_VIN0 1 @ 2 CMP_VOUT0

I_ADP <42>
UE6 1 20ppm / 9pF 1 ShortPad 1 RE392 100K_0402_5%
P

4 2 H_PROCHOT_EC ESR <50kohm (MAX)

<12,41,42,48> H_PROCHOT# Y A C5225 C5226 Close UE1 ESR <100m ohms CE87 2200P_0402_25V7K EC_AGND
NC

2
G

10P_0402_50V8J 10P_0402_50V8J
SN74LVC1G06DCKR_SC70-5 RE380 2 2 EC_AGND
Close UE1 2
1
1

EC_AGND
100K_0402_5% Reserve to Control 3D Camera
CE86 3D@ PCH_PLTRST#_EC 1 2
47P_0402_50V8J SJ10000IN00 3D_CAM_EN_EC 1 2
3D_CAM_EN <9,64>
CE72 0.047U_0402_16V4Z
1

2 RB551V-30_SOD323-2 DE9 ESD@

SJ10000IA00 EC_AGND FW_UPDATE_EC 1
3D@
2
FAN1_TACH
CE75
1 2
220P_0402_50V8J
FW_UPDATE <9,64>
RB551V-30_SOD323-2 DE10 ESD@
SIO_SLP_S3# 1 2
CE74 0.1U_0402_10V7K
+3VALW RE400 300_0402_5% ESD@
Debug Connector pin6,7 need assign GPIO for multi function??? I_BATT_R 1 2
I_BATT <42>
RESET_OUT# 1 2
CE82 1000P_0402_50V7K
+3VS +3VALW
1
1

2 1
10K_0402_5%

10K_0402_5%

10K_0402_5%

100K_0402_5%

ACAV_IN
@ RE74

@ RE75

DB1 CONN@ JDEG1 CONN@ RE71 49.9_0402_1% CE88 2200P_0402_25V7K CE84 100P_0402_50V8J
1 2 1
RE72

RE73

A A
1
EC_AGND

12 10 2 2 1 2
11 GND 10 9 2 3
JTAG_TDI RE420
2 1
0_0402_5% ICSP_CLK Close to UE1 each pin
JTAG_TMS RE421 0_0402_5% ICSP_CLR
GND 9 3
2

8 LPC_LAD0 4 JTAG_CLK RE422 2 1 0_0402_5% T4932

8 7 LPC_LAD1 4 5 JTAG_TDO RE423 2 1 0_0402_5% ICSP_DAT @
7 6 LPC_LAD2 5 6 MSCLK
6 5 LPC_LAD3 6 7 MSDATA EC_AGND
5 4 LPC_LFRAME# 7 8 HOST_DEBUG_TX
4 3 11 8 9
3 PCH_PLTRST#_EC <11,25,29,32,36,56> GND 9
2 12 10
2 1 GND 10 Pin8 5085_TXD for EC Debug
1
ACES_51522-01001-001
CLK_PCI_LPDEBUG <8>
ACES_51522-01001-001
pin9 5048_TXD for SBIOS
debug
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

SP01001AL00 SP01001AL00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC MEC1404
Size Document Number Rev
CIS Link OK CIS Link OK AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 29 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1 USB3.0 Port1

USB2.0 Port2 and USB2.0 Port3 are on IOBD
USB2.0 90ohm
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
2 @EMI@ 1
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
R3403 0R2J-2-GP 3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U) USB1

U3402 1 2 USB_PN1_C
USB30_VCCC VBUS D-
TR3404 USB3_PRX_CTX_N0_C 1 1 10 9USB3_PRX_CTX_N0_C 3 USB_PP1_C
2 1 USB_PN1_C D+
<10> USB_PN1
D USB3_PRX_CTX_P0_C 2 2 9 8USB3_PRX_CTX_P0_C USB3_PRX_CTX_N0_C 5 D
STDA_SSRX-

3
USB3_PRX_CTX_P0_C 6 7
3 4 4 4 STDA_SSRX+ GND_DRAIN
<10> USB_PP1 USB_PP1_C USB3_PTX_CRX_N0_C 7 7USB3_PTX_CRX_N0_C ESD@

3
USB3_PTX_CRX_N0_C 8
5 5 STDA_SSTX- AZC199-02SPR7G_SOT23-3
MCM1012B900F06BP_4P USB3_PTX_CRX_P0_C 6 6USB3_PTX_CRX_P0_C USB3_PTX_CRX_P0_C 9 10
STDA_SSTX+ GND 11 EU3403

1
EMI@
3 3 12 GND 4
CHASSIS#12 GND

1
13
8 CHASSIS#13
2 @EMI@ 1
R3404 0R2J-2-GP L05ESDL5V0NA-4_SLP2510P8-10-9 SKT-USB13-111-GP
ESD@
CONN@

USB3.0 90ohm USB3.0 90ohm

Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP) Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP)
USB30_VCCC 1 AFTP3401
2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T) 2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
C3404
3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U) 3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)

1 2 USB3_PTX_CRX_P0_R 2 EMI@ 1 USB3_PTX_CRX_P0_C <10> USB3_PRX_CTX_P0

2 EMI@ 1 USB3_PRX_CTX_P0_C
<10> USB3_PTX_CRX_P0 R3408 0R2J-2-GP R3410 0R2J-2-GP
SCD1U16V2KX-3GP
@EMI@ @EMI@
HCM1012GH900BP_4P HCM1012GH900BP_4P
3 4 3 4
C C

2 1 2 1

TR3402 TR3403

C3403

1 2 USB3_PTX_CRX_N0_R 2 EMI@ 1 USB3_PTX_CRX_N0_C <10> USB3_PRX_CTX_N0 2 EMI@ 1 USB3_PRX_CTX_N0_C

<10> USB3_PTX_CRX_N0 R3409 0R2J-2-GP R3411 0R2J-2-GP
SCD1U16V2KX-3GP

USB2 (USB2.0) CMC

USB2.0 90ohm
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
1 @EMI@ 2
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
R3412 0R2J-2-GP
3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)
B
3
TR3405
4 USB_PN2_C
USB ESD Diode B

<10> USB_PN2 USB_PN2_C <39>

EU3404 @ESD@ USB20_VCCA
<10> USB_PP2 2 1 USB_PP2_C
USB_PP2_C <39> 1 6
USB_PP2_C USB_PN2_C
MCM1012B900F06BP_4P I/O1 I/O4
EMI@ 2 5
GND VDD
3 4

SCD1U16V2KX-3GP
USB_PP3_C USB_PN3_C
I/O2 I/O3

1
1 @EMI@ 2

C3406
@
R3413 0R2J-2-GP
AZC099-04S-1-GP

2
USB3 (USB2.0) CMC USB2.0 90ohm
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
1 @EMI@ 2
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
R3414 0R2J-2-GP
3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)

TR3406
<10> USB_PN3 2 1 USB_PN3_C
USB_PN3_C <39>

<10> USB_PP3 3 4 USB_PP3_C

USB_PP3_C <39>

A MCM1012B900F06BP_4P A
EMI@

1 @EMI@ 2
R3415 0R2J-2-GP
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 30 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = USB3.0 Port1

USB3.0 Port1 Layout Note: Close USB1
USB30_VCCC
USB30_VCCC
2A
+5VALW U3504
1
5 OUT
IN 2

C3507
SCD1U16V2KX-3GP

C3508
SC1U10V2KX-1GP

C3512
SC22U6D3V5MX-2GP

C3513
SC22U6D3V5MX-2GP

TC3501
SC100U6D3V6MX-GP
D D
GND

1
4

@
USB_EN#
EN
1

Active Low 3 USB_OC#0_1 <10,31>

C3510 OCB

2
SC1U10V2KX-1GP SY6288D20AAC_SOT23-5
2

Main Func = USB2.0 Port3

USB2.0 Port3 (IO Board)
Support 2A
USB20_VCCA USB20_VCCA
+5VALW
U3505 2A
1
5 OUT
IN 2

C3517
SCD1U16V2KX-3GP

C3518
SC1U10V2KX-1GP

C3515
SC22U6D3V5MX-2GP
GND

1
4

@
C <29> USB_EN# Active Low EN 3 C
OCB USB_OC#2_3 <10>
1

2
1

C3504 SY6288D20AAC_SOT23-5
2

R3501 Short Pad

SCD1U16V2KX-3GP

0_0402_5%
Jason 6/24
2

USB_OC#0_1 <10,31>

Main Func =

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Power SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 31 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = LCD LCDVDD_LCD LCDVDD INVERTER POWER Main Func = CAM
R5211 @ R5214
1 2 +19VB 1 2 DCBATOUT_LCD
LCD1 0R5J-5-GP 0R5J-5-GP
41 EE note: Never change R5211 to short pad after MP
F5201 800mA
1 1 2

2 LCDVDD_LCD

C5205 @
SCD1U50V3KX-GP

C5202
SC1KP50V2KX-1GP
DCBATOUT_LCD SMD1812P150TF/24 1.5A UL/CSA/TUV

1
3 +3VS
4 Trace width = 80mil EE note: Never change R5229 to short pad after MP
5

C5201
C5206
Reserved for one time fuse: 69.43001.201

2
6

1
7 SC1U10V2KX-1GP +3VS 3D3V_CAMERA_S0
8 DBC_EN_R R6507 +3VS

1
9

SCD1U16V2KX-3GP
EDP_HPD_CONN 10KR2J-3-GP
10 LCD_TST_C R5229
D 11 EDP_AUX 1 2 D

1
12 EDP_AUX#
13 R5213

SC33P50V2JN-3GP
EC5210 @

C5207
SC4D7U6D3V3KX-GP
For ESD R5208 0R3J-0-U-GP

1
14 EDP_TX0# DBC_EN_R 1 2 10KR2J-3-GP DMIC_CLK_EDP R5207 1 2 33R2J-2-GP
DBC_EN <9> DMIC_CLK <23>
15 EDP_TX0 DMIC_DATA_EDP R5215 1 2 33R2J-2-GP
DMIC_DATA <23>
16
0R2J-2-GP R5210

2
17

SC6D8P50V2DN-GP
EC5205 @

SC6D8P50V2DN-GP
EC5206 @
EDP_TX1#

1
18 EDP_TX1 PANEL_SIZE_ID_CONN 1 2
19 PANEL_SIZE_ID <9>
20 LCD_BRIGHTNESS 100R2J-2-GP For AUDIO Grade B or C selection.

2
21 BLON_OUT_C
22 PANEL_SIZE_ID_CONN R5209 @
23 0R2J-2-GP
24 Layout Note: Reduce the stubs.
25

2
26 Intel PDG (#514849):
MIC_GND
27 DMIC_CLK_EDP Recommends having a pull-up resistor of 100 kΩ for AUXN
28 DMIC_DATA_EDP and a pull-down resistor of 100 kΩ for AUXP
29 between the AC capacitor and the connector,
30 USB_CAMERA_EDP# to assist source detection by the sink device.
31 USB_CAMERA_EDP
32
3D3V_CAMERA_S0
33 1 EMI@ 2
34 USB_PN7_TPNL EDP_AUX R5218 1 @ 2 100KR2J-1-GP R5216 0R2J-2-GP
35 USB_PP7_TPNL
36 EDP_AUX# R5219 1 @ 2 100KR2J-1-GP MCM1012B900F06BP_4P
+3VS
37 TP_RS USB_CAMERA_EDP# 1 2
USB_PN5 <10>
38 TP_RESET
39
40 USB_CAMERA_EDP 4 3
TPAN_VDD USB_PP5 <10>
RN5203
42 1 8 BKLT_CTRL TR5209 @EMI@
2 7 BLON_OUT_C PANEL_BKEN_EC <29>
3 6 EDP_HPD USB2.0 90ohm
Layout Note: 4 5 1 EMI@ 2 Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
ACES_51540-04001-P01_40P-T R5217 0R2J-2-GP
CONN@
Colse to LCD1. R5222 1 2 0R2J-2-GP
2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
SRN100KJ-5-GP @ 3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)

1 @ 2 D5202
RN5201 2 eDP_BKLT_CTRL
C R5201 BLON_OUT_C 1 8 C
0_0402_5% LCD_BRIGHTNESS 2 7 BKLT_CTRL 1
Jason 6/24 LCD_TST_C 3 6 LCD_TST
EDP_HPD_CONN 4 5 3 LCD_TST
Short Pad EDP_HPD <6>
MIC_GND
SRN100J-4-GP
BAT54C-7-F_SOT23-3
EC (BIST MODE)

1 2 SCD1U16V2KX-3GP EDP_TX0#
Main Func = TS
<6> EDP_TX0_DN C5203
C5210 1 2 SCD1U16V2KX-3GP EDP_TX0 +3VS +5VS
<6> EDP_TX0_DP
TPAN_VDD

1
@ R5231
1 2 SCD1U16V2KX-3GP

0R3J-0-U-GP

R5230
0R3J-0-U-GP
C5211 EDP_TX1#
<6> EDP_TX1_DN
<6> EDP_TX1_DP C5213 1 2 SCD1U16V2KX-3GP EDP_TX1 Touch Panel
R5205
TP_RS 1 2
TOUCH_SCREEN_PD# <12>

1
1 2 SCD1U16V2KX-3GP

C5208
SC10P50V2JN-4GP SC10P50V2JN-4GP
C5209 EDP_AUX# F5203 @ 33R2J-2-GP
<6> EDP_AUX_DN D5203
1 2 SCD1U16V2KX-3GP 1 2

@
C5212 EDP_AUX TPAN_VDD_F
<6> EDP_AUX_DP
LID_CLOSE# 1 2 TOUCH_SCREEN_PD#
<29,37> LID_CLOSE#

2
Brightness 1.1A_24V_SMD1812P110TF-24
R5232 2 1 0R3J-0-U-GP
1 2 eDP_BKLT_CTRL RB551V-30_SOD323-2
@
<6> L_BKLT_CTRL R5212
R5206 EE note: Never change R5232 to short pad after MP TP_RESET 1 @ 2
PCH_PLTRST#_EC <11,25,29,36,56>
0_0402_5%
Reserved for one time fuse: 69.43001.201

1
C5214
Jason 6/24
0R2J-2-GP

@
Short Pad

2
LCDVDD
D5201
2
<6> EDP_VDD_EN
1 LCDVDD_EN
USB_PN7_TPNL 1 EMI@ 2
USB_PN7 <10>
B 3 R5203 0R2J-2-GP B
<29> LCD_TST
2

+3VS
R5202 MCM1012B900F06BP_4P
BAT54C-7-F_SOT23-3 100KR2J-1-GP 1 2 USB2.0 90ohm
U5201 Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
LCDVDD 2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
1

1 5 4 3
2 EN VIN#5 3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)
3 GND 4 TR5201 @EMI@
VOUT VIN#4
1

C5204
RT9724GB-GP SC4D7U6D3V3KX-GP USB_PP7_TPNL 1 EMI@ 2 USB_PP7 <10>
R5204 0R2J-2-GP
2

Layout Note:
Trace width = 80mil

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD/Inverter CONN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P 1.0(A00)

Date: Thursday, July 09, 2015 Sheet 32 of 64

5 4 3 2 1
 5 4 3 2 1

Main Func = HDMI HDMI@EMI@

R5401
HDMI@EMI@
R5403
HDMI_CLK#_R 1 2 5.6_0402_1% HDMI_CLK#_R_C HDMI_DATA0#_R 1 2 5.6_0402_1% HDMI_DATA0#_R_C

@EMI@ @EMI@
HCM1012GH900BP_4P HCM1012GH900BP_4P

1
C5402 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_CLK#_R 3 4 HDMI@EMI@ 3 4 HDMI@EMI@
<6> HDMI_CLK# C5403 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_CLK_R R5414 R5416
<6> HDMI_CLK 150R2J-L1-GP-U 150R2J-L1-GP-U
C5404 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_DATA0#_R 2 1 2 1
<6> HDMI_DATA0# C5405 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_DATA0_R
<6> HDMI_DATA0

2
D TR5401 TR5402 D

HDMI_DATA1# C5409 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_DATA1#_R

1 2 HDMI@ R5402 R5404
HDMI_DATA1 C5406 SCD1U16V2KX-3GP HDMI_DATA1_R
HDMI_CLK_R 1
HDMI@EMI@ 2 5.6_0402_1% HDMI_CLK_R_C HDMI_DATA0_R 1
HDMI@EMI@ 2 5.6_0402_1% HDMI_DATA0_R_C
HDMI_DATA2# C5407 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_DATA2#_R
HDMI_DATA2 C5408 1 2 HDMI@ SCD1U16V2KX-3GP HDMI_DATA2_R

R5405 R5407
HDMI_DATA2#_R 1
HDMI@EMI@ 2 5.6_0402_1% HDMI_DATA2#_R_C HDMI_DATA1#_R 1
HDMI@EMI@ 2 5.6_0402_1% HDMI_DATA1#_R_C

8
7
6
5

8
7
6
5
RN5402 RN5403
SRN470J-3-GP SRN470J-3-GP
HDMI@ HDMI@ @EMI@ @EMI@
HCM1012GH900BP_4P HCM1012GH900BP_4P

1
3 4 HDMI@EMI@ 3 4 HDMI@EMI@

1
2
3
4

1
2
3
4
HDMI_PLL_GND R5415 R5417
150R2J-L1-GP-U 150R2J-L1-GP-U
2 1 2 1

2
R5418 TR5403 TR5404
1

+5VS @ 0R2J-2-GP
D Q5403
2 2N7002K_SOT23-3

1
G HDMI@
R5406 R5408
S
C HDMI_DATA2_R 1 2 5.6_0402_1% HDMI_DATA2_R_C HDMI_DATA1_R 1 2 5.6_0402_1% HDMI_DATA1_R_C C
3

R5413
HDMI@EMI@ HDMI@EMI@
1 2

100KR2J-1-GP
@

5V_HDMI_CRT_S0_R
RE39 2 HDMI@ 1 0_0402_5% HDMI_DATA1#
<6,34> HDMI_CRT_N1 RE40 2 HDMI@ 1 0_0402_5% HDMI_DATA1
<6,34> HDMI_CRT_P1

HDMI CONN

1
C5401
SCD1U16V2KX-3GP
RE41 2 HDMI@ 1 0_0402_5% HDMI_DATA2# HDMI@
<6,34> HDMI_CRT_N0

2
RE42 2 HDMI@ 1 0_0402_5% HDMI_DATA2
<6,34> HDMI_CRT_P0

JHDMI
HPD_HDMI_CON 19
18 HP_DET
17 +5V
+5VS DDC_DATA_HDMI 16 DDC/CEC_GND
DDC_CLK_HDMI 15 SDA
14 SCL
Reserved
1

13
B
D5401 HDMI_CLK#_R_C 12 CEC B
BAW56W_SOT323-3 11 CK- 23
HDMI@ HDMI_CLK_R_C 10 CK_shield GND3 22
HDMI_DATA0#_R_C 9 CK+ GND2 21
8 D0- GND1 20
D0_shield GND0
3

HDMI_DATA0_R_C 7
HDMI_DATA1#_R_C 6 D0+
5 D1-
DDC_DATA_PH2

D1_shield
DDC_CLK_PH1

HDMI_DATA1_R_C 4
HDMI_DATA2#_R_C 3 D1+
2 D2-
HDMI_DATA2_R_C 1 D2_shield
D2+
+3VS C-K_96067-3K28-192-124
CONN@
R5411
2

+3VS 150K_0402_5%

1
RE43 RE44 Q5401 C HDMI@
2.2K_0402_5% 2.2K_0402_5% LMBT3904LT1G-GP 2 HDMI_HPD_B 2 1
HDMI@ HDMI@ HDMI@ B

1
Q5402 HDMI@ E
1

3
HDMI@ R5410 @
4 3 DDC_CLK_HDMI <6,34> HDMI_CRT_DET
1 2 HDMI_HPD_E 200KR2F-L-GP
<6> PCH_HDMI_CLK
1

5 2 R5419

2
0R2J-2-GP R5412
6 1 10KR2J-3-GP
HDMI@
A DMN66D0LDW-7_SOT363-6 A
2

<6> PCH_HDMI_DATA
DDC_DATA_HDMI

2nd = 84.2N702.E3F
3rd = 75.00601.07C
Security Classification Compal Secret Data Compal Electronics, Inc.
4th = 84.DMN66.03F Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI L.Shifter/Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 33 of 64
5 4 3 2 1
 5 4 3 2 1

CRT_R 1
CRT_G 1 AFTP5501 AFTE14P-GP
CRT_B 1 AFTP5502 AFTE14P-GP
5V_HDMI_CRT_S0_R 1 AFTP5503 AFTE14P-GP
CRT_DDCDATA_CON 1 AFTP5504 AFTE14P-GP
5V_HDMI_CRT_S0_R CRT_DDCCLK_CON 1 AFTP5505 AFTE14P-GP
CRT_VSYNC_CON 1 AFTP5506 AFTE14P-GP
CRT_HSYNC_CON 1 AFTP5507 AFTE14P-GP
AFTP5508 AFTE14P-GP
JCRT +5VS

D 6 D
AFTE14P-GP 1 CRT_NC 11 5V_HDMI_CRT_S0_R
AFTP5509 CRT_R 1
7 16 F5501 D5501
G
CRT_DDCDATA_CON 12 17 1 2 1 2
CRT_G 2 G 18
G
8 19 RB551V-30_SOD323-2
G
CRT_HSYNC_CON 13 1.1A_6V_SPR-P110
CRT_B 3
9
CRT_VSYNC_CON 14
4
10
CRT_DDCCLK_CON 15
5

1
C5519

SCD01U16V2KX-3GP
@ C-K_80461-5K1-152
CONN@

2
CRT RGB
CRT_DDCDATA_CON CRT H/VSYNC
CRT SMBUS
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON

1
@
C5516
SC100P50V2JN-3GP

@
C5513
SC18P50V2JN-1-GP

@
C5507
SC18P50V2JN-1-GP

@
C5511
SC100P50V2JN-3GP
2

2
CRT@ L5503
DP_CRT_R 1 2 CHILISIN NBQ160808T-800Y-N 0603 CRT_R
C C
CRT@ L5501
DP_CRT_G 1 2 CHILISIN NBQ160808T-800Y-N 0603 CRT_G

CRT@ L5502
DP_CRT_B 1 2 CHILISIN NBQ160808T-800Y-N 0603 CRT_B

5V_HDMI_CRT_S0_R
C5506

C5512

C5509

CRT@
1 2 33R2J-2-GP
R5501

R5513

R5514

10P_0402_50V

10P_0402_50V

10P_0402_50V

C5514

10P_0402_50V

C5510

10P_0402_50V

C5518

10P_0402_50V
DP_CRT_HSYNC_CON R5511 CRT_HSYNC_CON
1

1
75_0402_1%

75_0402_1%

75_0402_1%

DP_CRT_VSYNC_CON R5507 1 2 33R2J-2-GP CRT_VSYNC_CON

CRT@

CRT@

CRT@
2

2
CRT@

CRT@

CRT@

CRT@

CRT@

CRT@

CRT@

2
2
2

RE45 RE46
2.2K_0402_5% 2.2K_0402_5%
CRT@ CRT@

1
1
CRT_DDCDATA_CON

CRT_DDCCLK_CON
Layout note:
All cap need close to chip
U5502
CRT@
2 1 AVCC33 24 1 CRT_PCH_HPD CRT_PCH_HPD R5517 1 2 0R2J-2-GP
AVCC_33 HPD HDMI_CRT_DET <6,33>
SCD1U16V2KX-3GP C5517 CRT@
+3VS AVCC33 2 1 VCCK_12 25 2
ShortPad AVCC_12 SMB_SCL PCH_SMBCLK <8,20,21>

1
SCD1U16V2KX-3GP C5503 CRT@ 3
2 1 +3VS 5 SMB_SDA PCH_SMBDAT <8,20,21>
R5504 R5510
0_0603_5% SCD1U16V2KX-3GP2 1 C5520 CRT@ +3VS 20 DVCC_33 4 CRT_DDCCLK_CON 100KR2J-1-GP
1 @ 2 SCD1U16V2KX-3GP C5522 CRT@ DVCC_33 VGA_SCL 6 CRT_DDCDATA_CON CRT@
2 1 VCCK_12 19 VGA_SDA
VCCK_12

2
CRT@ => @ SCD1U16V2KX-3GP2 1 C5501 CRT@
2

Jason 6/25 C5523 2

SC2D2U10V3KX-1GP 1 C5504 CRT@ 9 7 DP_CRT_VSYNC_CON
SC10U6D3V3MX-GP SCD1U16V2KX-3GP2 1 C5524 CRT@ VDD_DAC_33 VDD_DAC_33 VSYNC 8 DP_CRT_HSYNC_CON
CRT@ SC10U6D3V3MX-GP C5502 CRT@ HSYNC
1

LDO_EN 21 15 DP_CRT_R
LDO_EN RED_P 16
B CRT@ C5527 1 2 SCD1U16V2KX-3GP PCH_DPC_AUXP_U 26 RED_N B
<6> PCH_DPB_AUXP AUX_P
CRT@ C5528 1 2 SCD1U16V2KX-3GP PCH_DPC_AUXN_U 27 12 DP_CRT_G
<6> PCH_DPB_AUXN AUX_N GREEN_P 13
CRT@ C5529 1 2 SCD1U16V2KX-3GP PCH_DPC_P0_U 29 GREEN_N
+3VS VDD_DAC_33 <6,33> HDMI_CRT_P0 LANE0P
ShortPad <6,33> HDMI_CRT_N0 CRT@ C5526 1 2 SCD1U16V2KX-3GP PCH_DPC_N0_U 30 10 DP_CRT_B
LANE0N BLUE_P 11
R5503 CRT@ C5530 1 2 SCD1U16V2KX-3GP PCH_DPC_P1_U 31 BLUE_N
<6,33> HDMI_CRT_P1 LANE1P
0_0603_5% <6,33> HDMI_CRT_N1 CRT@ C5525 1 2 SCD1U16V2KX-3GP PCH_DPC_N1_U 32 22 POL1_SDA
1 @ 2 LANE1N POL1_SDA 23 POL2_SCL
POL2_SCL
CRT@ => @ CLK_DP2VGA 17
<8> CLK_DP2VGA XI/CKIN
2

Jason 6/25 C5521 18 14

SC10U6D3V3MX-GP XO GND_DAC
CRT@ RRX 28 33
RRX GND
1

RTD2168-CGT-GP
1

R5505
12KR2F-L-GP
2

+3VS

U5504 @

1 8
2 A0 VCC 7
3 A1 WP 6 POL2_SCL
4 A2 SCL 5 POL1_SDA
+3VS +3VS +3VS VSS SDA
2

CAT24C128WI-GT3-GP
R5509 R5515 R5502
4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
@ CRT@ CRT@
1

A POL1_SDA POL2_SCL LDO_EN A

2

R5508 R5516 R5512

4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
CRT@ @ @
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP to VGA Converter
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P 1.0(A00)

Date: Thursday, July 09, 2015 Sheet 34 of 64

5 4 3 2 1
Main Func = HDD
SATA HDD Connector
Jason 6/25
Short Pad
+5VS ShortPad 5V_HDD_S0
R5605
0_0402_5%
Jason 6/24
5V_HDD_S0 1
R5601 <10> HDD_DEVSLP HDD_DEVSLP 1 @ 2 HDD_DEVSLP_R AFTP5601 AFTE14P-GP
0_0805_5%
80 mils 1 @ 2
Reserve, refer to M15 EE Implementation Requirements HDD1
14
1

1
C5601 C5604 C5605 C5606 12
@ @ @ <10> SATA3_PTX_HDDRX_P0 SCD01U50V2KX-1GP 2 1 C5602 SATA_TXP0_R 11
SC10U10V5KX-2GP

SCD1U16V2KX-3GP

SC10U10V5KX-2GP

SCD1U16V2KX-3GP
<10> SATA3_PTX_HDDRX_N0 SCD01U50V2KX-1GP 2 1 C5603 SATA_TXN0_R 10
2

2
9
SCD01U50V2KX-1GP 1 2 C5616 SATA_RXN0_R 8
<10> SATA3_PRX_HDDTX_N0 SCD01U50V2KX-1GP 1 2 C5615 SATA_RXP0_R 7
<10> SATA3_PRX_HDDTX_P0 6
HDD_DEVSLP_R 5
4
5V_HDD_S0 3
2
Layout Note:
1
Place near HDD1 13
Close to HDD1
EU5602 ACES_51625-01201-001_12P-T
SATA_TXP0_R 1 1 10 9 SATA_TXP0_R CONN@

SATA_TXN0_R 2 2 9 8 SATA_TXN0_R

SATA_RXN0_R 4 4 7 7 SATA_RXN0_R

SATA_RXP0_R 5 5 6 6 SATA_RXP0_R

3 3

@ESD@
Swap based on the swap report.

Main Func = ODD

SATA Zero Power ODD
+3VS

R5607 2.5A
1 2 SATA_ODD_PWRGT X01_0729
ODD Connector +5VS
ZPODD@
100KR2J-1-GP 2
3
U5601

IN#2 OUT#6
6
7
ODD_PWR_5V
ODD_PWR_5V

+5VS
ODD
ODD_PWR_5V
IN#3 OUT#7 8
100 mil
OUT#8 R5603
C5609 4 C5610 ZPODD@ 1 2
EN/EN#

1
<9> SATA_ODD_PWRGT 1
@ 5 GND 9 0R5J-5-GP
SC10U10V5KX-2GP FLT# GND SC10U10V5KX-2GP

2
NOZPODD@
ODD_PWR_5V ZPODD@
ODD1 Current limit TPS2001CDGNR-GP
22
GND2 20
20
19
Active High
19 18 ZPODD@ typ =>2.5A 2nd = 74.02311.079
74.02001.079 is OBS
18
17
17
16
SATA_ODD_DA#_C 1 R5602 2 0R2J-2-GP SATA_ODD_DA# <10> Will use 74.06288.079
16 15 but 74.06288.079 is also OBS
15 14
14 13
we will use 074.06288.0079.
13 12
12 11
11 10
10 9
9 8 SATA_ODD_PRSNT#
8 SATA_ODD_PRSNT# <10>
7
7 6 SATA_RXP2_R C5608 1
ODD@ 2 SCD01U50V2KX-1GP
6 SATA_PRX_ODDTX_P1 <10>
1

5 SATA_RXN2_R C5607 1 2 SCD01U50V2KX-1GP SATA_PRX_ODDTX_N1 <10>

5 4 ODD@ R5604
4 3 SATA_TXN2_R C5611 1
ODD@ 2 SCD01U50V2KX-1GP @ 10KR2J-3-GP
3 SATA_PTX_ODDRX_N1 <10>
2 SATA_TXP2_R C5612 1 2 SCD01U50V2KX-1GP SATA_PTX_ODDRX_P1 <10>
2 1 ODD@
1
2

21
GND1
ACES_51519-02001-001
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 35 of 64
 5 4 3 2 1

Main Func = WLAN

USB2.0 90ohm
Main SM070003Z00(S COM FI_ INPAQ MCM1012B900F06BP)
+3VS Jason 6/25 +3.3V_WLAN 2nd SM070004U00(S COM FI_ MURATA DLM11SN900HY2L)
ShortPad 3rd SM070004400(S COM FI_ PANASONIC EXC24CQ900U)
R5809
1.1A 0_0805_5% R5801
1 @ 2 EMI@ 0R2J-2-GP
D USB_PN8_R 1 2 D
USB_PN8 <10>
C5801
SCD1U16V2KX-3GP

C5805

C5802
SCD1U16V2KX-3GP

C5806

C5804
SCD1U16V2KX-3GP

C5803
SCD1U16V2KX-3GP
1

1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
@ @ @ TR5801 @EMI@
4 3
2

2
1 2

MCM1012B900F06BP_4P

R5802
WLAN1 EMI@ 0R2J-2-GP
USB_PP8_R 1 2
68 69 USB_PP8 <10>
MTG76 MTG77
+3.3V_WLAN
67
66 GND 65
64 3.3VAUX RESERVED 63
62 3.3VAUX RESERVED 61
60 RESERVED GND 59
58 RESERVED RSRVD/PERN1 57
56 RESERVED RSRVD/PERP1 55
54 RESERVED GND 53
52 ALERT RSRVD/PETN1 51
Short Pad
TP5803 1 TPAD14-OP-GP E51_RX2 50 I2C_CLK RSRVD/PETP1 49 R5803 Jason 6/24
C D5503 1 2 RB551V-30_SOD323-2 WLAN_DISABLE#1 48 I2C_DATA GND 47 0_0402_5% C
<6> WLAN_RADIO_DIS# W_DISABLE1# PEWAKE0#
<9> BLUETOOTH_EN Short Pad R5804 1 @ 2 0_0402_5% BLUETOOTH_EN_NGFF 46 45 CLK_PCIE_WLAN_REQ#_R 1 @ 2
W_DISABLE2# CLKEQ0# CLK_PCIE_WLAN_REQ# <11>
Short Pad R5805 1 @
R5807 1 2 0_0402_5% PLT_RST_NGFF# 44 43
<11,25,29,32,56> PCH_PLTRST#_EC PERST0# GND
Short Pad @ 2 0_0402_5% SUSCLK_R 42 41 CLK_PCIE_WLAN_N1 <11>
<11> SUSCLK SUSCLK REFCLKN0
Jason 6/24 40 39 CLK_PCIE_WLAN_P1 <11>
1 E51_RX1 38 COEX1 REFCLKP0 37
TP5802 TPAD14-OP-GP E51_TX1 36 COEX2 GND 35 PCIE_PRX_WLANTX_N5_R R5808 1 2 0R2J-2-GP
34 COEX3 PERN0 33 PCIE_PRX_WLANTX_N5 <10>
PCIE_PRX_WLANTX_P5_R R5811 1 2 0R2J-2-GP
RESERVED PERP0 PCIE_PRX_WLANTX_P5 <10>
32 31
1 30 RESERVED GND 29 2 1 CV310 .1U_0402_16V7K
TP5804 TPAD14-OP-GP
E51_TX2
RESERVED PETN0
PCIE_PTX_WLANRX_N5 PCIE_PTX_WLANRX_N5_C <10> EMI request
28 27 PCIE_PTX_WLANRX_P5 2 1 CV311 .1U_0402_16V7K PCIE_PTX_WLANRX_P5_C <10>
26 UART_RTS PETP0 25
24 UART_CTS GND

CLK_PCIE_WLAN_N1

CLK_PCIE_WLAN_P1
UART_TX

23
22 SDIO_RESET# 21
20 UART_RX SDIO_WAKE# 19
Reserved for NGFF Debug Card 18
16
UART_WAKE#
GND
SDO_DAT3
SDO_DAT2
17
15
14 LED2# SDO_DAT1 13
+3VALW +3.3V_WLAN 12 PCM_OUT SDO_DAT0 11
10 PCM_IN SDIO_CMD 9

EC5801
SC33P50V2JN-3GP

EC5802
SC33P50V2JN-3GP
PCM_SYNC SIDO_CLK

1
R5810 +3.3V_WLAN 8 7
1 @ 2 6 PCM_CLK GND 5 USB_PN8_R @ @
0R2J-2-GP 4 LED1# USB_D- 3 USB_PP8_R
3.3VAUX USB_D+

2
R5806 2 1
1 @ 2 E51_TX1 3.3VAUX GND
B <29> HOST_DEBUG_TX B
0R2J-2-GP DAN05-67406-0100
CONN@
1 @ 2 E51_TX2
1

R5812
0_0402_5%
Jason 6/24 @ R6517
Short Pad 100KR2J-1-GP
2

Support: Intel Dual Band Wireless-AC 3160

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF_WLAN CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 36 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = Power BTN

Power button

1
G6102 G6102 G6101 G6101
Always Open GAP-OPEN
JP@
GAP-OPEN
JP@
Always Open
& Not Solder & Not Solder

2
D PWR1 D
R6109 100R2J-2-GP 4 6
1 2 LID_CLOSE#_C 3 4 G2 5
<29,32> LID_CLOSE# 1 2 KBC_PWRBTN#_C 2 3 G1
<29> POWER_SW#_MB R6102 100R2J-2-GP 1 2
+3VALW 1

1
ED6101 JXT_FP202DH-004M10M

1
AFTP6101 1 CONN@
@ EC6101 AZ5725-01F_DFN2
@ESD@

SC1KP50V2KX-1GP
2

2
For EMI Reserved
EC6105 1 2 SCD1U16V2KX-3GP
EC6101 must be used 1000pF. LID_CLOSE#_C

Main Func = Battery LED

C C

Low actived from KBC GPIO

Battery LED1(AMBER_LED)
+3VALW +5VALW
LED1
R6103 470R2J-2-GP
2 1 1
BAT_AMBER

3
Need CIS Symbol
Q6101
2

3 2 1 390R2J-3-GP 2
2R
R6107 BAT_WHITE
<29> BAT1_LED#
1 6CHG_AMBER_LED_R# 2
1
1R
AMBER_LED_BAT

1
QC4A 12-22A/Y2T7D-C30/2C YELLOW/WHITE
DMN66D0LDW-7_SOT363-6 EC6102 @ @ EC6103
DDTA144VCA-7-F-GP SC220P50V2KX-3GP SC220P50V2KX-3GP

2
Q6102
Battery LED2 (WHITE_LED)
5

3
2R

<29> BAT2_LED# 4 3 BATT_WHITE_LED_R# 2

1
1R
WHITE_LED_BAT
QC4B
DMN66D0LDW-7_SOT363-6
DDTA144VCA-7-F-GP
B B

Main Func = HDD LED <29> SATA_LED#_R

For EMI Reserved

2
G
SATA_LED EC6104 1 2 SCD1U16V2KX-3GP
+3VS 3 1 BATT_WHITE_LED_R#
<10,29,37> SATA_LED#

D
@

Q6105
Q6103 +5VS +3VS 2N7002K_SOT23-3
2

LED@ 2N7002K_SOT23-3
Q6104 R6110
G

LED@ HDLED1
3 1 2
2R
SATA_LED#_R
3

<10,29,37> SATA_LED# 3 1 SATA_LED#_B 2 R6108

1 1 2 2 1
1R
SATA_LED SATA_LED_R
S

LED@ 10KR2J-3-GP
A A
LED@ LED-W-27-GP-U
DDTA144VCA-7-F-GP 330R2J-3-GP
2nd = 83.00110.R70
3rd = 083.11204.0070
Security Classification Compal Secret Data Compal Electronics, Inc.
SATA HDD LED Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

LOW actived from PCH GPIO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED Bard/Power Button
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 37 of 64
5 4 3 2 1
 5 4 3 2 1

Main Func = KB Main Func = TPAD Check leakage

Jason 2015/03/06 +3VALW +3VS TP_VDD

Keyboard Backlight (Reserved) 2015/5/19 Modify NOTP_WAKE@

1
TP_VDD +3VS Jason TP_WAKE@ R6212 1 2
KB Backlight Power Consumption: 285mA max. R6215 0R3J-0-U-GP
KB1 0R2J-2-GP
30 32 +5VS +5V_KB_BL
<9> KB_DET# 29 30 GND 31

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
KSI7
29 GND

2
KSI6 28 2 1
27 28

RZ18

RZ19

RZ20

RZ21
KSI4 F6201
<29> KSI[0..7] 27

1
KSI2 26 0.5A_13.2V_NANOSMDC050F-13.2-2 KBBL@ TP_VDD Discharge
KSI5 25 26 KBBL@ C6202
KSI1 24 25 Q6203 TP_VDD
<29> KSO[0..16] 24

2
KSI3 23 SCD1U16V2KX-3GP NTK3139PT1G_SOT723-3
KSI0 22 23 DAT_TP_SIO
21 22 <29> DAT_TP_SIO 3 1 1 2
EC/PS2
KSO5 KB_BL1

D
KSO4 20 21 KBBL@ CLK_TP_SIO TP_WAKE@ R6211
20 <29> CLK_TP_SIO

1
KSO7 19 R6206 1 SCD1U16V2KX-3GP TP_WAKE@ 100R3J-4-GP
KSO6 18 19 1 2 KB_LED_DET_C 2 1 I2C_SDA_TP C6204

G
D D
18 <12> KB_LED_BL_DET 2 <9> I2C_SDA_TP

1
17 3 5
PCH/I2C
KSO8 51KR2J-1-GP
17 3 G1

2
KSO3 16 4 6 I2C_SCL_TP D Q2405
KSO1 15 16 4 G2 <9> I2C_SCL_TP 1 2 TP_ON#_GATE 2

KB_BL_CTRL#
15 <29> TP_PW_EN# 2N7002K_SOT23-3
14

@ESD@ CZ30

@ESD@ CZ31
KSO2 R6207 ACES_50524-00401-P01 G
13 14

10P_0402_50V8J

10P_0402_50V8J
KSO0 100KR2J-1-GP CONN@ R6214 S
KSO12 12 13 KBBL@ 20KR2F-L-GP
12

3
KSO16 11
KSO15 10 11
KSO13 9 10
9

2
KSO14 8
8

1
KSO9 7 D Q6202
KSO11 6 7 2 KBBL@
KSO10 5 6 <29> KB_LED_PWM
G
CAP_LED 4 5
S
4

3
3 LN2306LT1G_SOT23-3 TP_VDD TP_VDD
2 3
2
EMI depop location
1
1

2
ACES_51510-0304N-P01 R6203
CONN@ 10KR2J-3-GP
2015/5/19 Modify

2
Jason

1
TP_VDD 1 3
For EMI Reserved Check leakage
Change to PU TP_VDD (DVT1)
<12,29> TOUCHPAD_INTR#
INT_TP#

S
Jason 2015/03/06
KB_BL_CTRL# EC6207 1 2 SCD1U16V2KX-3GP
+3VS Q6204
@ LN2306LT1G_SOT23-3

1
+5V_KB_BL EC6208 1 2 SCD1U16V2KX-3GP
R6506
+3VS @ 2.2K_0402_5% TP_VDD

2 1

2
Q6501 SCD1U16V2KX-3GP C6201
I2C_SCL_TP 1 6 I2C_SCL_TP_Q
1

TP_VDD 4K7R2J-2-GP 2 1 R6209 TPAD1

1
2 5 NOTP_WAKE@ 1
1 2 2 1
CAP LED Control
R6202 2nd = 84.2N702.E3F T8 R6508 I2C_SDA_TP_Q
100KR2J-1-GP 3 4 I2C_SCL_TP_Q 3 2
3rd = 75.00601.07C 2.2K_0402_5% R6505 100KR2J-1-GP
3
+5VS 4
C
LOW actived from KBC GPIO Q6201 4th = 84.DMN66.03F 4
C
2

5
G

DMN66D0LDW-7_SOT363-6 D3801 INT_TP#

5

2
3 1 2 6 9
2R
I2C_SDA_TP_Q PTP_DIS# TP_LOCK#
<29> PTP_DIS# 6 G1
3 1 CAP_LED_R# 2 R6201 I2C_SDA_TP DAT_TP_SIO 7 10
<29> CAP_LED# 1R
1 CAP_LED_Q 1 2 CAP_LED RB551V-30_SOD323-2 CLK_TP_SIO 8 7 G2
S

8
1KR2J-1-GP 1 JXT_FP202DH-008M10M
Q6206 DDTA144VCA-7-F-GP
CONN@
LN2306LT1G_SOT23-3
AFTP6235

Main Func = Thermal

Fan controller1
+5VS
+3VS
@ R2605 FAN261

2.2U_0603_6.3V6K
0R2J-2-GP
1 2 FON# 1 8

C2611
FON# GND

SCD1U16V2KX-3GP
+3VS 1 2 7
+5VS VIN GND

1
FAN_VCC1 3 6

C2605
VOUT GND

1
4 5
<29> FAN1_DAC_1 VSET GND
RE32

2
2.2K_0402_5% 2

Q2601 APL5606AKI-TRG SOP 8P FAN CONTROL

2
DMN66D0LDW-7_SOT363-6
6 1 THM_SML1_DATA
<8,29,57> GPU_THM_SMBDAT Layout Note: FAN1

1
5 2 Need 10 mil trace width. Jason 6/24
2nd = 84.2N702.E3F 5
4
T8 3
RE432 Short Pad 4 GND2
3rd = 75.00601.07C 2.2K_0402_5%
GND1
4th = 84.DMN66.03F R2606
0_0402_5% 3
3

2
THM_SML1_CLK FAN1_TACH 1 @ 2 FAN1_TACH_C 2
+3VS <29> FAN1_TACH 2
FAN_VCC1 1
<8,29,57> GPU_THM_SMBCLK FAN_VCC1 1
B ACES_50224-0030N-001 B

SC2200P50V2KX-2GP
1
SCD1U16V2KX-3GP

RB551V30-GP
SC10P50V2JN-4GP
1 CONN@
SC10U6D3V3MX-GP

1
D2601 @

@
1

1
C2601 @

@
C2604
T8C2602
Layout Note: 2.2U_0603_6.3V6K

C2603
2

2
2
Main: Signal Routing Guideline:

EC2602

EC2601
SCD1U16V2KX-3GP
2

2
SA000067P00, S IC NCT7718W MSOP 8P THEMAL SENSOR Trace width = 15mil
2nd:
SA00007WP00, S IC F75397M MSOP 8P THEMAL SENSOR
Jason 2015/03/03
NCT7718_DXP
LMBT3904LT1G-GP

Q2603 THM26
1

@ 1 8 THM_SML1_CLK
2 2 VDD SCL 7 THM_SML1_DATA
T8 C2606 T8 C2607
SC2200P50V2KX-2GP 3 D+ SDA 6 ALERT#
SC470P50V3JN-2GP
D- T8 ALERT#
2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

T_CRIT# 4 5
T_CRIT# GND
3

NCT7718_DXN
C2608 @

C2609 @

DIMM CPU NCT7718W-GP

2

Close to KBC
Address: X100_1100(4C), 1001_100X(98)
Layout Note: Close to Thermal sensor VD_IN1 for system thermal sensor
Layout Note: C2607 close THM26
+3VLP +3VALW
DXN and DXP routing width and spacing is 10 mil / 10 mil.

1
24K9R2F-L-GP
R2609 @
R2608
10K_0402_1%
+3VS

2
1 2 18K7R2F-GP ALERT#
R2603 T8
1 2 2KR2F-3-GP T_CRIT# VCIN0_PH <29>
R2604 T8

1
C2612 PURE_KBCT8

1
R2610 SCD1U16V2KX-3GP
A A
NTC-100K-8-GP PURE_KBCT8 C2613 Short Pad
PURE_KBCT8 SC100P50V2JN-3GP

2
R2611 Jason 6/24

2
0_0402_5%
VD_IN1_C 1 @ 2

PURE_KBCT8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Keyboard/Touch Pad/Thermal
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P 1.0(A00)

Date: Thursday, July 09, 2015 Sheet 38 of 64

5 4 3 2 1
 5 4 3 2 1

Main Func = IO Connector

I/O Board Connector

X01_0808

D D
CN6301
24 26
23 24 GND 25
USB_PN2_C 22 23 GND
<30> USB_PN2_C 22
<30> USB_PP2_C USB_PP2_C 21
20 21

USB2 (USB2.0) <30> USB_PP3_C

<30> USB_PN3_C
USB_PP3_C
USB_PN3_C
19
18
20
19
18
17
USB3 (USB2.0) R6301
1
@
2 GND_R1
0R2J-2-GP USB20_VCCA
16
15
17
16
15
14
13 14

USB2 (USB2.0) X01_0731 12 13

12
R6302 0R2J-2-GP 11
USB3 (USB2.0) 1 @
AUD_AGND
2 GND_R2 10
9
11
10
9
AUD_PORTA_L_R_B 8
<24> AUD_PORTA_L_R_B AUD_PORTA_R_R_B 7 8
<24> AUD_PORTA_R_R_B SLEEVE_R 6 7
<24> SLEEVE_R 6
5
Universal Jack <24> RING2_R RING2_R 4
3
5
4
3
<24> JACK_PLUG JACK_PLUG 2
1 2
AUD_AGND 1
ACES_51524-0240N-001
CONN@
C C

1
R6305
@ 2
Pitch: 1mm
Power: 5 pins
0R3J-0-U-GP
GND: 4 pins
AUD_AGND
AGND: 2 Pins

RING2_R 1
AFTP6305 AFTE14P-GP
AUD_PORTA_L_R_B 1
1 AFTP6306 AFTE14P-GP
JACK_PLUG
AFTP6307 AFTE14P-GP
AUD_PORTA_R_R_B 1
1 AFTP6309 AFTE14P-GP
SLEEVE_R
B AFTP6310 AFTE14P-GP B
USB20_VCCA 1
AFTP6311 AFTE14P-GP

AUD_AGND 1
AFTP6313 AFTE14P-GP

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO Board Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 39 of 64
5 4 3 2 1
 5 4 3 2 1

+5V_RUN/+3.3V_RUN for System +3VALW_PCH for System +3VALW +3VALW_PCH

PJP@
PJP23
+5VS 1 2 PJP23 Short
1 2
JUMP_43X79
for NON-DS3

1
+3VALW
PJP21 PJP@ PJP21
D
+5VALW
PAD-OPEN1x3m Always Short For NON-DS3 D

UZ2

2
1 14 +5V_RUN_UZ2 1 2

SC1U10V2KX-1GP
DSX@
VIN1 VOUT1

1
2 13 @ CZ44 0.1U_0402_10V7K +3VALW_PCH
VIN1 VOUT1 CZ36
3 12 1 2
<11,17,29,41,46,51> SIO_SLP_S3# ON1 CT1

2
CZ45 470P_0402_50V7K UZ3 DSX@ PJP@
4 11 PJP22
VBIAS GND 1 8 1 2
5 10 1 2 2 GND OUT#8 7
ON2 CT2 CZ23 3 IN#2 OUT#7 6
6 9 470P_0402_50V7K PJP13 PJP@ 1 DSX@ 2 +3VALW_PCH_ON4 IN#3 OUT#6 5 PAD-OPEN1x3m
+3VALW VIN2 VOUT2 <29> PCH_ALW_ON EN OC#
7 8 +3.3V_LAN_UZ2 1 2 CZ37
VIN2 VOUT2 +3VS PJP13

1
R3802 For DS3
15 Always Short

SC1U10V2KX-1GP
1 PAD-OPEN1x3m 0R2J-2-GP SY6288C10CAC-GP
GPAD
PJP22 Short

2
EM5209VF_SON14_2X3 @ CZ50

2
0.1U_0402_10V7K
RdsON: 100m ohm for DS3

C C

+3V/+0.95V/+1.8V/+1.35V for GPU

+1.35V_MEM
2000mA +1.35V_MEM_GFX
U5602 DIS@ J13 PJP@
1 14 +1.35V_MEM_GFX_OUT 1 2 J13
VIN1 VOUT1 1 2
C6210 1 @ 2 1U_0402_6.3V6K 2
VIN1 VOUT1
13
C6208 DIS@ JUMP_43X118
2
@
Always Short
R6509 1 DIS@ 2 1K_0402_5% +1.35V_MEM_GFX_ON 3 12 2 1 330P_0402_50V7K C6207
<12,29,52> DGPU_PWROK ON1 CT1 .1U_0402_16V7K
C6212 1DIS@ 2 0.1U_0402_16V7K 4 11 1
+5VALW VBIAS GND
DGPU_PWR_EN RZ79 1 DIS@ 2 0_0402_5% +3VGS_GPU_ON 5 10 2 1 C6209 DIS@
<9,52> DGPU_PWR_EN ON2 CT2 330P_0402_50V7K J12 PJP@
C6211 1 @ 2 0.1U_0402_16V7K 6 9 +3VGS_OUT 1 2
7 VIN2 VOUT2 8 1 2 +3VGS J12
VIN2 VOUT2
15
JUMP_43X118 Always Short
EM5209VF_SON14_2X3
GPAD
1500mA
+3VS

B B
2300mA
U15 DIS@ J11 PJP@
1 14 +0.95VSDGPU_OUT 1 2
+1.0V_PRIM
2 VIN1 VOUT1 13 1 2 +0.95VSDGPU J11
VIN1 VOUT1
DGPU_PWR_EN R6510 1 DIS@ 2 1K_0402_5% +0.95VSDGPU_ON 3 12 2
C343 DIS@
1 330P_0402_50V7K
JUMP_43X118 Always Short
ON1 CT1
C983 1DIS@ 2 0.1U_0402_16V7K +5VALW
4 11
VBIAS GND
R437 1 DIS@ 2 1K_0402_5% +1.8VGS_GPU_ON 5 10 2 1 C349 DIS@ +1.8VGS
ON2 CT2 330P_0402_50V7K J10 PJP@
C987 1DIS@ 2 0.1U_0402_16V7K +1.8V_PRIM
6 9 +1.8VGS_OUT 1 2 J10
VIN2 VOUT2
1 2 7
VIN2 VOUT2
8 2
@
Always Short
C24 @ 15 PAD-OPEN1x2m C26
1U_0402_6.3V6K GPAD .1U_0402_16V7K
EM5209VF_SON14_2X3 500mA 1

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power control
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P
Date: Thursday, July 09, 2015 Sheet 40 of 64
5 4 3 2 1
 A B C D

@ PJP1
2 1
2 1
JUMP_43X79

EMI@ PL1
+19V_VIN PR4 PSID@
FBMJ4516HS720NT_2P 33_0402_5%
@ PJPDC1 +19V_ADPIN 1 2 1 3 PSID-3 1 2 PS_ID <29>

S
8 PQ6 PSID@
GND 7 FDV301N_G 1N SOT23-3
GND

1000P_0402_50V7K

1000P_0402_50V7K

G
2

1
6

100K_0402_1%
0.1U_0402_25V7K

0.1U_0402_25V7K
6 PR8

2
5 PSID@ PR3 PSID@
5 4 PSID-2 2 1

PC1

PC2

PC3

PC4

PR6
2.2K_0402_5%

PSID@
4 +5VALW

3
3
3

2
2 @ PD4
2 10K_0402_1%

2
1 1 2

EMI@

EMI@

EMI@

EMI@
TVNST52302AB0_SOT523-3 +3VALW
1

1
1 EMI@ PL4 C 1

FBMJ4516HS720NT_2P PSID-1 2
ACES_50458-00601-001 B

15K_0402_1%
1

2
@ PJP2 E

MMST3904-7-F_SOT323
3
2 1 @ PR11 3

PR9
PSID@

PSID@
2 1 +5VALW
1 2 1
JUMP_43X79 PL2 2
BLM15AG102SN1D_2P
100K_0402_1%

1
PSID 2 1 @ PD5

PQ5
EMI@
BAV99W_SC70-3

1
@ PD6
BAV99W_SC70-3
+17.4V_BATT+ @ PJP3
2 1 +17.4V_BATT++
2 1
+17.4V_BATT+

3
JUMP_43X79

EMI@ PL3
FBMJ4516HS720NT_2P
1 2 +17.4V_BATT++
+5VALW
1

1000P_0402_50V7K
0.01U_0402_25V7K
1

PC8

1
PC7

PD2 PD3
2

TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
ESD@ ESD@
EMI@

EMI@

3
SMART
Battery: PBAT_PRES# <29,42>
01.GND @ PBATT1
2 02.GND 1
1
PR16
2
2
03.SYS_PRES 2 3 SYS_PRES PR20
PR15
200_0402_5% 10K_0402_1%
04.BATT_PRS 3 4 100_0402_5% 1 2 1 2
05.DAT_SMB 4 5 DAT_SMB 1 2 +3VALW
5
06.CLK_SMB 6
6
7
CLK_SMB 1 2
07.BATT1+ 7 8 PR18
08.BATT2+ 8 9 100_0402_5%
GND 10
GND PBAT_CHG_SMBCLK <29,42>
SUYIN_200277GR008M270ZR

PBAT_CHG_SMBDAT <29,42>

Other component (37.1)

3 3

Adapter protection: Battery protection: Erp lot6 Circuit +19V_VIN

if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is
then trigger the H_PROCHOT#, unplugged, keep low for 10ms

3.3K_1206_5%
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC

1
be removed by end user <11,17,29,40,46,51> SIO_SLP_S3#

PR5
H_PROCHOT#
<12,29,42,48> H_PROCHOT# +19V_VIN +3VALW PR7
2
10K_0402_1%

3 2
1

1M_0402_1%
+3VALW
PR28

PR31 PC16
10K_0402_1%

L2N7002DW1T1G_SC88-6
1

.1U_0402_16V7K PQ1B
L2N7002DW1T1G_SC88-6

1M_0402_1% 5
PQ2A
PR37

3 2
3

PC14 1 2 2
6

.1U_0402_16V7K
L2N7002DW1T1G_SC88-6

L2N7002DW1T1G_SC88-6

@
PQ3B

PQ2B

100K_0402_1%
L2N7002DW1T1G_SC88-6
2

1
1

PBAT_PRES# 1 2 5 PR10
PQ1A

5 2
PR29

PR33 1M_0402_1%
10K_0402_1%
100K_0402_1%

1
1

1
4

1M_0402_1%
PR32

PR2
2

4 4
2

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_DCIN/BATT CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 41 of 64
A B C D
 A B C D

2 1 2 1

@ PR739 @ PR746 Iada=0~3.33A(65W)

1M_0402_1% 1M_0402_1%
Iada=0~2.30A(45W)

5
2 1 3 4 ADP_I = 32*Iadapter*Rsense
@ PR744 @
PQ709B
1M_0402_1%
L2N7002DW1T1G_SC88-6

@
PD706
1 1

ACIN_CHG 2 1 +19VB

PQ709A

L2N7002DW1T1G_SC88-6
SDMK0340L-7-F_SOD323-2
2

1
2 1 2 1

PR738 PR737
1M_0402_1% 3M_0402_5% PQ718
PR703
PQ740 MDU1512RH_POWERDFN56-8-5 0.01_1206_1%
AON7426_DFN3X3EP8-5 @EMI@ PL704
1 1 1 4 1 2
2 2
5 3 3 5 2 3 1UH_PCMB053T-1R0MS_7A_20%

2200P_0402_25V7K
+19V_VIN

0.1U_0402_25V7K
EMI@

EMI@
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
5600P_0402_25V7K

2
@ PJP701

PC764
1 4

4
2

1
1 2

0_0402_5%

PC744

PC760

PC762

PC763
3.3K_1206_5%

1 2

0_0402_5%

0_0402_5%
@ PR778

PC765

PC705
1
1

1
JUMP_43X118
PC742

PR772

PR740
1

2
@
PR720

@
2

2
@
PQ707A

L2N7002DW1T1G_SC88-6

@ PC747
0.1U_0402_25V6
2 2 1
<29,42> AC_DIS

0.1U_0402_25V6

0.1U_0402_25V6
1

2
4.02K_0402_1%

4.02K_0402_1%
2 2

For DT Mode

PC745

PC746
1

1
1

1
@ @

MDU1512RH_POWERDFN56-8-5
PR745
100_0402_1%
392K_0402_1%

2
1

5
PR762

PR763
1 2 +17.4V_BATT+
PR729

0.22U_0603_25V7K
@ PR773
0_0603_5%
2

1 2 4
0.01UF_0402_25V7K
1
49.9K_0402_1%

D
1

1
PR732

0.1U_0402_25V7K

3
2
1
2
PC711

PC750
<29,42> AC_DIS

2
CMSRC

PQ717
PC779
G
1

2
@ PQ720 S
VDD_CHG
3

ASGATE

1
L2N7002WT1G_SC70-3

5
@

AON7408L_DFN8-5
100K_0402_1%

32

31

30

29

28

27

26

25
1

PU703 ISL95521HRZ-T_QFN32_4X4
For Learn Mode 4S1P: CV = 17.7V CC: 1.6A

PQ704
PR741

VBAT
CSIP

ASGATE

QPCP

BGATE
CSIN

CMSRC

OPCN
@ PR771 PC721 4
0_0603_5% 0.22U_0603_25V7K
ACIN_CHG 1 24 1 2 1 2
ACIN BOOT
2

PR765
PL700
ACIN 2 23 UGATE_CHG 1 2 0.01_1206_1%
<11,29> ACAV_IN ACOK UGATE
+17.4V_BATT+

3
2
1
@ PR769 0_0402_5% @ PR761 4.7UH_5.5A_20%_7X7X3_M
1

1 2 3 22 PHASE_CHG 0_0603_5% 1 2 1 4
158K_0402_1%

<29,41> PBAT_CHG_SMBDAT SDA PHASE

PR731

1 2 @ PR770 4 21 LGATE_CHG 2 3

680P_0603_50V7K 4.7_1206_5%
<29,41> PBAT_CHG_SMBCLK SCL LGATE

1
0_0402_5%

@EMI@ PR766

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7K
5
3
@ PR777 1 2 5 20 VDDP_CHG 3

AON7506_DFN33-8-5
PROCHOT# VDOP
2

<12,29,41,48> H_PROCHOT# 0_0402_5% @ PR774 0_0402_5%

1
1 2 6 19 VDD_CHG 1 2

PC775

PC776

PC777

PC761

PC766
<29> I_ADP @ PR775 AMON VDO

2
1 2 7 18 PR760 4.7_0402_5%

PQ708
<29> I_BATT BMON DCIN

2
4

1U_0402_16V6K

1U_0402_16V6K
2

2
8 17

BATGONE
0_0402_5%
<29,48> I_SYS PSYS NTC

@EMI@ PC767
100K_0402_1%
CCLIM
COMP

ACLIM
PROG
AGND

CSON

CSOP
FSET

PC768

PC769
2200P_0402_25V7K

2200P_0402_25V7K

1
2
10.5K_0402_1%

3
2
1

2
1

PR757
1

2
PC748

PC749

PR727

33

10

11

12

13

14

15

16

3
PQ710
2

2
LMUN5113T1G_SOT323-3

0_0603_5%
2

PR780
1 2

1U_0603_25V6
+19V_VIN

2
VDD_CHG PR743 10_1206_5%

1
1 2 PD704 SDMK0340L-7-F_SOD323-2 @

0_0402_5%

1
2
PC757
PR779 1 2 BA

1
200K_0402_1%

200K_0402_1%

1
PD705 SDMK0340L-7-F_SOD323-2 <11> SIO_SLP_S5# 2
@

CCLIM
2

1 2
PR749

PR750

PQ711
ACIN

BA
ACLIM @ PC758 0.1U_0402_25V6
10K_0402_1%

3
PROG 1 2 LTC015EUBFS8TL_UMT3F
1

COMP PR742 2_0402_5%

2
@ PR722 PC708
5

3.3K_1206_5% 0.1U_0402_25V6
499_0402_1%
150K_0402_1%

133K_0402_1%
2

@ PR776

1
4 3 2 1 0_0402_5%
PR764
560P_0402_50V7K

1
2

1 2
PR753

PR754

PR755
2

@
75K_0402_1%

66.5K_0402_1%

PQ707B @ PR756
PC751

4 L2N7002DW1T1G_SC88-6 10K_0402_1% 1 2 4
1
2

1 2
PR751

PR752

+3VALW
0.015U_0402_25V7K
1

@ PC759 0.1U_0402_25V6
2

10P_0402_50V8J
PC752

PC753
1

PBAT_PRES# <29,41>
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 42 of 64
A B C D
 A B C D E

1 1

@EMI@ PL102
FBMJ4516HS720NT_2P PR102
1 2 499K_0402_1%
ENLDO_3V5V 1 2
@ PR100 +19VB
@ PJP105 0_0603_5% PC102

1
1 2 3V_VIN BST_3V 1 2 1 2
+19VB

499K_0402_1%
1 2

PR103
JUMP_43X79 0.1U_0603_25V7K

2200P_0402_50V7K

1
PU100

2
PC100

PC103
0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K

BS
IN

IN

IN

IN
1

1
LX_3V 6 20 PL100

PC105

@ PC104
LX LX 1.5UH_PCMC063T-1R5MN_9A_20%

2
7 19 LX_3V 1 2

EMI@
@EMI@
GND LX +3VALWP
8 SY8286BRAC_QFN20_3X3 18

@EMI@ PR106
GND GND

4.7_1206_5%
9 17

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PG LDO +3VLP

1
Update PH401 change

PC106

PC107

PC108

PC109

@ PC110
10 16
NC NC to Common Part
SH000016800 20141202 3VALWP

2
OUT
EN2

EN1

1
21

NC
FF
GND PC111 TDC 7.087 A

1 3V_SN 2
PR107 4.7U_0603_6.3V6M
Peak Current 8.504 A

11

12

13

14

15

2
10K_0402_1%

680P_0603_50V7K
1 2 3.3V LDO 150mA~300mA

@EMI@ PC112
+3VALWP OCP Current 9 A fix by IC
2 2
Vout is 3.234V~3.366V

ENLDO_3V5V
POK <11,45,46,47>

2
POK

@ PJP102
PC113 PR108 +3VALWP 1 2 +3VALW

150K_0402_1%
1 2

1
1000P_0402_25V8J 1K_0402_5%

@ PR109
EN_3V 3V_FB 1 2 1 2 JUMP_43X118

@EMI@ PL103

2
FBMJ4516HS720NT_2P
1 2

1
@ PJP103

150K_0402_1%
@ PR111 +5VALWP 1 2 +5VALW

@ PR110
@ PJP106 0_0603_5% PC114 1 2
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
+19VB 1 2

2
JUMP_43X79 0.1U_0603_25V7K
2200P_0402_50V7K

1
PU102
PC115

PC116
0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

BS
IN

IN

IN

IN
PC117

PC118

LX_5V 6 20 PL101
LX LX
2

2.2UH +-20% 7.8A 7X7X3 MOLDING

EMI@
@EMI@

7 19 LX_5V 1 2 +5VALWP
GND LX
8 SY8286CRAC_QFN20_3X3 18
GND GND

1
3 PC119 3

PR112

680P_0603_50V7K 4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
9 17 1 2

@EMI@

PC120

PC121

PC122

PC123

@ PC124
PG VCC
Update PH401 change
10 16
NC NC 4.7U_0603_6.3V6M to Common Part

2
1 5V_SN
SH000016800 20141202
OUT

2
LDO
EN2

EN1

@ PR121 0_0402_5% 21
FF

EN_3V 1 2 GND
11

12

13

14

15

@ PR113

PC125
@ PR120 0_0402_5% +3VALWP 10K_0402_1% VL

@EMI@

2
EN_5V 1 2 1 2
5V LDO 150mA~300mA
ENLDO_3V5V

POK
EN_5V

PC126
4.7U_0603_6.3V6M

PR114
2.2K_0402_5%
5VALWP
2

1 2

150K_0402_1%
<29> ALWON
TDC 4.5 A

1
@ PR115
PD102
@ PR116 0_0402_5% SDMK0340L-7-F_SOD323-2 Peak Current 6.3 A
<29> CMP_VOUT0
1 2 1 2 OCP Current 9 A fix by IC

2
4.7U_0402_6.3V6M
1

1
PC127 PR117
PC128

150K_0402_1%
EN_3V 1000P_0402_25V8J 1K_0402_5%

@ PR118
5V_FB 1 2 1 2
2

EN_5V

2
EN1 and EN2 dont't floating
4 4
3

@ESD@

PD101
DELL CONFIDENTIAL/PROPRIETARY
TVNST52302AB0_SOT523-3
1

Compal Electronics, Inc.

Title

Place PD101 close to PU100 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 43 of 64
A B C D E
 5 4 3 2 1

@ PR200

BST_1.35V_R 1
0_0603_5%
2 BST_1.35V
0.675Volt +/- 5%
+1.35VP TDC 0.7A
Peak Current 1A

1
PC200
D 0.1U_0603_25V7K D

2
@ PJP206
+19VB 2 1 +19VB_1.35V UG_1.35V
2 1 +0.675VSP
JUMP_43X79

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
LX_1.35V

10U_0805_6.3V6K

10U_0805_6.3V6K
EMI@ PC208

EMI@ PC201

PC206

PC212

1
PC205

PC211
2

16

17

18

19

20
PU200

2
VLDOIN
PHASE

UGATE

BOOT

VTT
21
PAD
LG_1.35V 15 1
LGATE VTTGND

14 2
PGND VTTSNS

1
PR205
PQ201 10.2K_0402_1%

D1

D1

D1

G1
AON7934_DFN3X3A8-10 1 2 CS_1.35V 13 3
+1.35V_MEM PC204 CS RT8207PGQW_WQFN20_3X3 GND
TDC 6 A 10
D1 D2/S1
9 1U_0603_10V6K
1 2 12 4 VTTREF_1.35V
Peak Current 9 A PR206 VDDP VTTREF
OCP Current 11 A 5.1_0603_5%

G2
S2

S2

S2
1 2 VDD_1.35V 11 5
VDD VDDQ +1.35VP

1
PGOOD
5

1
PC210
+5VALW

TON
1
C PR210 0.033U_0402_16V7K C

FB
S5

S3

2
PC209 2.2_0603_5%
1U_0603_10V6K @ PC214

10

6
220P_0402_25V8J

2
1 2
+5VALW

FB_1.35V
TON_1.35V

EN_0.675VSP
EN_1.35V
PR207
54.9K_0402_1%
<11> 1.35V_VTT_PWRGD 1 2 +1.35VP
PR208
@ PR209 +19VB_1.35V 1 2
10K_0402_1%
453K_0402_1%

1
1 2
+3VALW

1
@ PC213
For RT8207P PR204
.1U_0402_16V7K
@ PR201 0_0402_5% 68.1K_0402_1%

2
1 2
<11,17,29> SIO_SLP_S4#

2
PL200
1UH_11A_20%_7X7X3_M
+1.35VP

1
1 2 @ PC202
0.1U_0402_10V7K

2
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@ PR202 0_0402_5%
1 2
<7> 0.675V_DDR_VTT_ON
1
1

EMI@ PC207
PC220

PC218

PC217

PC216

PC215

PC219

1
B 680P_0402_50V7K B
2

@ PC203
2

0.1U_0402_10V7K

2
1

EMI@ PR203
4.7_1206_5%
2

@ PJP200
+1.35VP 1 2 +1.35V_MEM
1 2
JUMP_43X118
@ PJP202
Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P 1 2
1 2
S5 L L off off off JUMP_43X118
S3 L H on on off
S0 H H on on on 2
@ PJP203
1
+0.675VSP 2 1 +0.675V_DDR_VTT
JUMP_43X79

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
PWR_+1.35V_MEN/+0.675V_DDR_VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 44 of 64
5 4 3 2 1
 5 4 3 2 1

@
D PR314 D
0_0402_5%
1 2
SIO_SLP_SUS# <11,29,46,47>
@ PR313
0_0402_5%
1 2
POK <11,43,46,47>
@ PR312
0_0402_5%
EN_+1VALWP 1 2
+1.0V_PRIM_CORE_PG <46>

1
0.1U_0402_25V6
1
@ PC405
1M_0402_1%
PR302 @ PJP302

+1VALWP +1.0V_PRIM

2
1 2
1 2

2
JUMP_43X118

@EMI@ PR303 @EMI@ PC302

4.7_1206_5% 680P_0603_50V7K
1 2 SNB_+1VALWP 1 2
@ PJP301 PU301
+19VB 2 1 2200P_0402_50V7K +19VB_+1VALWP 8 1 @ PR304 PC304
0.1U_0402_25V6

2 1 IN EN 0_0603_5% 0.1U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K
JUMP_43X79 6 1
BST_+1VALWP 2 1 2 PL301
BS
1

1
0.68UH +-20% 7.9A
@ PC305

PC306
C 9 10 SW_+1VALWP 1 2 +1VALWP C
@EMI@ PC301

@EMI@ PC303

GND LX
2

330P_0402_50V7K

47U_0805_6.3V6M

47U_0805_6.3V6M

22U_0805_6.3VAM

22U_0805_6.3VAM
1

1
4 FB_+1VALWP

PC307
6.65K_0402_1%
FB

PC308

PC309

PC310

PC311
2
ILMT_+1VALWP 3 7

PR306
ILMT BYP +3VALW

2
+3VALW

4.7U_0603_6.3V6K

1
2 5

1K_0402_5%
4.7U_0603_6.3V6K
PG LDO

PC312

PR308
2
1
SYX196DQNC_QFN10_3X3

PC313
1

2
@ PR307

2
0_0402_5%
2

1
ILMT_+1VALWP
PR311
1

10K_0402_1%

@ PR310

2
0_0402_5%
2

B B

+1.0V_PRIM
TDC 2.63 A
Peak Current 3.748 A
OCP Current 6.0 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
PWR_+1VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 45 of 64
5 4 3 2 1
 5 4 3 2 1

+3VALW

1
PR404 Premium@
10K_0402_5%
@ PR425
0_0402_5%

2
1 2
<13,51> PM_ZVM#
PR402 Premium@
0_0402_5%
1 2
<11,17,29,40,41,51> SIO_SLP_S3#

EN_1VS_VCCIO
0.1U_0402_25V6
1

1
@ PC402
@
PR403
D 0_0402_5% D
@ PJP401

2
JUMP_43X79
1 2
+1VS_VCCIOP 1 2 +1.0VS_VCCIO

13

14

15

16

17
Vin=3~17V Premium@ PU401

TP
EN

PGND

PGND
LPM
@ PJP403

+3VALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP
Premium@ PL402

10U_0603_10V6M

10U_0603_10V6M
PAD-OPEN1x1m 1UH_PCMB041B-1R0MS_4.2A_20%
+3VALW

1
11 2 LX_1VS_VCCIO 1 2
+1VS_VCCIOP

Premium@ PC403

Premium@ PC404
PVIN SW

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
TPS62134ARGT_QFN16_3X3

Premium@ PC406

Premium@ PC407

PC422
10 3
AVIN SW

2
@

2200P_0402_50V7K
0.1U_0402_25V6
1

1
VID0_VCCIO 9 4

PC408

1SNUB_1VS_VCCIO
PC409
VID0 PG @EMI@ PR405
+3VALW
1

AGND
Premium@ 4.7_0603_5%

VID1

FBS
PR413 PR414 @ @EMI@

SS

2
10K_0402_1% 10K_0402_1%

Premium@EMI@
2

1
VID0_VCCIO Premium@

100_0402_1%
1
PR401 @EMI@ PC401
VID1_VCCIO

Premium@ PR421
10K_0402_1%

1SS_1VS_VCCIO
VID1_VCCIO 470P_0402_50V7K

2
2
1

2
Premium@
@ PR415 PR416

470P_0402_50V7K
10K_0402_1% 10K_0402_1% 1VS_VCCIO_PWRGD <11> Premium@
PR422
C C
2

2 1

Premium@ PC410
VCCIO_SENSE <17>

2
0_0402_5%
+1.0VS_VCCIO
PR412
Premium@ TDC 1.9 A
2 1 Peak Current 2.73 A
VSSIO_SENSE <17>
0.95V based on PDDG 0.91. OCP Current 4.2 A Fix by IC
"R" for SILERGY
0_0402_5% TYP MAX
Choke DCR 48.0mohm
+3VALW

1
PR410 Premium@
10K_0402_5%

@ PR426

2
PM_ZVM# 1 2

0_0402_5%

PR406
EN_1.0V_PRIM_COREP

Premium@DSX@ 0_0402_5%
1 2
<11,29,45,47> SIO_SLP_SUS#
PR428
0.1U_0402_25V6
1

Premium@N-DSX@ 0_0402_5%
@ PC411
0_0402_5%

1 2
PR407

<11,43,45,47> POK
2

@
@ PJP402
2

JUMP_43X79
1 2
13

14

15

16

17

+1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
B Vin=3~17V Premium@ PU402
B
TP
EN

PGND

PGND
LPM

@ PJP404

+3VALW 1 2 VIN_1V_PRIM 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3VALW Premium@ PL404
10U_0603_10V6M

10U_0603_10V6M

PAD-OPEN1x1m 1UH_PCMB041B-1R0MS_4.2A_20%
1

11 2 1 2
LX_1V_PRIM
+1.0V_PRIM_COREP
Premium@ PC412

Premium@ PC413

PVIN SW

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

TPS62134DRGT_QFN16_3X3

1
10 3

Premium@ PC424

Premium@ PC415

PC416
AVIN SW
Rup
2200P_0402_50V7K

2
@
0.1U_0402_25V6
1

1
9 4
PC417

PC418

Premium@ @ VID0 PG @EMI@ PR409

1 SNUB_1V_PRIM

PR417 PR418
499K_0402_1%
2

AGND

10K_0402_1% 10K_0402_1% 4.7_0603_5%

Premium@
VID0_PRIM_CORE

VID1

FBS

PR427
@EMI@

SS
Premium@EMI@
2

VID0_PRIM_CORE
+1.0V_PRIM_CORE
8

VID1_PRIM_CORE TDC 1.8 A

2

@EMI@ PC419
Peak Current 2.57 A
SS_1V_PRIM

+3VALW OCP Current 4.2 A Fix by IC

1

470P_0402_50V7K
VID1_PRIM_CORE

Premium@ @ PR408
@ PR419 PR420 0_0402_5% TYP MAX
10K_0402_1% 10K_0402_1%
<18> CORE_VID0
1 2 Choke DCR 48.0mohm
Premium@
470P_0402_50V7K
2

<45> +1.0V_PRIM_CORE_PG
PR423
1

@ PR411
0_0402_5% 1 2
Premium@ PC420

<18> CORE_VID1
1 2
2

5.23K_0402_1%
1

Premium@
PR424
A 100K_0402_1% A
0.95V based on PDDG 0.91.
2

"R" for SILERGY

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
PWR_+1VS_VCCIOP/+1.0V_PRIM_COREP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 46 of 64
5 4 3 2 1
 5 4 3 2 1

TDC = 0.76A
Prak current : 1.096A
OCP : 3A
FB=0.6V

@ PJP502
JUMP_43X79
D D
1 2
+1.8VALWP 1 2 +1.8V_PRIM

PC502
22U_0603_6.3V6M

1 2 PU501
SY8032ABC_SOT23-6
@ PJP501 PL501
JUMP_43X79 1UH +-20% 2.3A 2.5X2X1.2
1 2 VIN_1.8VALW 4 3 LX_1.8VALW 1 2
+3VALW 1 2 IN LX +1.8VALWP
5 2
PG GND

22U_0603_6.3V6M

22U_0603_6.3V6M
1
6 1

68P_0402_50V8J
FB EN

1
@EMI@ PR502

PC501

PC504
1
PR501

PC503
DSX@ PR504 4.7_0603_5%

2
0_0402_5% 20K_0402_1%

2
1 2 EN_1.8VALW
<11,29,45,46> SIO_SLP_SUS#

2
SNUB_1.8VALW
Rup

1
N_DSX@ PR507

1
0_0402_5% @ PC505 FB_1.8VALW

1M_0402_1%
1 2

PR505
<11,43,45,46> POK
0.1U_0402_16V7K

1
2
PR506

1
non-DS3 @EMI@ PC506
10K_0402_1%
Rdown
680P_0402_50V7K

2
C
Note: C
When design Vin=5V, please stuff snubber +1.8V_PRIM
to prevent Vin damage TDC 0.66 A
Vout=0.6V* (1+Rup/Rdown) Peak Current 0.95 A
OCP Current 3.5A fix by IC

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.8V_PRIM and +1.5VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 47 of 64
5 4 3 2 1
 5 4 3 2 1

VCC_SA
+1.0V_VCCST Loadline : 10.3m-ohm
@ PJP603

@ PR602
TDC 5A 1 2
0_0402_5% Peak Current 5A VCCSA_B+ CPU_B+

0.1U_0402_25V6
1

1
1 2
OCP current 7A

45.3_0402_1%

75_0402_1%

100_0402_1%
+5VALW

PC602
PAD-OPEN1x1m

PR605
PR601

PR604
Local sense put on HW site @ PR603 Choke DCR 12 +-5%m ohm

2
0_0402_5%
@ 1 2 CPU_B+

0.22U_0603_25V7K
2

2
@ PR606 0_0402_5%

1U_0603_10V6K
D 1 2 1 VR_SCLK 2 D
<15> VIDSCLK

1
49.9_0402_1% PR618

PC603

PC604
<15> VIDALERT_N @ PR607 1 2 0_0402_5% 1 2 VR_ALERT#
@ PR625 0_0402_5%

2
<15> VIDSOUT @ PR609 1 2 0_0402_5% 1 2 VR_SDA
10_0402_1% PR626
<12,29,41,42> H_PROCHOT# PR678 VCCSA_B+
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
U22@ PR608
PH601 PR610 78.7K_0402_1%

10U_0805_25V6K

10U_0805_25V6K
470K_0402_5%_ TSM0B474J4702RE 10K_0402_1% 1 2
1 2 1 2 PR613 1.91K_0402_1% PR612

1
86.6K_0402_1% 1 2 PR611
+3VS

PC612

PC608
1 2 1 2 48.7K_0402_1%
PR631 PC613

2
27.4K_0402_1% 330P_0402_50V8J @ PR616
1 2 1 2
<11,49> IMVP_VR_ON
PC614 PR617
2200P_0402_50V7K 3.6K_0402_1% 0_0402_5%
1 2 1 2

40
39
38
37
36
35
34
33
32
31
PU602
PC616 @ PR619

VR_HOT#

ALERT#

PROG1
PROG2
SCLK

SDA
VR_ENABLE
VR_READY

VCC
VIN
33P_0402_50V8J 1 2
1 2 U22@ PC617 U22@ PR621 @ PR620 0_0402_5%
220P_0402_50V7K 1K_0402_1% 1 2 1 30 PWM_VSA 0_0603_5% PU606 AON7934_DFN3X3A-8-10
<29,42> I_SYS PSYS PWM_C

1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ501
<16> VCC_GT_SENSE IMON_B FCCM_C
PR622 3 28

D1

D1

D1

G1
@ PC618 1.96K_0402_1% 4 NTC_B ISUMN_C 27 1 8 PL601
1 2 1 2 5 COMP_B ISUMP_C 26 PC611 UGATE PHASE 0.68UH +-20% 7.9A
FB_B RTN_C
0.082U_0402_16V7K

6 25 FB_VSA 1 2 2 7 10 9 SA_SW 1 2
PC620

RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA

1

7 24

PR627 @EMI@
330P_0402_50V7K COMP_VSA 0.22U_0603_16V7K
U22@ PC621 PR623 8 ISUMP_B COMP_C 23 IMON_VSA PWM_VSA 3 6
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C

G2
S2

S2

S2

4.7_1206_5%
ISEN1_B PWM_A PWM_IA <49>
2

1
1 2 @ 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_IA <49> GND LGATE

1
TP
ISUMN_A
ISUMP_A
PR624

PWM1_B
PWM2_B

COMP_A

8
FCCM_B
41

IMON_A
0.01U_0402_50V7K

NTC_A

RTN_A
AGND 3.65K_0603_1%

1
FB_A
<16> VSS_GT_SENSE

2
@ PR679
0_0402_5%

ISUMP_VSA 2
11
12
13
14
15
16
17
18
19
20

SA_SNUB

ISUMN_VSA
ISL95859HRTZ-T_TQFN40_5X5
+5VALW

2
1
<49> ISUMP_GT

1U_0402_10V6K
IMON_IA
<49> FCCM_GT

FB_IA
NTC_IA

FCCM_VSA
COMP_IA

PC685
<49> PWM1_GT
4.42K_0402_1%

2
1

@ PR637 <49> PWM2_GT

1
PC625
PR628

20M_0402_5%

680P_0603_50V7K
330P_0402_50V7K

1
1 2
10K_0402_5%_ERTJ0ER103J

@EMI@ PC622
U22@ @ PR654
PR629
2

2
0.047U_0402_25V7K

84.5K_0402_1%

2
0.047U_0402_25V7K
1

1
1 2 20M_0402_5%
PC624

U22@ PC626

10P_0402_50V8J

4.02K_0402_1%
PC627 PH603

PR630
1

1
PR632 470K_0402_5%_ TSM0B474J4702RE
11K_0402_1%

2200P_0402_50V7K

1200P_0402_50V7K
2200P_0402_50V7K
1

1K_0402_1% 1 2 1 2
PH602

PR633

PC628
1 2 1 2 ISUMP_VSA

2
PR647 27.4K_0402_1% PR635 1 2

255_0402_1%
1
U22@ PR638 1 2 10K_0402_1%
2

2.61K_0402_1%
1

1
274_0402_1% PR636 1.24K_0402_1%

PC630

PR640
2

1 2 PC629

PC631
<49> ISUMN_GT PR639

PR642
2200P_0402_50V7K 3K_0402_1% 1 2 1 2

2
1 2 1 2

2
PR638 U23@ U23@ PC635 PC632 PR641

10KB_0402_5%_ERTJ0ER103J
U22@

2
2
0.033U_0402_16V7K
0.022U_0402_16V7K PC636 2200P_0402_25V7K 1K_0402_1%

1K_0402_1%

11K_0402_1%
1 2 ISEN1_GT 33P_0402_50V8J

PR643
6800P_0402_25V7K
1

1
1 2

PR644

PC633
PC637
U23@ PC638

1
B 0.022U_0402_16V7K PC639 PR645 PR646 PC640 B

1
357_0402_1% 1 2 ISEN2_GT 2200P_0402_25V7K 316_0402_1% 1 2 1 2 @
1 2 1 2
.1U_0402_16V7K

330P_0402_50V7K
2
1

PR622 U23@ 316_0402_1% 2200P_0402_25V7K

+5VALW

PH604
U22@ PR648
PC641

2
1 2 PR649
2

1
1 2

PR651
140K_0402_1%
1
PR615 U22@ 1.37K_0402_1% PC642 ISUMN_VSA
<49> ISEN1_GT
0_0402_5% 0.047U_0402_25V7K 1.69K_0402_1% PC644

PC643
2K_0402_1%
1

1
2.55K_0402_1% 1 2 1 2 .1U_0402_16V7K

2K_0402_1%
<49> ISEN2_GT

2
1 2

U22@

PR652
2
.1U_0402_16V7K
1
PR650

U22@ U23@ PR634 U22@

0_0402_5%
PC645
2

1 2
1 2 PC646
680P_0402_50V7K

680P_0402_50V7K
0.047U_0402_25V7K
PR622 1.96k 2.55K
2

PR629 U23@ PR640 U23@ PR648 U23@ 1 2 VSA_SEN- <17>

PC647

PC601
2
PR648 1.37K 1.54k
1

PC649
0.01U_0402_50V7K
1 2
PR629 84.5K 88.7K

0.082U_0402_16V7K
88.7K_0402_1% 280_0402_1% 1.54K_0402_1% PR656
11K_0402_1%
<15> VCCSENSE

2
1 2
PR651 140K 80.6K

PC650
PR651 U23@ PC626 U23@ PR608 U23@ @ PC652
PR657
330P_0402_50V7K

1
PR608 78.7K 100K 1
@ PC651
2 4.42K_0402_1%
PH605
10KB_0402_5%_ERTJ0ER103J
@
1 2
1 2 1 2
0.082U_0402_16V7K

PR638 274 357 330P_0402_50V7K

PC653
1

80.6K_0402_1% 0.15u_0402_16V7K 100K_0402_1%

VSA_SEN+ <17>

PR640 255 280 PC621 U23@ PR621 U23@ PC617 U23@ ISUMN_IA <49>
2

PC654 @
A 1 2 A

PC626 0.047U 0.15U 0.01U_0402_50V7K

ISUMP_IA <49>
1

PC621 680P 470P 470P_0402_50V7K 316_0402_1% 390P_0402_50V7K @ PR653

<15> VSSSENSE
20M_0402_5% DELL CONFIDENTIAL/PROPRIETARY
PR621 1K 316 PC614 U23@
Local sense put on HW site
2

Security Classification Compal Secret Data Compal Electronics, Inc.

PC617 220P 390P Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
PWR_+VCC_SA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PC614 2200P 6800P 6800P_0402_25V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Document Number Rev
1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 48 of 64
5 4 3 2 1
 5 4 3 2 1

VCC_core VCC_GT
U22 - 15W U22 - 15W
Loadline : 2.4m-ohm Loadline : 3.1m-ohm
U23e - 15W U23e - 15W
Loadline : 2.4m-ohm Loadline : 2m-ohm
TDC 21A U22-15W
D
Peak Current 29A TDC 18A D
OCP current 34A Peak Current 31A
Choke DCR 0.66 +-7%m ohm OCP current 37A
+19VB Choke DCR 0.66 +-7%m ohm
@ PJP601
1 2

CPU_B+ PAD-OPEN 4x4m

U23e-15W
TDC 36A
@EMI@ PL602
1 2 Peak Current 64A
OCP current 77A
@EMI@

@EMI@

PWM_IA <48>

1
5.11K_0402_1%
FBMA-L11-453215800LMA90T_2P
Choke DCR 0.66 +-7%m ohm

PR662
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6K~D

S ELE CAP 33U 25V

1

+
PC656

PC657

PC658

PC659

PC660

PC606

2
@
2

+5VALW
@ PR655
1U_0402_10V6K
1

0_0402_5%
DRMOS_EN 2 1
PC661

IMVP_VR_ON <11,48>
PU603
2

AOZ5019QI_QFN23_5X3P5
@ PR659 CPU_B+
0_0402_5% 13 GPU_B+
<48> FCCM_IA 2 1 @ PR660 1 PWM 12 PL603
0_0603_5% 2 SMOD EN 11 .15UH +-20% 29A 7X7X4 MOLDING
1 2 3 VCC VIN 10
C
4 BOOT CGND 9 C
0.22U_0603_16V7K GH GL
1 2 5 8 4 1 @ PJP602

PC668 @EMI@

PC674 @EMI@
CORE_SW
6 VSWH
VIN
VSWH
PGND
7 PR663 @EMI@ +VCC_CORE GPU_B+
1 2
CPU_B+

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6K~D
PC655 3 2
10P_0402_25V8J

PAD-OPEN 1x2m~D
4.7_1206_5%
1

1
PC680
PC686

U23@ PC664

U23@ PC665
1
1000P_0402_50V7K PR661 PWM2_GT <48>
2
2

2
3.65K_0603_1%

1
5.11K_0402_1%
PR681
2

2
CORE_SNUB

<48>

<48>
@
ISUMP_IA

ISUMN_IA

2
+5VALW
U23@ PR664
0_0402_5%
<48,49> FCCM_GT DRMOS_EN
680P_0603_50V7K

2 1 U23@ PU604
1

AOZ5019QI_QFN23_5X3P5
GPU_B+
@EMI@ PC662

1U_0402_10V6K
1
13
PWM
2

1 12 U23@ PL604

U23@ PC669
0_0603_5% 2 SMOD EN 11 .15UH +-20% 29A 7X7X4 MOLDING
VCC VIN

2
U23@ 1 PR665 2 3 10
4 BOOT CGND 9
0.22U_0603_16V7K
1 2 5 GH GL 8 4 1
GT_SW2
6 VSWH VSWH 7 +VCC_GT

PR669 @EMI@
GPU_B+ U23@ PC663 VIN PGND 3 2

10P_0402_25V8J

4.7_1206_5%

GT2P
1

1
U23@ PC681 GT2N

U23@ PC687

1
1000P_0402_50V7K

2
U23@ PR667 U23@ PR668 U23@ PR666

2
PC666 @EMI@

PC667 @EMI@

3.65K_0603_1% 100K_0402_1% 10_0402_1%

B 1 2 1 2 B
10U_0805_25V6K

10U_0805_25V6K

2
2200P_0402_50V7K
0.1U_0402_25V6K~D

PWM1_GT <48>

2
ISUMP_GT
<48,49>
<48> ISEN2_GT
1

1
5.11K_0402_1%

<48,49>
ISUMN_GT
PC672

PC673

GT_SNUB2
@ PR670
PR680

GT1N 1 2
2

100K_0402_1%
2

+5VALW @ PR671

680P_0603_50V7K
1
0_0402_5%

@EMI@ PC670
<48,49> FCCM_GT
2 1 DRMOS_EN

2
PU605
AOZ5019QI_QFN23_5X3P5
GPU_B+
1U_0402_10V6K
1

13
PC677

@ PR672 1 PWM 12 PL605

SMOD EN
2

0_0603_5% 2 11 .15UH +-20% 29A 7X7X4 MOLDING

1 2 3 VCC VIN 10
4 BOOT CGND 9
0.22U_0603_16V7K GH GL
1 2 5 8 GT_SW1 4 1
6 VSWH VSWH 7 +VCC_GT
PR676 @EMI@

PC671 VIN PGND 3 2

10P_0402_25V8J

4.7_1206_5%

GT1P
1

PC679 GT1N
PC688

1000P_0402_50V7K
2

PR674 U23@ PR675 PR673

2

3.65K_0603_1% 100K_0402_1% 10_0402_1%

1 2 1 2
2

<48> ISEN1_GT
<48,49>
ISUMN_GT

A A
@ PR677
GT_SNUB1

GT2N 2 1
100K_0402_1%
ISUMP_GT

<48,49>

DELL CONFIDENTIAL/PROPRIETARY
680P_0603_50V7K
1

Compal Electronics, Inc.

@EMI@ PC678

Security Classification Compal Secret Data

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCC_core and +VCC_GT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 49 of 64
5 4 3 2 1
 4
3
2
1
+VCC_CORE

A
A

2 1 2 1

2
1
2
1

+
PC1099 PC1083 PC1076
220U 2V Y D2

+VCC_GT
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
U22@ PC1127
2 1 2 1

2
1
2
1
2
1
U22-15W

PC1095 PC1030 U23@ PC1081 PC1078

220U 2V Y D2
U23e-15W

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1062
U22@ PC1221 2 1 2 1 2 1

2
1
2
1

22U_0603_6.3V6M
@

PC1170 PC1094 PC1031 PC1080 PC1077

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1222 2 1 2 1 2 1

2
1
2
1

22U_0603_6.3V6M
@

PC1171 PC1096 PC1032 U23@ PC1082 PC1079

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@ PC1223 2 1 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
@ PC1172 PC1090 PC1033 @ PC1067 U23@ PC1001
VCC_CORE Place on CPU

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1224 2 1 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
@ PC1173 PC1093 PC1034 PC1072 U23@ PC1002

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1158 2 1 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
@ PC1174 PC1091 PC1035 PC1069 PC1003

2
1
22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1162 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
PC1097 PC1036 U23@ PC1074 U23@ PC1004

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U23@ PC1159 2 1 2 1

B
B

2
1
2
1

22U_0603_6.3V6M
PC1092 PC1037 PC1070 U23@ PC1005

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1154 2 1 2 1
2
1
2
1

22U_0603_6.3V6M

PC1127 U23@

330U 2V Y D2
PC1098 PC1038 PC1061 PC1006

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U22@ PC1161 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
@

PC1050 PC1039 PC1071 PC1007

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 * 27 pcs +1U_0201*35 pcs+330u_D2*2 pcs
22U_0603 * 18 pcs +1U_0201*35 pcs+220u_D2*2 pcs

PC1163 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
PC1051 PC1084 PC1066 PC1008

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1062 U23@

330U 2V Y D2
U22@ PC1155 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
@
@

PC1052 PC1086 PC1073 PC1009

2
1
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@ PC1156 2 1 2 1
2
1
2
1

For GTX
22U_0603_6.3V6M
PC1053 PC1085 PC1068 PC1010
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1

PC1054 PC1088 PC1075 PC1011

U22-15W
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

U23e-15W
2 1 2 1
2
1
2
1

PC1126 PC1087 U23@ PC1064 U23@ PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
1
2
1

Issued Date
@

PC1164 PC1089 PC1065 PC1013

+VGA_CORE

2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

C
C

Security Classification
VGA@ 330U_D2_2V_Y 2 1
PC836
PC1125
VCC_SA Place on CPU

2
1
+
1U_0201_6.3V6M
VGA@ 330U_D2_2V_Y
PC837

2
1
VGA@ 330U_D2_2V_Y
PC838

2
1
+

2015/07/09
VGA@ 330U_D2_2V_Y
PC839
22U_0603 * 9 pcs + 1U_0201*7 pcs
22U_0603 * 12 pcs + 1U_0201*7 pcs
+VCC_GT

2
1
+

330U 2V Y D2
U22@ PC1128
2 1
2
1
2
1
2
1

For VGACORE
PC1040 @ PC1133 U22@ PC1014
330U 2V Y D2
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
@ PC1063
2 1
+

2
1
2
1
2
1

+VCC_SA

Compal Secret Data

PC1041 @ PC1137 @ PC1015
330U 2V Y D2

Deciphered Date
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
U23@ PC1101
2 1
U22-15W

2
1
2
1
2
1

+
U23e-15W

2 1 330U 2V Y D2
PC1042 U23@ PC1129 U23@ PC1016
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

U23@ PC1100

D
D

PC1153 U23@ PC1057 2 1 2 1

2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 U22@ PC1181 PC1043 U23@ PC1132 @ PC1017
2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PC1147 U23@ PC1058 2 1 2 1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2016/07/31

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2 1 U23@ PC1180 PC1044 U22@ PC1136 U22@ PC1018

2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2 1 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

PC1148 PC1059
VCC_GT Place on CPU

2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 U23@ PC1177 PC1045 U22@ PC1134 @ PC1019
2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1149 PC1060 2 1 2 1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 U22@ PC1179 PC1046 @ PC1135 U22@ PC1020
2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1150 PC1139 2 1 2 1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
Size

Date:
Title

2 1 U22@ PC1176 PC1047 @ PC1138 U23@ PC1021

2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1151 PC1140 2 1 2 1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 U22@ PC1178 PC1048 U23@ PC1027 U23@ PC1022
2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1152 PC1141 2 1 2 1
2
1
2
1

1U_0201_6.3V6M 22U_0603_6.3V6M
Document Number

U22@ PC1175 PC1049 U22@ PC1028 U22@ PC1023

2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

U23@ PC1142 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
Thursday, July 09, 2015

U22@ PC1182 PC1055 @ PC1130 U22@ PC1024

2
1

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1143 2 1 2 1
2
1
2
1

22U_0603_6.3V6M
U22@ PC1184 PC1056 U23@ PC1029 @ PC1025
E
E

2
1
22U_0603 * 48 pcs +1U_0201*12 pcs+330u_D2*4 pcs
22U_0603 * 25 pcs +1U_0201*12 pcs+330u_D2*1 pcs

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1144 2 1
2
1
2
1

22U_0603_6.3V6M
Sheet

PC1183 U23@ PC1131 U23@ PC1026

2
1

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1145
50

22U_0603_6.3V6M
2
1

Compal Electronics, Inc.

of

PC1146
22U_0603_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY

64
PWR_CPU&VGA bulk and MLCC
Rev
4
3
2
1

1.0(A00)
 5 4 3 2 1

+3VALW

1
U23@ PR1201
10K_0402_5%

@ PR1222

2
2 1
<13,46> PM_ZVM#
0_0402_5%
U23@ PR1200
0_0402_5%
1 2
<11,17,29,40,41,46> SIO_SLP_S3#

EN_VCC_EDRAM
1

1
@ PC1200
0.1U_0402_25V6
@
PR1202
D 0_0402_5% D
@ PJP1200

2
JUMP_43X79
1 2
+VCC_EDRAM_P 1 2 +VCC_EDRAM

2
U23@

13

14

15

16

17
Vin=3~17V PU1200

TP
EN

PGND

PGND
LPM
@ PJP1202

+3VALW 1 2 VIN_VCC_EDRAM 12
PVIN VOS
1
+VCC_EDRAM_P
U23@ PL1200

10U_0603_25V6M

10U_0603_25V6M
PAD-OPEN1x1m 1UH_PCMB041B-1R0MS_4.2A_20%
+3VALW

1
11 2 LX_VCC_EDRAM 1 2
+VCC_EDRAM_P

U23@ PC1201

U23@ PC1202
PVIN SW

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

2
SY8057QDC_QFN16_3X3TP

1
10 3

U23@ PC1203

U23@ PC1204

PC1205
AVIN SW

2200P_0402_50V7K

2
0.1U_0402_25V6

1SNUB_VCC_EDRAM
1

1
VID0_EDRAM_VR 9 4 @

@EMI@ PC1208

PC1209
VID0 PG @EMI@ PR1204
1

AGND
U23@ @ 4.7_0603_5%

VID1

FBS
PR1205 PR1203

SS

2
10K_0402_1% 10K_0402_1%

U23@EMI@
2

SS_VCC_EDRAM 7

5
VID0_EDRAM_VR
@EMI@ PC1210
VID1_EDRAM_VR

1
VID1_EDRAM_VR 470P_0402_50V7K

100_0402_1%
2

U23@ PR1206
1

@ PR1207 U23@ PR1208

2
10K_0402_1% 10K_0402_1%

1
C U23@ PR1209 C
2

U23@ PR1225 2 1
0_0402_5% VCC_EDRAM_SENSE <15>
0_0402_5%
+VCC_EDRAM

2
TDC 1.75 A
U23@ PR1210
2 1 Peak Current 2.5 A
VSS_EDRAM_SENSE <15> OCP Current 4.2 A Fix by IC
0_0402_5%
TYP MAX
Choke DCR 48.0mohm
+3VALW

1
U23@
PR1211
10K_0402_5%

2
PR1223
PM_ZVM# 2 1

U23@ 0_0402_5%
PR1212
0_0402_5%
SIO_SLP_S3# 1 2
EN_VCC_EOPIO
0.1U_0402_25V6
1

1
@ PC1212

PR1213
@

0_0402_5%
2

@ PJP1201
2

JUMP_43X79
1 2
13

14

15

16

17

+VCC_EOPIO_P 1 2 +VCC_EOPIO
B Vin=3~17V U23@ PU1201
B
TP
EN

PGND

PGND
LPM

@ PJP1203

+3VALW 1 2 VIN_VCC_EOPIO 12
PVIN VOS
1
+VCC_EOPIO_P
10U_0603_25V6M

10U_0603_25V6M

U23@ PL1201
PAD-OPEN1x1m
1

1UH_PCMB041B-1R0MS_4.2A_20%
U23@ PC1213

U23@ PC1214

11 2 1 2
PVIN SW
LX_VCC_EOPIO
+VCC_EOPIO_P
2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
SY8057QDC_QFN16_3X3

1
10 3

U23@ PC1215

U23@ PC1216

PC1225
AVIN SW
Rup
U23@ PC1218

+1.0V_VCCSTG
2200P_0402_50V7K

2
0.1U_0402_25V6
1

9 4
1 SNUB_VCC_EOPIO

VID0_EOPIO_VR @
@EMI@ PC1217

VID0 PG @EMI@ PR1216

2

AGND

4.7_0603_5%
VID1

FBS
2

@
SS

PR1290
100K_0402_1%
+VCC_EOPIO
8

TDC 1.4 A
@EMI@ PC1219
Peak Current 2 A
1

1
U23@

100_0402_1%
U23@ PR1219
SS_VCC_EOPIO

PR1224 VID1_EOPIO_VR 470P_0402_50V7K OCP Current 4.2 A Fix by IC

2

0_0402_5%
1 2 TYP MAX
MSM_N <13>
Choke DCR 48.0mohm
2 U23@
PR1220
1

2 1
VCCEOPIO_SENSE <15>
1

U23@ PR1226
U23@ @ 0_0402_5% 0_0402_5%
PR1214 PR1215
10K_0402_1% 10K_0402_1%
2

A U23@ PR1221 A
2

VID0_EOPIO_VR 2 1
VSSEOPIO_SENSE <15>
VID1_EOPIO_VR 0_0402_5%
1

DELL CONFIDENTIAL/PROPRIETARY
@

PR1217 U23@ PR1218

10K_0402_1% 10K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCCEDRAM / +VCCEPOIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 51 of 64
5 4 3 2 1
 5 4 3 2 1

+19VB_GPU @ PJP1101
2 1
2 1
JUMP_43X79

@VGA@EMI@ PL1101
FBMJ4516HS720NT_2P
1 2
+19VB

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K

0.1U_0402_25V6K
1
5

VGA@EMI@ PC1107
PC1103

PC1104

PC1105

@EMI@ PC1106
AON6552_DFN5X6-8-5
D D

2
2

2
VGA@ PQ1101

VGA@

VGA@

VGA@
UG2_VGA 4

SH000011H00 (DCR:0.98m± 5%)

PL1102

3
2
1
@ 0.22UH_24A_20%_7X7X4_MOLDING

10K_0402_1% VGA@

10K_0402_1% VGA@
VGA@
LX2_VGA 1 2

32.4K_0402_1%
@ PR1103
VGA@
PC1108 VGA@ PR1104
+VGA_CORE
0_0603_5% 0.22U_0603_25V7K @EMI@ 10K_0402_1%

1
BST2_VGA 1 2 1 2 PR1107 ISEN2_VGA 1 2

1
4.7_1206_5%
VGA@ PR1108

5
3.65K_0603_1%

AON6554_DFN5X6-8-5

AON6554_DFN5X6-8-5
+5VALW @EMI@ VSUM+_VGA1 2

PR1140

PR1105

PR1106

1 2
PC1109

2
680P_0603_50V7K VGA@ PR1110

VGA@ PQ1102

VGA@ PQ1103
1_0402_1%
LG2_VGA 4 4 VSUM-_VGA1 2

2
VGA@

41

40

39

38

37

36

35

34

33

32

31
PU1100

TP

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB

3
2
1

3
2
1
VGA_CORE (EXO-XT)
VGA@ PR1101 100K_0402_1% TDC 34A
1 2 1 30
VGA@ PR1111 100K_0402_1% NTC_NB BOOT2
BST2_VGA
Peak Current 51A
1 2 2
IMON_NB UGATE2
29 UG2_VGA OCP current 61.2A
3 28 LX2_VGA Load line XXmV/A (no need)
<57> SVI2_SVC SVC PHASE2
4 27 LG2_VGA +5VALW
<57> OCP_L
@ PR1112 100K_0402_1%
VR_HOT_L LGATE2 VGA_CORE (Meso-LE)
1 2 5 26
+3VS <57> SVI2_SVD SVD ISL62771HRTZ-T_TQFN40_5X5 VDDP VGA@ PR1114 +19VB_GPU TDC 28A
+1.8VGS
1 2 @ PR1113 0_0402_5% VDDIO_VGA6
VDDIO VDD
25 1 2 Peak Current 42A
1_0603_5%
OCP current 52.5A

1U_0603_10V6K
1

@ PR1115 0_0402_5% 7 24 LG1_VGA

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
C <57> SVI2_SVT SVT LGATE1 C

1
1 2 @ PR1116 0_0402_5% Load line 1mV/A ( need)

0.1U_0402_25V6
1U_0603_10V6K
+3VGS
PC1226 1 2 8
ENABLE_VGA 23 LX1_VGA

PC1111
<9,40> DGPU_PWR_EN ENABLE PHASE1
2

0.1U_0402_25V6K

VGA@ PC1110
2

1
5

1
9 22
VGA@ PWRGD_VGA UG1_VGA
FSW=300kHz

PC1116
PC1112

PC1113

PC1114

@EMI@ PC1115
PWROK UGATE1

AON6552_DFN5X6-8-5
1 2 IMON_VGA 10 21 BST1_VGA

VGA@

2
IMON BOOT1

2
+3VS
PR1117 VGA@

VGA@EMI@
PGOOD

VGA@ PQ1104
133K_0402_1%

VGA@

VGA@

VGA@
ISUMN
ISUMP

COMP
ISEN2

ISEN1

4
VSEN

UG1_VGA
NTC

RTN

1 2 VGA@ FB

1
1000P_0402_50V7K
PC1117
VGA@
PR1120
VGA@
PR1121 SH000011H00 (DCR:0.98m± 5%)
11

12

13

14

15

16

17

18

19

150K_0402_1% 13.3K_0402_1% 20 @ PR1119 PL1103

3
2
1
1 2 1 2 100K_0402_1% 1 2 0.22UH_24A_20%_7X7X4_MOLDING
DGPU_PWROK <12,29,40> VGA@

2
@ PR1122 LX1_VGA 1 2

1 2
PWRGD_VGA 0_0402_5%
@ PR1123
VGA@
PC1118 VGA@ PR1124
+VGA_CORE
@ PH1101 0_0603_5% 0.22U_0603_25V7K @EMI@ 10K_0402_1%

1
470K_0402_5%_TSM0B474J4702RE PC1119 VGA@ BST1_VGA 1 2 1 2 PR1125 ISEN1_VGA1 2
0.22U_0402_10V6K 4.7_1206_5%
1 2 ISEN2_VGA VGA@ PR1126

5
3.65K_0603_1%

AON6554_DFN5X6-8-5

AON6554_DFN5X6-8-5
PC1120 VGA@ @EMI@ VSUM+_VGA1 2

1 2
0.22U_0402_10V6K PC1121
VSUM-_VGA 1 2 ISEN1_VGA 680P_0603_50V7K VGA@ PR1128

VGA@ PQ1105

VGA@ PQ1106
1_0402_1%
VGA@ VGA@ VGA@ PC1123 LG1_VGA 4 4 VSUM-_VGA1 2

2
PC1122 PR1129 330P_0402_50V7K EXO@ PR1130
1000P_0402_50V7K 301_0402_1% 121K_0402_1%
VSUM+_VGA 1 2 1 2 1 2 1 2
PR1131 VGA@

330P_0402_50V7K

3
2
1

3
2
1
VGA@ VGA@
@ PC1124
2.61K_0402_1%

EXO@ PR1133
1

PR1134 PC1228
10K_0402_5%_ERTJ0ER103J

1.15K_0402_1% 22.1K_0402_1% 390P_0402_50V7K

0.15U_0603_16V7K
0.033U_0402_16V7K
11K_0402_1%
1

1 2 1 2 1 2
2
1

1
PR1132

VGA@ PC1232

VGA@ PC1230

VGA@ VGA@
1 2

PR1135 PC1233
2

2K_0402_1% 330P_0402_50V
2

1 2 1 2
VGA@
PH1102
VGA@

B EXO@ B
PR1136
2

562_0402_1%
VSUM-_VGA 1 2

@ PC1227 @ PR1138 PR1133 MESO@

1

VGA@ @ PR1137 820P_0402_50V7K 0_0402_5%

PC1231 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 VCCSENSE_VGA <57>
2

1 2 1K +-1% 0402
EXO@ MESO@
VSSSENSE_VGA <57>
0.01U_0402_50V7K

@ PR1139
PR1133 1.15k 1K
1

PC1229

0_0402_5% PR1136 MESO@

2

PR1136 562 470

VGA@

470 +-1% 0402

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
PWR_VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Docum ent Num ber Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 52 of 64
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Request Issue Solution
Item Page# Title Date Owner Description Description Rev.
D
1 NA HW NA COMPAL NA NA NA D

or PWR

2 COMPAL

3 COMPAL

4 COMPAL

5 COMPAL

6 COMPAL

7 COMPAL
C C
8 COMPAL

9 COMPAL

10 COMPAL

11 COMPAL 0.2(X01)

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_Change list
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 53 of 64
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List )

Re que st Owne r
Ite m Page # Title Date Issue Solution Re v.
De scription De scription
1 HW 20141124 COMPAL Power sequence 1. Add RC344 for PCH_DPWROK reserved. 0.1(X00)
2. Add UC13, RC343, RC345, RE429 for IMVP_VR_ON.

2 HW 20141124 COMPAL Debug conn 1. Delete JAPS1, JSPI1 0.1(X00)

3 HW 20141125 COMPAL Correct XDP conn and GPIO check 1. Change XDP conn 0.1(X00)
2. Add RE430 for GPIO021 reserve
3. Add RC356, RC357, RC358 for GPIO pull-up
4. Delete RC227, RC290, UC12, RC224

4 HW 20141126 COMPAL Circuit double 1. Delete P32, P33 for double circuit. 0.1(X00)

D
5 HW 20141128 COMPAL GPIO modify 1. Add RC360 for PWRGD_VGA 0.1(X00) D

2. Delete RC283, RC174, RC247, R6503, R6504, RC26, RC357, Q2505, R2504
, C620, C621, U74
3. Add DE6, Q6204, U5602

6 HW 20141203 COMPAL GPIO modify 1. Add RE437 0.1(X00)

2. Delete DE6

1. Delete C6203, R6205, R6208, R6217, R6213, Q2602,

7 HW 20141204 COMPAL Follow M16 EE implementation guide modify C2610, R2612, R2602, R2607 0.1(X00)
2. Add C6214, C6215, R6512, R6514, R6515, RC361

1. Add D5503, RE439,

8 HW 20141210 COMPAL 0.1(X00)

1. Add RC365
9 HW 20141212 COMPAL PCH Strap modify 2. Change VCCIO, EOPIO, EDRAM power enable by S3# 0.1(X00)
3. Delete RC362, RC363
4. VCCST_PWRGD control by EC

1. DDR_VTT_CNTL 1. Add UC14, CC57, RC123 for DDR_VTT_CNTL buffer

10 HW 20141216 COMPAL 2. CODEC 2. Delete RE34 0.1(X00)
3. LPC connector 3. change RE33 to 1K and move to D2701 pin1
4. VCCSTG control 4. Change R2717 to 10K
5. Move C2901 to AUD_SENSE_A and change to 0.1uF
6. Move EC2901~EC2904 to R2901~R2904 pin1
7. Move R2919, R2920, EC2905~EC2908 to R2906, R2907, R2909, R2911 pin1
8. Change C2907, C2908 to 10uF/10V/0603
9. Change DB2 location to DB1
10. Add UC15 for VCCSTG control, delete RZ73

1. SMBus power rail 1. pop RC15, RC17, de-pop RE426, RE427

11 HW 20141217 COMPAL 2. PROCPWRGD 2. RC77 de-pop 0.1(X00)
3. USB2_ID 3. Add RC366 to GND for USB2 OTG setting
4. CODEC 4. Change CODEC pin20 from +3VALW to +RTC_CELL
5. Touch pad 5. Add DZ3, RE440 for touch pad INT#
6. VRAM 6. GPU VRAM bit/Byte swap
7. GPU power 7. U5602 IN1/OUT1 swap with IN2/OUT2

1. GPU 1. Add RC367, delete RV60, RV254, RV255 for MESO VGA CORE power
12 HW 20141218 COMPAL 2. EC 2. Add RV260 for GPU_PWR_LEVEL 0.1(X00)
3. CPU 3. Change VREF_CPU to +1.0V_VCCST
4. DDI to VGA 4. Delete RC359, connect VCC_OPC_1P8 to +1.8V_PRIM
5. Change CC283~CC286 pin1 to +1.0V_PRIM
6. Add CC288~CC292 for +VCC_EDRAM
7. Add CC293~CC295 for VDDQ
8. Add CC296 for VDDQC
9. Add CC297 for VDDPLL_OC
10. Change UZ20 VIN from +1.0V_MPHYAON to +1.0V_PRIM
C
11. Add RC638 for +1.0V_PRIM to +1.0V_MPHYGT C

12. Delete R5409 for HDMI power config

13. Change U5502 pin 5, 20 from 3D3V_S0 to +3VS
14. Change HDD_DEVSLP to port 0

1. GPU 1. Add PCIe series caps for BOM control.

13 HW 20141219 COMPAL 2. CODEC 2. Swap VRAM bit for layout 0.1(X00)
3. Change +3V_1.8V_CPVDD to DGND

1. Power rail 1. Change VGA_CORE to +VGA_CORE

14 HW 20141222 COMPAL 2. Debug solution 2. Delete PJP102 0.1(X00)
3. Add R6517, RC369 for debug port
4. Swap RP pin for layout routing smoothly

1. Power rail 1. Change +1.0VS_VCCSTG to +1.0V_VCCSTG

15 HW 20141223 COMPAL 2. Debug solution 2. Delete RC369 0.1(X00)
3. Add R4621, R4622, RC207, R4702, R4703, R4704, R4706, C4701, U4701
, JWBD1 for debug port
4. Change PWR1, TPAD1 connector source
5. Delete LV25, LV26, +VDDCI

1. Debug solution 1. Delete R4621, R4622, RC207, R4702, R4703, R4704, R4706, C4701
16 HW 20141224 COMPAL , U4701, RC207 for debug port 0.1(X00)
2. Add RC62, RC63 for debug port

1. EMI CAP 1. Delete CC284, CC287, CC254 for placement 0.1(X00)

17 HW 20141226 COMPAL

1. GPIO 1. Change CLK_PCI_LPC_MEC to PCI_CLK_LPC1 0.1(X00)

18 HW 20141228 COMPAL 2. HSIO 2. Delete T4947, Add R5208~R5210 for PANEL_SIZE_ID
3. Add RC369 for SUS_STAT#/LPCPD#
4. Add RC307~RC373 for PROJECT_ID1, PROJECT_ID2
5. Add RC374~RC377 for BOARD_ID2, BOARD_ID3
6. Add RC378~RC381 for VRAM_ID1, VRAM_ID2
7. Swap SIO_EXT_SCI# to GPP_E5
8. Swap BLUETOOTH_EN to GPP_C9
9. Swap I2C_SDA_TP to GPP_C16
10. Swap I2C_SCL_TP to GPPC17
11. Add RC382 for LPSS_UART2_CTS#
12. Swap WLAN_RADIO_DIS# to GPP_D4
13. Add RC383 for DGPU_HOLD_RST#
14. Change RC358 to GND for DGPU_PWR_EN
15. Add R2504, Q2505, RC384 for RTC_DET#
16. Swap SIO_EXT_SMI# to GPP_E15
17. Swap SATA_ODD_DA# to GPP_E6
18. Add RC385, RC386 for HDMI_CRT_DET
19. Replace UE1 AC_PRESENT by DGPU_PWROK
20. Add RC387 for SIO_EXT_WAKE#
21, Add DZ4 for AC_PRESENT
22. Add R5809, Delete RE411
B
23. Delete RC342 and KBC_DPWROK B
24. Add RE441 for FAN1_TACH
25. Delete UC13, QE2, RE67, RE68, Add RC389 for ALL_SYS_PWRGD
26. Add UC16, CC298, RC71 for VCCST_PWRGD
27, Delete RZ77, RE429, CE83
28. Add RC390 for L_BKLT_EN_EC, delete D5502, R6506
29. Change VREF_CPU connect to +1.0V_PRIM
30. Swap PCIE_WAKE# to GPIO002
31. Swap CLK_PCIE_LAN_REQ# to port2
32. Swap LAN from PCIE port9 to port6
33. Swap USB2 port6 and por8 device (BT and Card Reader)

1. GPIO 1. Change UZ3 to single channel load switch 0.1(X00)

19 HW 20141229 COMPAL 2. Add C5801, C5802, C5805, R5809 for WLAN power
3. Add RC391 for EC_WAKE#
4. Add RC391 for ALL_SYS_PWRGD

1. GPIO 1. Add Q1901, R1902 for RTCRST_ON 0.1(X00)

20 HW 20141230 COMPAL
1. Change CPU part number 1.Change part number SA011405071 to SA00008M40L:UC1A~UC1T
2. Change capacitor part number 2.Change part number SE102104K80 to SE102104K00 : CC214,CC223,CC270,
21 HW 20150108 COMPAL 3. Change USB Load switch symbol and part CC281,CC297,CD24,CD25,CD26,CD27,CD32,CD57,CD58,CD59,CD60,CD64,CZ34,CZ44,
number CZ50,CZ78,CZ82,CZ86,CZ85,CZ88
4.Add CPU dummy symbol, modify PCB 3.Add CPU dummy symbol 2.3G,1.6G on page1 0.1(X00)
dummy symbol 4.Modify PCB dummy symbol part description to "PCB"
5.Change symbol and part number from SA00007BW00 to SA00007U200 :
U3504,U3505

A A

DELL CONFIDENTIAL/PROPRIETARY
Com pal Ele ctronics , Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE_Change lis t
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0(A00)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-D071P
Date: Thursday, July 09, 2015 Sheet 54 of 64
5 4 3 2 1
 5 4 3 2 1

Timing Diagram for S5 to S0 mode

+3VALW
2 +RTC_CELL
PCH 5
VCCRTC
SLP_SUS#
SIO_SLP_SUS#
TPS62134 +1.0V_PRIM_CORE 5
+1.0V_PRIM
+19VB
VCCPRIM_1P0
6
D D

CPU DCPDSW_1P0
+VCC_CORE VCCMPHYAON_1P0 +1.0V_PRIM_CORE_PG
VCCST_PWRGD VCCAPLL_1P0 SYX196 +1.0V_PRIM
12 VCCST_PWRGD VCC
VCCCLK1~6
+1.0VS_VCCIO +3VALW
VCCIO +1.0V_MPHYGT
H_CPUPWRGD
15 PROCPWRGD +VCC_GT VCCMPHYGT_1P0
VCCSRAM_1P0
SY8032 +1.8V_PRIM 5
VCCGT
VCCGTX VCCAMPHYPLL_1P0
PCH_PLTRST# +1.0V_PRIM VCCAPLLEBB
16 PLTRST#
+1.35V_MEM 6 +3VALW
MPHYP_PWR_EN
VDDQ +1.0V_MPHYGT TPS22961 EXT_PWR_GATE#
0.675V_DDR_VTT_ON VDDQC
12 VCCPLL_OC
5
@PCH_ALW_ON +3VALW_PCH
DDR_VTT_CNTL +1.0V_VCCST +3VALW +3.3V_ALW_DSW EM5209VF
VCCST 3 VCCDSW_3P3
VCCSTG
VCCPLL AUX_EN_WOWL 11
+3.3V_WLAN
PCH_DPWROK
+VCC_SA 4 DSW_PWROK
VCCSA
+V_EDRAM_VR
VCCOPC +3.3V_SPI 5 +3.3V_ALW_PCH RSMRST#
PCH_RSMRST#
7
+V1.8S_EDRAM VCCHDA
VCCSPI
VCC_OPC_1P8 VCCPRIM_3P3
VCCPGPPA~E PWRBTN#
SIO_PWRBTN# 8
+V_EOPIO_VR VCCRTCPRIM
VCCEOPIO SIO_SLP_S5#
+1.8V_PRIM
SLP_S5#
9
5 VCCPGPPG +1.0V_PRIM
VCCATS
10 10
SIO_SLP_S4#
SLP_S4# TPS22967 +1.0V_VCCST
C
5 +1.0V_PRIM_CORE
C
VCCPRIM_CORE
+19VB
+1.35V_MEM
16 PCH_PLTRST#
PLTRST# RT8207
+0.675V_DDR_VTT
VDDQ
VTT
DDR

12
0.675V_DDR_VTT_ON
Power Button

1BAT 2AC +5VALW

ADAPTER 2
+19VB
SIO_SLP_S3# 11
SLP_S3# +5VS
VL
EC 1404 ALWON
+5VALW EM5209VF
TPS51275 +3VS
+3VLP
+3VALW +3VALW
BATTERY
+3VALW

@PCH_ALW_ON TPS62134 +1.0VS_VCCIO

5
4 PCH_DPWROK

+3VALW

5 SIO_SLP_SUS# 12 +PWR_SRC
TPS62134 +VCC_EDRAM
IMVP_VR_ON
+VCC_SA
B
ISL95857 +VCC_CORE B

+3VALW
7 PCH_RSMRST#
+VCC_GT
@ALL_SYS_PWRGD TPS62134 +VCC_EOPIO
9 SIO_SLP_S5#
12 PCH_PWROK 13
VCCST_PWRGD
VCCST_PWRGD 12
10 SIO_SLP_S4#
PCH_PWROK
PCH_PWROK
13
11 SIO_SLP_S3#
H_CPUPWRGD
PROCPWRGD 15
AUX_EN_WOWL

11
RUNPWROK 11 RESET_OUT#
SYS_PWROK
14
RESET_OUT#
14

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev

LA-D071P 1.0(A00)

Date: Thursday , July 09, 2015 Sheet 55 of 64

5 4 3 2 1
 1 2 3 4 5

PEG_HTX_C_GRX_P[0..3]
<10> PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] No Use GPU Display Port outpud
<10> PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3] @
<10> PEG_GTX_C_HRX_P[0..3]
UV1F
PEG_GTX_C_HRX_N[0..3] +VGA_CORE_MESO
<10> PEG_GTX_C_HRX_N[0..3]

@ AB11
UV1A VARY_BL AB12
DIGON

A A

AL15
TXCAP_DPA3P AK14
PEG_HTX_C_GRX_P0 2
MESO@ 1 CV220 .1U_0402_16V7K PEG_HTX_GRX_P0 AF30 AH30 PEG_GTX_HRX_P0 2
MESO@ 1 CV1 .1U_0402_16V7K PEG_GTX_C_HRX_P0 TXCAM_DPA3N
PEG_HTX_C_GRX_N0 2
MESO@ 1 CV306 .1U_0402_16V7K PEG_HTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N0 2
MESO@ 1 CV2 .1U_0402_16V7K PEG_GTX_C_HRX_N0 AH16
PCIE_RX0N PCIE_TX0N TX0P_DPA2P AJ15
TX0M_DPA2N
PEG_HTX_C_GRX_P1 2
MESO@ 1 CV308 .1U_0402_16V7K PEG_HTX_GRX_P1 AE29 AG29 PEG_GTX_HRX_P1 2
MESO@ 1 CV3 .1U_0402_16V7K PEG_GTX_C_HRX_P1 AL17
PEG_HTX_C_GRX_N1 2
MESO@ 1 CV305 .1U_0402_16V7K PEG_HTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N1 2
MESO@ 1 CV4 .1U_0402_16V7K PEG_GTX_C_HRX_N1 TX1P_DPA1P AK16
PCIE_RX1N PCIE_TX1N TX1M_DPA1N
AH18
PEG_HTX_C_GRX_P2 2
MESO@ 1 CV307 .1U_0402_16V7K PEG_HTX_GRX_P2 AD30 AF27 PEG_GTX_HRX_P2 2
MESO@ 1 CV5 .1U_0402_16V7K PEG_GTX_C_HRX_P2 TX2P_DPA0P AJ17
PEG_HTX_C_GRX_N2 2
MESO@ 1 CV309 .1U_0402_16V7K PEG_HTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N2 2
MESO@ 1 CV6 .1U_0402_16V7K PEG_GTX_C_HRX_N2 TX2M_DPA0N
PCIE_RX2N PCIE_TX2N AL19
NC_TXOUT_L3P AK18
PEG_HTX_C_GRX_P3 2
MESO@ 1 CV219 .1U_0402_16V7K PEG_HTX_GRX_P3 AC29 AD27 PEG_GTX_HRX_P3 2
MESO@ 1 CV7 .1U_0402_16V7K PEG_GTX_C_HRX_P3 NC_TXOUT_L3N
PEG_HTX_C_GRX_N3 2
MESO@ 1 CV304 .1U_0402_16V7K PEG_HTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N3 2
MESO@ 1 CV8 .1U_0402_16V7K PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N TMDP

AB30 AC25 AH20

AA31 PCIE_RX4P PCIE_TX4P AB25 TXCBP_DPB3P AJ19
PCIE_RX4N PCIE_TX4N TXCBM_DPB3N
AL21
AA29 Y23 TX3P_DPB2P AK20
Y28 PCIE_RX5P PCIE_TX5P Y24 TX3M_DPB2N
PCIE_RX5N PCIE_TX5N AH22
TX4P_DPB1P AJ21
Y30 AB27 TX4M_DPB1N
W31 PCIE_RX6P PCIE_TX6P AB26 AL23
PCIE_RX6N PCIE_TX6N TX5P_DPB0P AK22
TX5M_DPB0N

UV1 GPU R1 UV1 GPU R3 W29

V28 PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
Y27
Y26 NC_TXOUT_U3P
NC_TXOUT_U3N
AK24
AJ23
B B
SA00008FE0L SA00008FE1L
V30 W24
MESOR1@ MESOR3@ U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
2160856030-A0_FCBGA631
?
MESO LE S3 BGA GPU 0FD MESO LE S3 FCBGA A31!
U29 V27
T28 NC#U29 NC#V27 U26
UV1 UV1 NC#T28 NC#U26

PCI EXPRESS INTERFACE

SA000089Y0L SA000089Y1L T30 U24
R31 NC#T30 NC#U24 U23
EXOR1@ EXOR3@ NC#R31 NC#U23

EXO XT S3 FCBGA631P 0FD EXO XT S3 FCBGA A31! R29 T26

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27 For EXO/MESO PCIe Gen3/Gen2 option

K30 NC#L29 NC#M27 N26
NC#K30 NC#N26 CV220 EXO@ CV306 EXO@ CV308 EXO@ CV305 EXO@

C CLOCK C
CLK_PEG_VGA AK30
<11> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32
<11> CLK_PEG_VGA# PCIE_REFCLKN +0.95VSDGPU
0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K
CALIBRATION SE00000R700 SE00000R700 SE00000R700 SE00000R700
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1% CV307 EXO@ CV304 EXO@ CV3 EXO@ CV6 EXO@
TEST_PG PCIE_CALR_RX

PLT_RST_VGA# AL27
PERSTB

2160856030-A0_FCBGA631 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K

SE00000R700 SE00000R700 SE00000R700 SE00000R700

CV309 EXO@ CV1 EXO@ CV4 EXO@ CV7 EXO@

+3VGS

UV2 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K

DIS@
5

PLT_RST# SE00000R700 SE00000R700 SE00000R700 SE00000R700

1
<11,25,29,32,36> PCH_PLTRST#_EC
P

IN1 4 PLT_RST_VGA#
2 O CV219 EXO@ CV2 EXO@ CV5 EXO@ CV8 EXO@
<9> DGPU_HOLD_RST# IN2
G

DGPU_HOLD_RST#(GPIO191)
3

RV4
SN74AHC1G08DCKR_SC70-5 100K_0402_5%
D D
DIS@
0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K 0.22U 16V 7K
2

SE00000R700 SE00000R700 SE00000R700 SE00000R700

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
EXO/MESO_PCIE/DP
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0(A00)
LA-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 56 of 64
1 2 3 4 5
 1 2 3 4 5

+3VGS
Resistor Divider Lookup Lable
@
UV1B +1.8VGS
U? 0402 1% resistors are equired PS_0[3:1]=001 Strap Name :
R_pu (ohm) R_pd (ohm) Bitd [3:1] PS_0[5:4]=11

1
AF2
PS_0[1] ROM_CONFIG[0]
RV5 RV6
NC#AF2

5
45.3K_0402_1% AF4 NC 4.75k RV8
45.3K_0402_1% 000 PS_0[2] ROM_CONFIG[1]

G
QV1B DIS@ DIS@ NC#AF4 8.45K_0402_1%
DIS@ @ 1 N9 AG3 DIS@
T201 DBG_DATA16 NC#AG3 8.45k 2k 001 PS_0[3] ROM_CONFIG[2]

2
@ 1 L9 AG5 PS_0
3 4 T202 1 AE9 DBG_DATA15 NC#AG5
VGA_SMB_DA3 @ DPA 4.53k 2k 010 PS_0[4] N/A
<8,29,38> GPU_THM_SMBDAT T203

S
DBG_DATA14

1
@ 1 Y11 AH3

D
T204 DBG_DATA13 NC#AH3 1

0.68U_0402_10V
@ 1 AE8 AH1 6.98k
T205 DBG_DATA12 NC#AH1 4.99k 011 PS_0[5] AUD_PORT_CONN_PINSTRAP[0]

2
DMN66D0LDW-7 2N SOT363-6 @ 1 AD9 CV29 RV9

G
T206 1 AC10 DBG_DATA11 AK3
QV1A @ 4.53k 4.99k 100 @ 2K_0402_1%
T207 1 AD7 DBG_DATA10 NC#AK3 AK1 2
DIS@ @ DIS@
T208 DBG_DATA9 NC#AK1

2
A @ 1 AC8 3.24k A
6 1 VGA_SMB_CK3 T209 1 AC7 DBG_DATA8
DVO
AK5
5.62k 101
<8,29,38> GPU_THM_SMBCLK T210@

S
@ 1 AB9 DBG_DATA7 NC#AK5 AM3

D
T211 1 AB8 DBG_DATA6 NC#AM3 3.4k 10k 110
@
T212 1 AB7 DBG_DATA5 AK6
DMN66D0LDW-7 2N SOT363-6 @ 4.75k NC 111
T213 1 AB4 DBG_DATA4 NC#AK6 AM5
@
T214 1 AB2 DBG_DATA3 NC#AM5
@ DPB
T215 1 Y8 DBG_DATA2 AJ7
T216@ 1 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS Strap Name :
@ PS_1[3:1]=000
+3VGS T217 DBG_DATA0 NC#AH6
AK8
Capacitor Divider Lookup Lable
MESO@ PS_1[5:4]=11 PS_1[1] STRAP_BIF_GEN3_EN_A
RV146 NC#AK8

1
+3VGS AL7
1 2 GPU_THM_INT NC#AL7 EXO@
Cap (nF) Bitd [5:4] PS_1[2] TRAP_BIF_CLK_PM_EN
RV11
4.7K_0402_5% W6 8.45K_0402_1% PS_1[3] N/A
NC#W6
2

MESO@ V6
NC#V6 680nF 00

2
RV58 V4 PS_1 PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING RV12 EXO@
+3VGS AC6 NC#V4 U5
4.7K_0402_5% SA010320110 (S IC ADM1032ARMZ MSOP 8P TEMP SENSOR) NC#AC5 NC#U5 82nF 01

1
AC5
NC#AC6 1 PS_1[5] STRAP_TX_DEEMPH_EN

0.68U_0402_10V
1000P_0402_50V7K W3 MESO@
NC#W3 10nF 10
1

MESO@ UV11 AA5 V2 CV28 RV12

1 2 VGA_DPLUS CV9 1
MESO@ 2 AA6 NC#AA5 NC#V2 @ 4.75K_0402_1%
VDD1 D+ NC#AA6 DPC
Y4
NC 11 2 2K_0402_1%
NC#Y4

2
GPU_THM_INT 6 3 VGA_DMINUS +1.8VGS W5
ALERT# D- NC#W5
SD034200180
MESO@ 1 4 8 VGA_SMB_CK3_R 1 2
MESO@ VGA_SMB_CK3 RV82 2 MESO@ 1 4.7K_0402_5%BP_0 U1 AA3 PLL_Analog_out
CV10 THERM# SCLK RV164 0_0402_5% @ 1FB_VDDCI W1 NC#U1 NC#AA3 Y2
T222 NC#W1 NC#Y2

1
0.1U_0402_16V4Z 5 7 VGA_SMB_DA3_R 1 2
MESO@ VGA_SMB_DA3 RV81 2 MESO@ 1 4.7K_0402_5%BP_1 U3
GND SDATA RV165 0_0402_5% Y6 NC#U3 J8 RV83
2 1PLL_Analog_in AA1 NC#Y6 NC#J8 +1.8VGS
T221@ NC#AA1
16.2K_0402_1% PS_2[3:1]=000 Strap Name :
ADM1032ARMZ_MSOP8 MESO@
PS_2[5:4]=11

1
Address: X100_1101(4D), 1001_101X(9A) PS_2[1] N/A
@
Main: For 2nd I2C RV28 PS_2[2] N/A
SA000084A00, S IC F75399M MSOP 8P TEMP. SENSOR SA00001Z710 (S IC EMC1402-2-ACZL-TR MSOP 8P SENSOR) @ 1 R1
8.45K_0402_1%
2nd: SA00003PU00 (S IC W83L771AWG-2 TSSOP 8P SENSOR) T223 SCL PS_2[3] STRAP_BIOS_ROM_EN

2
1 R3 PS_2
SA00003PU00, S IC W83L771AWG-2 TSSOP 8P SENSOR T224@ SDA
Chnage CPN first, Need apply CIS Symbol PS_2[4] STRAP_BIF_VGA_DIS
Jason 2015/03/03

1
AM26
SA000084A00, S IC F75399M MSOP 8P TEMP. SENSOR +VGA_CORE_MESO R 1

0.082U_0402_16V
AK26 PS_2[5] N/A
SA00003PU00, S IC W83L771AWG-2 TSSOP 8P SENSOR U6
GENERAL PURPOSE I/O
AVSSN#AK26 +3VGS CV11 RV13
Jason 2015/01/26 U10 GPIO_0 AL25 @ 4.75K_0402_1%
T10 GPIO_1 G AJ25 2 DIS@
GPIO_2 AVSSN#AJ25

2
1
2 DIS@ 1 VGA_SMB_DA3 U8
B +3VGS U7 SMBDATA AH24 B
RV260 10K_0402_5% VGA_SMB_CK3 RV162
T9 SMBCLK B AG25 4.7K_0402_5%
<29> GPU_PWR_LEVEL PCC_GPIO_6 T8 GPIO_5_AC_BATT AVSSN#AG25 @
T7 GPIO_6 DAC1 AH26
GPIO_7_BLON HSYNC

2
P10 AJ27 WAKEB
P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI

1
+VGA_CORE +VGA_CORE_MESO P2 +1.8VGS
Reduce 3.3V TO 1.8V level shift for EXO. N6 GPIO_10_ROMSCK AD22
PS_3[3:1]=000 Strap Name :
RV163
+VGA_CORE_MESO N5 GPIO_11 RSET
BOM contorl in POWER sheet GPIO_12
4.7K_0402_5% PS_3[5:4]=11

1
MESO@ N3 AG24 DIS@ PS_3[1] BOARD_CONFIG[0] (Memory ID)
RC367 1 2 0_0603_5% Y9 GPIO_13 AVDD AE22 @
GPIO_14_HPD2 AVSSQ VRAM Type

2
SVI2_SVD EXO@ 1 RV77 2 0_0402_5% GPU_VID3 N1 RV15 PS_3[2] BOARD_CONFIG[1] (Memory ID)
<52> SVI2_SVD M4 GPIO_15_PWRCNTL_0 AE23
R6 GPIO_16 VDD1DI AD23
8.45K_0402_1% Need reference
GPIO_17_THERMAL_INT VSS1DI PS_3[3] BOARD_CONFIG[2] (Memory ID) X76 Schematic

2
W10 PS_3
GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

1
<52> SVI2_SVC
SVI2_SVC EXO@ 1 RV78 2 0_0402_5% GPU_VID1 P8 AM12
1
GPIO_20_PWRCNTL_1 CEC_1

0.68U_0402_10V
P7 @ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
N8 GPIO_21 CV15 RV16
AK10 GPIO_22_ROMCSB AK12 MESO@ 1 RV155 2 0_0402_5% SVI2_SVD @ 4.75K_0402_1%
AM10 GPIO_29 RSVD#AK12 AL11 MESO@ 1 RV156 2 0_0402_5% SVI2_SVT 2 SD034475180
GPIO_30 RSVD#AL11 SVI2_SVT <52>

2
1 @ 2 PEG_CLKREQ#_G N7 AJ11 MESO@ 1 RV157 2 0_0402_5% SVI2_SVC
<11> PEG_CLKREQ# CLKREQB RSVD#AJ11
RV153 0_0402_5%
JTAG_TRSTB L6
JTAG_TDI_GPU L5 JTAG_TRSTB
JTAG_TCK L3 JTAG_TDI
JTAG_TMS_GPU L1 JTAG_TCK AL13
1 JTAG_TDO_GPU K4 JTAG_TMS GENLK_CLK AJ13
T86 @
TESTEN K7 JTAG_TDO GENLK_VSYNC
AF24 TESTEN
PAD
+VGA_CORE_MESO NC#AF24 AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB
+3VGS +1.8VGS W8 GENERICA
W9 GENERICB
W7 GENERICC AC19 PS_0
RV154 1 @ 2 5.1K_0402_1% RV152 @ AD10 GENERICD PS_0
2 1 GPIO19_CTF AJ9 GENERICE AD19 PS_1
1 AL9 NC#AJ9 PS_1
@
NC#AL9
RV17 1 DIS@ 2 1K_0402_1% TESTEN 10K_0402_5% T4935 AE17 PS_2
PS_2
2

AC14
1 PX_EN AB16 HPD1 AE20 PS_3
RV151 @
T218 PX_EN PS_3
10K_0402_5%
EXO@
C AE19 C
TS_A
1

AC16
DBG_VREFG
+3VGS

DDC/AUX
1 8 JTAG_TDI_GPU AE6
2 7 JTAG_TMS_GPU PLL/CLOCK DDC1CLK AE5
3 6 JTAG_TCK DDC1DATA
4 5 JTAG_TRSTB AD2
RV20 DIS@ AUX1P AD4 +VGA_CORE_MESO
1M_0402_5% RP34 10K_8P4R_5% AUX1N
XTALOUT XTALIN AC11
@ DDC2CLK AC13
YV1 DIS@ DDC2DATA
27MHZ_10PF_7V27000050 XTALIN AM28 AD13 Jason 6/24
XTALOUT AK28 XTALIN AUX2P AD11
3 1 XTALOUT AUX2N Short Pad
3 1
1 1 RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV158 1 @ 2 0_0402_5% VSSSENSE_VGA VSSSENSE_VGA <52>
CV18 GND GND CV17 RV59 1 DIS@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20 FB_VDDC RV159 1 @ 2 0_0402_5% VCCSENSE_VGA VCCSENSE_VGA <52>
XO_IN2 NC#AC20
8.2P_0402_50V8D 8.2P_0402_50V8D
4 2 AE16
DIS@
2 2
DIS@
NC#AE16 AD16
Short Pad
NC#AD16 Jason 6/24
SEYMOUR/FutureASIC AC1
+1.8VGS VGA_DPLUS T4 DDCVGACLK AC3
LV2 DIS@ VGA_DMINUS T2 DPLUS THERMAL DDCVGADATA +1.8VGS +3VGS
1 2 13mA DMINUS
BLM15BD121SN1D_0402
DIS@ GPIO28 R5 +VGA_CORE 1 MESO@ 2 1 EXO@ 2
Change CV17, CV18 for YV1 2nd source. CV19 2 1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO RV71 0_0402_5% RV72 0_0402_5%
Jason 5/29 AC17 TSVDD
DIS@
TSVSS

2
CV20 2 1 1U_0402_6.3V4Z VCCSENSE_VGA 1 EXO@ 2
DIS@ VSSSENSE_VGA RV161 1 EXO@ 2 10_0402_5% @
CV21 2 1 0.1U_0402_10V6K
2160856030-A0_FCBGA631
RV160 10_0402_5% RV84
10K_0402_5%
RV87
10K_0402_5% Boot-VID Code
RV21 1 EXO@ 2 10K_0402_5% ? DIS@
Voltage

1
TOPAZ Thermal Address-->0x82 SVC SVD
SVI2_SVD
Selected (V)
Enable MLPS SVI2_SVC
0 0 1.1
0 1 1.0

2
D D
+3VGS
@ RV88
1 0 0.9
RV89 10K_0402_5%
1 1 0.8
2

10K_0402_5% DIS@

1
@
RV91
10K_0402_5%
1

PCC_GPIO_6 1 2 OCP_L OCP_L <52>

2 RV90 @ 1K_0402_1%

Compal Electronics, Inc.

CVT90
0.1U_0402_10V7K 1
Security Classification Compal Secret Data
Peak Current Control (PCC) CKT Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title
EXO/MESO_MSIC
Reversed THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 57 of 64
1 2 3 4 5
 1 2 3 4 5

A A

@
UV1E U?

+1.35VS_VGA TO +1.35V_MEM_GFX +1.8VGS ShortPad

370mA (HDMI)
188mA (Display Port)
No Use GPU Display Port outpud AA27
AB24
AB32
GND
GND
GND
GND
A3
A30
AA13
@ AC24 GND GND AA16
1 2 AC26 GND GND AB10
JP9 DEFAULT SHORT
@ +DP_VDDR UV1G U?
RV27 0_0603_5% AC27 GND GND AB15
B
NC/DP POWER AD25 GND GND AB6 B

CV26

CV27

CV35
DP POWER
AD32 GND GND AC9
1 1 1 GND GND
AG15 AE11 AE27 AD6
DIS@ DIS@ DIS@ AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
DP_VDDR#AF16 NC#AE13 GND GND

1U_0402_6.3V4Z
2 2 2

10U_0603_6.3V6M

0.1U_0402_10V6K
AG17 AF13 AH32 AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
Short_pad DP_VDDR#AG18 NC#AG8 GND GND
RV27 AG19 AG10 K32 AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
RV30 DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+0.95VSDGPU ShortPad AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
1 @ 2 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
RV30 0_0603_5% DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1

CV30

CV33

CV34
W25 GND GND C32
1 1 1 GND GND
AG14 AE1 W26 E28
DIS@ DIS@ DIS@ AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
DP_VSSR NC#AG1 GND GND

1U_0402_6.3V4Z
2 2 2

10U_0603_6.3V6M

0.1U_0402_10V6K
AM16 AG6 Y32 F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND GND F8
C
DP_VSSR P6 GND GND G10 C
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
2160856030-A0_FCBGA631
? T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND

2160856030-A0_FCBGA631
?

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
EXO/MESO_Power/GND
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0(A00)
LA-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 58 of 64
1 2 3 4 5
 1 2 3 4 5

A A
+VGA_CORE 10uF 1uF 0.1uF

VDDC TBD 5 (1@) 10 (2@) 0 @

UV1D +1.8VGS
+1.35V_MEM_GFX
U?
100mA
AM30 +PCIE_PVDD
VDDCI 3.5A 1 3 0 1.5A MEM I/O PCIE_PVDD

PCIE

CV38

CV46

CV39
H13 AB23

0.01U_0402_16V7K CV179
VDDR1 NC#AB23 1 1 1 1
H16 AC23
H19 VDDR1 NC#AC23 AD24 DIS@ DIS@ DIS@ DIS@

CV43

CV44

CV45

CV40

CV47

CV48

CV41

CV42

CV49

CV50

CV51

CV52

CV53
J10 VDDR1 NC#AD24 AE24

0.01U_0402_16V7K CV174

0.01U_0402_16V7K CV175

0.01U_0402_16V7K CV176

0.01U_0402_16V7K CV177

0.01U_0402_16V7K CV178
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDR1 NC#AE24

1U_0402_6.3V4Z
2 2 2 2

10U_0603_6.3V6M

0.1U_0402_10V6K
J23 AE25
+0.95VSDGPU 10uF 1uF 0.1uF DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@
J24 VDDR1 NC#AE25 AE26
J9 VDDR1 NC#AE26 AF25

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
K10 AG26
K23 VDDR1 NC#AG26
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 0 1 0 L13 VDDR1 PCIE_VDDC L26
ShortPad
L20 VDDR1 PCIE_VDDC M22 RC364 +0.95VSDGPU
L21 VDDR1 PCIE_VDDC N22 2.5A 0_0603_5%
L22 VDDR1 PCIE_VDDC N23 +PCIE_VDDC 1 @ 2
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24

CV54

CV55

CV56

CV57

CV58

CV59

CV60

CV120

CV121
PCIE_VDDC R22 DIS@ => @
PCIE_VDDC 1 1 1 1 1 1 1 1 1
T22 Jason 6/25
+1.8VGS 13mA LEVEL PCIE_VDDC U22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
LV3 DIS@ TRANSLATION PCIE_VDDC V22

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
PCIE_VDDC 2 2 2 2 2 2 2 2 2

10U_0603_6.3V6M

10U_0603_6.3V6M
+1.35V_MEM_GFX 1 2 +VDD_CT AA20
10uF 2.2uF 0.1uF 0.01uF BLM15BD121SN1D_0402 AA21 VDD_CT
AB20 VDD_CT AA15

CV61

CV62

CV63
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 5 DIS@ DIS@ DIS@ +3VGS VDDC R13
LV4 DIS@ 25mA I/O VDDC R16
VDDC

1U_0402_6.3V4Z
2 2 2

10U_0603_6.3V6M

0.1U_0402_10V6K
1 2 +VDDR3 AA17 R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
AB17 VDDR3 VDDC T12

CV64

CV65

CV66
CV123
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 1 1 1 VDDR3 VDDC TBD
T17
DIS@ DIS@ DIS@ DIS@ V12 VDDC T20
Y12 VDDR4 VDDC U13

CV67

CV68

CV69

CV70

CV71

CV72

CV73

CV74

CV75

CV76

CV77

CV78

CV79

CV80
VDDR4 VDDC

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2

10U_0603_6.3V6M
U12 U16 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC U18
VDDC V21 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDDC V15
VDDC

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
V17
MPLL_PVDD 130mA 1 1 1 VDDC V20
VDDC Y13

POWER
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 CIS SYMBOL VDDC

CV101

CV104

CV100

CV106

CV103

CV109

CV102

CV107

CV108

CV105
+1.8VGS
130mA 1 1 1 1 1 1 1 1 1 1
LV6 DIS@ PLL
1 2 +MPLL_PVDD DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDD_CT 13mA 1 1 1 BLM15BD221SN1D_2P
CV81

CV82

CV124

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2
1 1 1 1.4A
R21
DIS@ DIS@ DIS@ BIF_VDDC U21 +BIF_VDDC
+TSVDD 13mA 1 1 1 BIF_VDDC
1U_0402_6.3V4Z

2 2 2
10U_0603_6.3V6M

0.1U_0402_10V6K

L8
C +1.8VGS MPLL_PVDD C
LV7 DIS@ 75mA
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O
BLM15BD121SN1D_0402 M13
CV84

CV85

CV86
H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16

CV111

CV114

CV110

CV117

CV113

CV118

CV112

CV116

CV119

CV115
+DP_VDDC 0 0 0 DIS@ DIS@ DIS@ VDDCI M17 1 1 1 1 1 1 1 1 1 1
+0.95VSDGPU VDDCI M18
100mA
1U_0402_6.3V4Z

2 2 2 VDDCI
10U_0603_6.3V6M

0.1U_0402_10V6K

LV8 DIS@ M20 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2 +SPLL_VDDC H8 VDDCI M21
SPLL_VDDC VDDCI

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
BLM15BD121SN1D_0402 N20 2 2 2 2 2 2 2 2 2 2

CV91

CV92

CV93
J7 VDDCI
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
DIS@ DIS@ DIS@

1U_0402_6.3V4Z
2 2 2

10U_0603_6.3V6M

0.1U_0402_10V6K
VDDR3 25mA 0 2 (1@) 1 2160856030-A0_FCBGA631
?

ShortPad +0.95VSDGPU

+BIF_VDDC 1 @ 2
RV31 0_0805_5%
+VGA_CORE

CV122

CV171

CV168
1 2 2
3.5A (DDR3)
DIS@ DIS@ DIS@

CV88

CV89

CV90

CV87
1 1 1 1

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 1 1

10U_0603_6.3V6M
DIS@ DIS@ DIS@ DIS@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2

10U_0603_6.3V6M
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
EXO/MESO_Power
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0(A00)
LA-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 59 of 64
1 2 3 4 5
 1 2 3 4 5

M_DA[63..0]
<61,62> M_DA[63..0]
M_MA[15..0]
<61,62> M_MA[15..0]
M_DQM[7..0]
<61,62> M_DQM[7..0]
M_DQS[7..0]
<61,62> M_DQS[7..0]
A A
M_DQS#[7..0]
<61,62> M_DQS#[7..0]

@
UV1C U?

GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1

1
M_DA11 C28 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
DIS@ DIS@ M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
DQA0_15 MAA1_4/MAA_12
2

M_DA16 A25 G11 M_BA2

+MVREFDA +MVREFSA M_DA17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 M_BA0 M_BA2 <61,62>
E25 DQA0_17 MAA1_6/MAA_BA0 L15 M_BA0 <61,62>
M_DA18 M_BA1
M_DA19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 M_MA14 M_BA1 <61,62>
DQA0_19 MAA1_8/MAA_14
1

1 1 M_DA20 E23 L16

DQA0_20 MAA1_9/RSVD

MEMORY INTERFACE
M_DA21 F23
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1 +1.35V_MEM_GFX
DIS@ 2 DIS@ DIS@ 2 DIS@ M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
DQA0_24 WCKA0_1/DQMA0_2
2

M_DA25 D20 C21 M_DQM3

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4 RV136 1 DIS@ 2 100_0402_1% M_MA0 100_0402_1% 1 DIS@ 2 RV137
B
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 RV138 1 DIS@ 2 100_0402_1% M_MA1 100_0402_1% 1 DIS@ 2 RV139
B

M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6 RV140 1 DIS@ 2 100_0402_1% M_MA2 100_0402_1% 1 DIS@ 2 RV141
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7 RV142 1 DIS@ 2 100_0402_1% M_MA3 100_0402_1% 1 DIS@ 2 RV143
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3 RV144 1 DIS@ 2 100_0402_1% M_MA4 100_0402_1% 1 DIS@ 2 RV145
M_DA31 C17 DQA0_30 H28 M_DQS0 RV199 1 DIS@ 2 100_0402_1% M_MA5 100_0402_1% 1 DIS@ 2 RV150
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1 RV200 1 DIS@ 2 100_0402_1% M_MA6 100_0402_1% 1 DIS@ 2 RV166
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2 RV205 1 DIS@ 2 100_0402_1% M_MA7 100_0402_1% 1 DIS@ 2 RV167
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3 RV206 1 DIS@ 2 100_0402_1% M_MA8 100_0402_1% 1 DIS@ 2 RV168
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 RV207 1 DIS@ 2 100_0402_1% M_MA9 100_0402_1% 1 DIS@ 2 RV169
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_DQS5 RV213 1 DIS@ 2 100_0402_1% M_MA10 100_0402_1% 1 DIS@ 2 RV170
M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6 RV214 1 DIS@ 2 100_0402_1% M_MA11 100_0402_1% 1 DIS@ 2 RV171
RV36 DIS@ RV37 DIS@ M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7 RV215 1 DIS@ 2 100_0402_1% M_MA12 100_0402_1% 1 DIS@ 2 RV172
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3 RV216 1 DIS@ 2 100_0402_1% M_MA13 100_0402_1% 1 DIS@ 2 RV173
1 2 2 1 DRAM_RST_G M_DA40 E11 DQA1_7 H27 M_DQS#0 RV221 1 DIS@ 2 100_0402_1% M_MA14 100_0402_1% 1 DIS@ 2 RV174
<61,62> DRAM_RST A11 DQA1_8 DDBIA0_0/QSA0_0B A27 RV222 1 DIS@ 2 100_0402_1% 100_0402_1% 1 DIS@ 2 RV175
M_DA41 M_DQS#1 M_MA15
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
DQA1_10 DDBIA0_2/QSA0_2B
1

1 1 M_DA43 F11 C19 M_DQS#3

@ M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4 RV223 1 DIS@ 2 100_0402_1% M_BA0 100_0402_1% 1 DIS@ 2 RV176
CV96 RV38 CV97 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5 RV224 1 DIS@ 2 100_0402_1% M_BA1 100_0402_1% 1 DIS@ 2 RV177
120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6 RV225 1 DIS@ 2 100_0402_1% M_BA2 100_0402_1% 1 DIS@ 2 RV178
DIS@ 2 DIS@ 2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
DQA1_15 DDBIA1_3/QSA1_3B
2

M_DA48 E7
M_DA49 A7 DQA1_16 L18 VRAM_ODT0 RV179 1 DIS@ 2 100_0201_1% VRAM_ODT0100_0201_1% 1 DIS@ 2 RV184
M_DA50 C7 DQA1_17 ADBIA0/ODTA0 K16 VRAM_ODT1 VRAM_ODT0 <61,62> RV185 1 DIS@ 2 100_0201_1% VRAM_ODT1100_0201_1% 1 DIS@ 2 RV186
F7 DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <61,62>
M_DA51
M_DA52 A5 DQA1_19 H26 M_CLK0
E5 DQA1_20 CLKA0 H25 M_CLK0 <61,62> RV187 1 DIS@ 2 100_0201_1% 100_0201_1% 1 DIS@ 2 RV189
M_DA53 M_CLK#0 M_RAS#0
M_DA54 C3 DQA1_21 CLKA0B M_CLK#0 <61,62> RV188 1 DIS@ 2 100_0201_1% M_RAS#1 100_0201_1% 1 DIS@ 2 RV190
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 <61,62>
and place componment close to each other M_DA57 G6 DQA1_24 CLKA1B M_CLK#1 <61,62> RV191 1 DIS@ 2 100_0201_1% M_CAS#0 100_0201_1% 1 DIS@ 2 RV194
M_DA58 G1 DQA1_25 G22 M_RAS#0 RV192 1 DIS@ 2 100_0201_1% M_CAS#1 100_0201_1% 1 DIS@ 2 RV193
M_DA59 G3 DQA1_26 RASA0B G17 M_RAS#1 M_RAS#0 <61,62>
M_DA60 J6 DQA1_27 RASA1B M_RAS#1 <61,62>
C M_DA61 J1 DQA1_28 G19 M_CAS#0 RV208 1 DIS@ 2 100_0201_1% M_CS0B#0 100_0201_1% 1 DIS@ 2 RV212 C
M_DA62 J3 DQA1_29 CASA0B G16 M_CAS#1 M_CAS#0 <61,62> RV210 1 DIS@ 2 100_0201_1% M_CS1B#0 100_0201_1% 1 DIS@ 2 RV211
J5 DQA1_30 CASA1B M_CAS#1 <61,62>
M_DA63
DQA1_31 H22 M_CS0B#0
+MVREFDA K26 CSA0B_0 J22 M_CS0B#1 M_CS0B#0 <61> RV217 1 DIS@ 2 100_0201_1% M_CS0B#1 100_0201_1% 1 DIS@ 2 RV219
J26 MVREFDA CSA0B_1 M_CS0B#1 <62> RV218 1 DIS@ 2 100_0201_1% 1 DIS@ 2 RV220
+MVREFSA M_CS1B#1 100_0201_1%
MVREFSA G13 M_CS1B#0
J25 CSA1B_0 K13 M_CS1B#0 <61>
M_CS1B#1
RV39 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1 M_CS1B#1 <62> RV195 1 DIS@ 2 100_0201_1% M_CKE0 100_0201_1% 1 DIS@ 2 RV198
MEM_CALRP0 K20 M_CKE0 RV196 1 DIS@ 2 100_0201_1% M_CKE1 100_0201_1% 1 DIS@ 2 RV197
CKEA0 J17 M_CKE0 <61,62>
M_CKE1
CKEA1 M_CKE1 <61,62>
G25 M_WE#0 RV201 1 DIS@ 2 100_0201_1% M_WE#0 100_0201_1% 1 DIS@ 2 RV203
DRAM_RST_G L10 WEA0B H10 M_WE#1 M_WE#0 <61,62> RV202 1 DIS@ 2 100_0201_1% M_WE#1 100_0201_1% 1 DIS@ 2 RV204
DRAM_RST WEA1B M_WE#1 <61,62>
RV40 @ 1 2 51.1_0402_1% CV98 @1 2 0.1U_0402_16V4Z K8
RV41 @ 1 2 51.1_0402_1% CV99 @1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short
2160856030-A0_FCBGA631
debug only, for clock observation,if not need, DNI. ?

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
EXO/MESO_MEM
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0(A00)
LA-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 60 of 64
1 2 3 4 5
 1 2 3 4 5

M_DA[63..0] Reduce Vref Circuit

<60,62> M_DA[63..0] for Spacing saving. UV15 @ UV12 @ UV13 @ UV14 @
M_MA[15..0]
<60,62> M_MA[15..0] VREFCA_UV3 M8 E3 M_DA19 VREFCA_UV4 M8 E3 M_DA10 VREFCA_UV5 M8 E3 M_DA52 VREFCA_UV6 M8 E3 M_DA42
M_DQM[7..0] VREFCA_UV7 H1 VREFCA DQL0 F7 M_DA16 VREFDQ_UV4 H1 VREFCA DQL0 F7 M_DA12 VREFDQ_UV5 H1 VREFCA DQL0 F7 M_DA54 VREFDQ_UV6 H1 VREFCA DQL0 F7 M_DA47
<60,62> M_DQM[7..0] VREFDQ DQL1 F2 M_DA23 VREFDQ DQL1 F2 M_DA8 VREFDQ DQL1 F2 M_DA48 VREFDQ DQL1 F2 M_DA41
M_DQS[7..0] M_MA0 N3 DQL2 F8 M_DA17 M_MA0 N3 DQL2 F8 M_DA13 M_MA0 N3 DQL2 F8 M_DA51 M_MA0 N3 DQL2 F8 M_DA45
<60,62> M_DQS[7..0] M_MA1 P7 A0 DQL3 H3 M_DA18 M_MA1 P7 A0 DQL3 H3 M_DA11 M_MA1 P7 A0 DQL3 H3 M_DA50 M_MA1 P7 A0 DQL3 H3 M_DA40
M_DQS#[7..0] M_MA2 P3 A1 DQL4 H8 M_DA21 M_MA2 P3 A1 DQL4 H8 M_DA14 M_MA2 P3 A1 DQL4 H8 M_DA53 M_MA2 P3 A1 DQL4 H8 M_DA46
<60,62> M_DQS#[7..0] M_MA3 N2 A2 DQL5 G2 M_DA20 M_MA3 N2 A2 DQL5 G2 M_DA9 M_MA3 N2 A2 DQL5 G2 M_DA49 M_MA3 N2 A2 DQL5 G2 M_DA43
M_MA4 P8 A3 DQL6 H7 M_DA22 M_MA4 P8 A3 DQL6 H7 M_DA15 M_MA4 P8 A3 DQL6 H7 M_DA55 M_MA4 P8 A3 DQL6 H7 M_DA44
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
VREFCA_UV7 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
<62> VREFCA_UV7 M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA28 M_MA7 R2 A6 D7 M_DA62 M_MA7 R2 A6 D7 M_DA38
A M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA27 M_MA8 T8 A7 DQU0 C3 M_DA56 M_MA8 T8 A7 DQU0 C3 M_DA35 A
Reduce Vref Circuit for Spacing saving. M_MA9 R3 A8 DQU1 C8 M_DA7 M_MA9 R3 A8 DQU1 C8 M_DA31 M_MA9 R3 A8 DQU1 C8 M_DA63 M_MA9 R3 A8 DQU1 C8 M_DA37
M_MA10 L7 A9 DQU2 C2 M_DA0 M_MA10 L7 A9 DQU2 C2 M_DA24 M_MA10 L7 A9 DQU2 C2 M_DA59 M_MA10 L7 A9 DQU2 C2 M_DA34
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA29 M_MA11 R7 A10/AP DQU3 A7 M_DA61 M_MA11 R7 A10/AP DQU3 A7 M_DA36
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA25 M_MA12 N7 A11 DQU4 A2 M_DA58 M_MA12 N7 A11 DQU4 A2 M_DA32
M_MA13 T3 A12 DQU5 B8 M_DA6 M_MA13 T3 A12 DQU5 B8 M_DA30 M_MA13 T3 A12 DQU5 B8 M_DA60 M_MA13 T3 A12 DQU5 B8 M_DA39
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA26 M_MA14 T7 A13 DQU6 A3 M_DA57 M_MA14 T7 A13 DQU6 A3 M_DA33
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX

M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<60,62> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<60,62> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<60,62> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<60,62> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <60,62> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<60,62> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <60,62> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<60,62> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX <60,62> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX

VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<60,62> VRAM_ODT0 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 <60,62> VRAM_ODT1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<60> M_CS0B#0 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <60> M_CS1B#0 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<60,62> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <60,62> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<60,62> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <60,62> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<60,62> M_WE#0 WE VDDQ E9 WE VDDQ E9 <60,62> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS6 F3 VDDQ H2 M_DQS5 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM6 E7 A9 M_DQM5 E7 A9

M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM7 D3 DML VSS B3 M_DQM4 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
B VSS VSS VSS VSS B
G8 G8 G8 G8
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#6 G3 VSS J2 M_DQS#5 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#7 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<60,62> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV102 J9 NC/CS1 VSSQ D1 RV103 J9 NC/CS1 VSSQ D1 RV108 J9 NC/CS1 VSSQ D1 RV104 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
DIS@ NCZQ1 VSSQ E2 DIS@ NCZQ1 VSSQ E2 DIS@ NCZQ1 VSSQ E2 DIS@ NCZQ1 VSSQ E2
VSSQ VSSQ VSSQ VSSQ
2

2
E8 E8 E8 E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
M_CLK0 RV109 1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
80.6_0402_1% VSSQ VSSQ M_CLK1 RV98 1 2 VSSQ VSSQ
96-BALL 96-BALL 80.6_0402_1% 96-BALL 96-BALL
M_CLK#0RV105 1 DIS@ 2 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
DIS@
80.6_0402_1% H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96 M_CLK#1RV99 1 2 H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
DIS@ 1 80.6_0402_1%
CV206 DIS@ 1
.01U_0402_16V7-K CV247
DIS@ .01U_0402_16V7-K
2 DIS@
2

C C

+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX

1

.1U_0402_16V7K
CV210

.1U_0402_16V7K
CV260

.1U_0402_16V7K
CV246

.1U_0402_16V7K
CV262

.1U_0402_16V7K
CV254

.1U_0402_16V7K
CV245

.1U_0402_16V7K
CV207

.1U_0402_16V7K
CV259

.1U_0402_16V7K
CV248

.1U_0402_16V7K
CV244

.1U_0402_16V7K
CV214

.1U_0402_16V7K
CV165

.1U_0402_16V7K
CV211

.1U_0402_16V7K
CV251

.1U_0402_16V7K
CV239

.1U_0402_16V7K
CV238

10U_0603_6.3V6M
CV240

10U_0603_6.3V6M
CV208

10U_0603_6.3V6M
CV258

10U_0603_6.3V6M
CV249
RV100 RV101 RV239 RV238 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6
1

1 1 1 1
RV106 CV209 RV107 CV216 RV237 CV237 RV244 CV242
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 +1.35V_MEM_GFX
2

1U_0402_6.3V6K
CV257

1U_0402_6.3V6K
CV217

1U_0402_6.3V6K
CV204

1U_0402_6.3V6K
CV223

1U_0402_6.3V6K
CV205

1U_0402_6.3V6K
CV241

1U_0402_6.3V6K
CV243

1U_0402_6.3V6K
CV250

1U_0402_6.3V6K
CV213

1U_0402_6.3V6K
CV253

10U_0603_6.3V6M
CV256

1U_0402_6.3V6K
CV261

1U_0402_6.3V6K
CV215

1U_0402_6.3V6K
CV222

1U_0402_6.3V6K
CV221

1U_0402_6.3V6K
CV212
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1

RV245 RV246 RV241

4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
D
DIS@ DIS@ DIS@ D
2

Reduce Vref Circuit for Spacing saving. VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6

VREFDQ_UV3 Share with VREFCA_UV7
1

1 1 1
RV243 CV263 RV235 CV236 RV242 CV252
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
VRAM A Lower Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSCustom
LA-D071P
1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 61 of 64
1 2 3 4 5
 1 2 3 4 5

M_DA[63..0]
<60,61> M_DA[63..0]
Reduce Vref Circuit
M_MA[15..0] UV19 @ for Spacing saving. UV17 @ UV16 @ UV18 @
<60,61> M_MA[15..0]
M_DQM[7..0] VREFCA_UV7 M8 E3 M_DA16 VREFCA_UV8 M8 E3 M_DA12 VREFCA_UV9 M8 E3 M_DA54 VREFCA_UV10 M8 E3 M_DA45
<60,61> M_DQM[7..0] VREFDQ_UV7 H1 VREFCA DQL0 F7 M_DA19 VREFCA_UV7 H1 VREFCA DQL0 F7 M_DA10 VREFDQ_UV9 H1 VREFCA DQL0 F7 M_DA52 VREFDQ_UV10 H1 VREFCA DQL0 F7 M_DA42
M_DQS[7..0] VREFDQ DQL1 F2 M_DA17 VREFDQ DQL1 F2 M_DA13 VREFDQ DQL1 F2 M_DA51 VREFDQ DQL1 F2 M_DA46
<60,61> M_DQS[7..0] M_MA0 N3 DQL2 F8 M_DA23 M_MA0 N3 DQL2 F8 M_DA8 M_MA0 N3 DQL2 F8 M_DA48 M_MA0 N3 DQL2 F8 M_DA41
M_DQS#[7..0] M_MA1 P7 A0 DQL3 H3 M_DA22 M_MA1 P7 A0 DQL3 H3 M_DA14 M_MA1 P7 A0 DQL3 H3 M_DA55 M_MA1 P7 A0 DQL3 H3 M_DA44
<60,61> M_DQS#[7..0] M_MA2 P3 A1 DQL4 H8 M_DA20 M_MA2 P3 A1 DQL4 H8 M_DA11 M_MA2 P3 A1 DQL4 H8 M_DA49 M_MA2 P3 A1 DQL4 H8 M_DA43
M_MA3 N2 A2 DQL5 G2 M_DA21 M_MA3 N2 A2 DQL5 G2 M_DA15 M_MA3 N2 A2 DQL5 G2 M_DA53 M_MA3 N2 A2 DQL5 G2 M_DA47
M_MA4 P8 A3 DQL6 H7 M_DA18 M_MA4 P8 A3 DQL6 H7 M_DA9 M_MA4 P8 A3 DQL6 H7 M_DA50 M_MA4 P8 A3 DQL6 H7 M_DA40
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
VREFCA_UV7 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
A
<61> VREFCA_UV7 M_MA7 R2 A6 D7 M_DA3 M_MA7 R2 A6 D7 M_DA27 M_MA7 R2 A6 D7 M_DA56 M_MA7 R2 A6 D7 M_DA35 A
M_MA8 T8 A7 DQU0 C3 M_DA5 M_MA8 T8 A7 DQU0 C3 M_DA28 M_MA8 T8 A7 DQU0 C3 M_DA62 M_MA8 T8 A7 DQU0 C3 M_DA38
Reduce Vref Circuit for Spacing saving. M_MA9 R3 A8 DQU1 C8 M_DA0 M_MA9 R3 A8 DQU1 C8 M_DA24 M_MA9 R3 A8 DQU1 C8 M_DA59 M_MA9 R3 A8 DQU1 C8 M_DA34
M_MA10 L7 A9 DQU2 C2 M_DA7 M_MA10 L7 A9 DQU2 C2 M_DA31 M_MA10 L7 A9 DQU2 C2 M_DA63 M_MA10 L7 A9 DQU2 C2 M_DA37
M_MA11 R7 A10/AP DQU3 A7 M_DA2 M_MA11 R7 A10/AP DQU3 A7 M_DA26 M_MA11 R7 A10/AP DQU3 A7 M_DA57 M_MA11 R7 A10/AP DQU3 A7 M_DA33
M_MA12 N7 A11 DQU4 A2 M_DA6 M_MA12 N7 A11 DQU4 A2 M_DA30 M_MA12 N7 A11 DQU4 A2 M_DA60 M_MA12 N7 A11 DQU4 A2 M_DA39
M_MA13 T3 A12 DQU5 B8 M_DA1 M_MA13 T3 A12 DQU5 B8 M_DA25 M_MA13 T3 A12 DQU5 B8 M_DA58 M_MA13 T3 A12 DQU5 B8 M_DA32
M_MA14 T7 A13 DQU6 A3 M_DA4 M_MA14 T7 A13 DQU6 A3 M_DA29 M_MA14 T7 A13 DQU6 A3 M_DA61 M_MA14 T7 A13 DQU6 A3 M_DA36
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX

M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2

<60,61> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<60,61> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<60,61> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<60,61> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <60,61> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<60,61> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <60,61> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<60,61> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX <60,61> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX

VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1

<60,61> VRAM_ODT0 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 <60,61> VRAM_ODT1 M_CS1B#1 L2 ODT/ODT0 VDDQ A8 M_CS1B#1 L2 ODT/ODT0 VDDQ A8
<60> M_CS0B#1 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <60> M_CS1B#1 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<60,61> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <60,61> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<60,61> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <60,61> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<60,61> M_WE#0 WE VDDQ E9 WE VDDQ E9 <60,61> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS6 F3 VDDQ H2 M_DQS5 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM6 E7 A9 M_DQM5 E7 A9

M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM7 D3 DML VSS B3 M_DQM4 D3 DML VSS B3
B DMU VSS DMU VSS DMU VSS DMU VSS B
E1 E1 E1 E1
VSS G8 VSS G8 VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#6 G3 VSS J2 M_DQS#5 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#7 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<60,61> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV118 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1 RV117 J9 NC/CS1 VSSQ D1 RV114 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
V_4G@ NCZQ1 VSSQ E2 V_4G@ NCZQ1 VSSQ E2 V_4G@ NCZQ1 VSSQ E2 V_4G@ NCZQ1 VSSQ E2
VSSQ VSSQ VSSQ VSSQ
2

2
E8 E8 E8 E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
M_CLK0 RV95 1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
80.6_0402_1% VSSQ VSSQ M_CLK1 RV116 1 2 VSSQ VSSQ
V_4G@ 96-BALL 96-BALL 80.6_0402_1% 96-BALL 96-BALL
M_CLK#0RV111 1 2 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
80.6_0402_1% H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96 M_CLK#1RV112 1 V_4G@ 2 H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
V_4G@ 1 80.6_0402_1%
CV271 V_4G@ 1
.01U_0402_16V7-K CV279
V_4G@ .01U_0402_16V7-K
2 V_4G@
2

C C

+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX

1

RV96 This circuit is share with 3pcs VRAM. RV113 RV234 RV258
4.99K_0402_1% Please keep stuff when DIS@. 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ V_4G@ V_4G@ V_4G@
+1.35V_MEM_GFX +1.35V_MEM_GFX
2

VREFCA_UV7 VREFCA_UV8 VREFCA_UV9 VREFCA_UV10

1

.1U_0402_16V7K
CV288

.1U_0402_16V7K
CV281

.1U_0402_16V7K
CV285

.1U_0402_16V7K
CV274

.1U_0402_16V7K
CV229

.1U_0402_16V7K
CV224

.1U_0402_16V7K
CV278

.1U_0402_16V7K
CV294

.1U_0402_16V7K
CV269

.1U_0402_16V7K
CV302

.1U_0402_16V7K
CV266

.1U_0402_16V7K
CV287

.1U_0402_16V7K
CV228

.1U_0402_16V7K
CV268

.1U_0402_16V7K
CV272

.1U_0402_16V7K
CV296

10U_0603_6.3V6M
CV282

10U_0603_6.3V6M
CV301

10U_0603_6.3V6M
CV276

10U_0603_6.3V6M
CV292
1 1 1 1
RV115 CV298 RV97 CV300 RV251 CV264 RV248 CV275 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
2 2 2 2
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@

+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX

1

1U_0402_6.3V6K
CV295

1U_0402_6.3V6K
CV299

1U_0402_6.3V6K
CV227

1U_0402_6.3V6K
CV277

1U_0402_6.3V6K
CV270

1U_0402_6.3V6K
CV283

1U_0402_6.3V6K
CV291

1U_0402_6.3V6K
CV289

1U_0402_6.3V6K
CV290

1U_0402_6.3V6K
CV297

10U_0603_6.3V6M
CV284

1U_0402_6.3V6K
CV303

1U_0402_6.3V6K
CV225

1U_0402_6.3V6K
CV280

1U_0402_6.3V6K
CV226

1U_0402_6.3V6K
CV286
RV252 RV256 RV247 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
V_4G@ V_4G@ V_4G@
D D
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VREFDQ_UV7 Reduce Vref Circuit for Spacing saving. VREFDQ_UV9 VREFDQ_UV10
VREFDQ_UV8 Share with VREFCA_UV7
1

1 1 1
RV249 CV265 RV253 CV293 RV259 CV273 V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
2 2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/09 Deciphered Date 2016/07/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
VRAM A Upper Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSCustom
LA-D071P
1.0(A00)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 09, 2015 Sheet 62 of 64
1 2 3 4 5
 5 4 3 2 1

Power-Up/Down Sequence 1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μs.
2. It is recommended that the 3.3-V rail ramp up first.
3. It is recommended that the 0.95-V rail reach at least 90% of its nominal value
no later than 2 ms from the start of VDDC ramping up.
4. The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress? idle state), all the power rails are removed from the dGPU.
D The gate circuits must meet the slew rate requirement (such as ? 50 mV/μs). D

5. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).

6. For power down, reversing the ramp-up sequence is recommended.

PCH_PLTRST#
AND PCH_PLTRST#_EC
GPU
GPP_B13
< 20mS < 20mS
MCP GATE AND PLT_RST_VGA# PERSTB
GATE
VDDR3(3.3V)
+3VGS >10uS
DGPU_HOLD_RST#
(DGPU_PWR_EN) GPP_D10
PCIE_VDDC(0.95V) GPP_D13 DGPU_PWR_EN
+0.95VSDGPU
(DGPU_PWR_EN with RC delay) DGPU_PWROK
GPP_D18
1.8V_IO(1.8V)
+1.8VGS
(DGPU_PWR_EN with RC delay)
VDDC/VDDCI(0.8~1.15V)
+VGA_CORE
(DGPU_PWR_EN)
VMEMIO(1.35V or 1.5V) +3VS +3VGS
C
+1.35V_MEM_GFX > 100mS > 100mS (SW) C

(DGPU_PWROK with RC delay) DGPU_PWR_EN#

LDO 1
PWRGOOD
DGPU_PWROK
+1.0V_PRIM +0.95VSDGPU +1.8V_PRIM +1.8VGS
PERSTb
> 100uS
DGPU_PWR_EN#
LDO 2 DGPU_PWR_EN#
LDO 2
PLT_RST_VGA# Asserted Before PERSTb

REFCLK B+ +VGA_CORE +1.35V_MEM +1.35V_MEM_GFX

CLK_PEG_VGA/CLK_PEG_VGA# DGPU_PWR_EN#
PWM 3 DGPU_PWROK
LDO 3
DEVICE
Device in Device Hardware Reset Device CFG Accessible Device Powering down Device Powered down
Reset or Working

No requirements

ZZZ ZZZ ZZZ

X7662631L81 X7662631L82 X7662631L83

2G_S@ 2G_H@ 2G_M@

ALT. GROUP PARTS SAMSUNG 2GB AAL25 ALT. GROUP PARTS HYNIX 2GB AAL25 ALT. GROUP PARTS MICRON 2GB AAL25

ZZZ ZZZ ZZZ

B Hynix 1G Micron 1G X7662631L84 X7662631L85 X7662631L86 B

4G_S@ 4G_H@ 4G_M@

RV15 1G_H@ RV16 1G_H@ RV15 1G_M@ RV16 1G_M@
ALT. GROUP PARTS SAMSUNG 4GB AAL25 ALT. GROUP PARTS HYNIX 4GB AAL25 ALT. GROUP PARTS MICRON 4GB AAL25

8.45K_0402_1% 2K_0402_1% 4.53K_0402_1% 2K_0402_1% For AMD EXO-XT VRAM Only

SD000000680 SD034200180 SD034453180 SD034200180 Memory ID P/N Vendor Configuration Size

Samsung 2G Hynix 2G Micron 2G 000 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 4GB

RV15 2G_S@ RV16 2G_S@ RV15 2G_H@ RV16 2G_H@ RV15 2G_M@ RV16 2G_M@ 110 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 4GB
111 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 4GB

6.98K_0402_1% 4.99K_0402_1% 4.53K_0402_1% 4.99K_0402_1% 3.24K_0402_1% 5.62K_0402_1% 011 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 2GB
SD000002680 SD034499180 SD034453180 SD034499180 SD034324180 SD034562180
100 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 2GB
Samsung 4G Hynix 4G Micron 4G 101 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 2GB
RV16 4G_S@ RV15 4G_H@ RV16 4G_H@ RV15 4G_M@
For AMD MESO-LE VRAM Only
Memory ID P/N Vendor Configuration Size

4.75K_0402_1% 3.4K_0402_1% 10K_0402_1% 4.75K_0402_1% 011 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 2GB
A A
SD034475180 SD034340180 SD034100280 SD034475180
100 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 2GB
2015/5/19 Modify
Jason 101 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 2GB

Security Classification
2015/07/09
Compal Secret Data
2016/07/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO_NOTE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 63 of 64
5 4 3 2 1
 5 4 3 2 1

+5VALW TO +5V_3DCAM
+5VALW +5V_CAM
J14
Always Open
1 1 2 1

0.1U_0402_10V6K
J14 PJP@

12P_0402_50V8J
1U_0402_6.3V6K
1 2

12P_0402_50V8J
CX12

CX1
@RF@ 3D@ 3D@ @RF@

CX2

CX13
D D
1 2
2 2 JUMP_43X39 1 2
+3VS
RX1 1 @3D@ 2 10K_0402_5% UX1 3D@

+3VALW_PCH 1 7
RX2 1 3D@ 2 10K_0402_5% 2 VIN VOUT 8
VIN VOUT
3 6
<9,29> 3D_CAM_EN ON CT
1

1
RX3 4 3D@ CX3
100K_0402_5% 3D@ VBIAS 5 2200P_0402_25V7K
GND 9 2
GND

2
CT pin use 2200pf for
TPS22967DSGR_SON8_2X2
soft start tuning
For Test,
APE8937(SA000070L00)
AOZ1336(SA00006U600)
+3VS RX4 1 @EMI@ 2 0_0402_5% TPS22967(SA000070S00)

3D@ USB3.0 90ohm (Used 2nd Symbol & Footprint)

0.01U_0402_16V7K 1 2 CX4 LX1 3D@EMI@ Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP)
4 1
1 2 CX5 4 1 2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
0.1U_0402_10V6K Change RX5 BOM option.
UX2 3D@ Jason 7/6 3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)
C 3D@ 1 7 RX5 1 3D@ 2 4.99K_0402_1% 3 2 +5V_CAM C
13 VCC NC 24 RX6 1 @3D@ 2 0_0402_5% 3 2
3D@ VCC NC MCF12102G900-T_4P JCAM3D
CX6 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_N3 11 20 USB3_CRX_RD_DTX_N3 CONN@
<10> USB3_CRX_DTX_N3 CX7 1 2 0.1U_0402_10V6K USB3_CRX_C_RD_DTX_P3 12 TX2- RX2- 19 USB3_CRX_RD_DTX_P3 RX7 1 @EMI@ 2 0_0402_5% 1
<10> USB3_CRX_DTX_P3 TX2+ RX2+ USB3_CRX_L_DTX_N3 USB3_CRX_L_DTX_N3 2 1
3D@ USB3_OS2_P0 15 USB3_CRX_L_DTX_P3 USB3_CRX_L_DTX_P3 3 2
USB3_DE2_P0 16 OS2 5 USB3_ERD_P0 USB3_CTX_L_DRX_N3 4 3
USB3_EQ2_P0 17 DE2 EN_RXD 14 USB3_CM_P0 USB3_CTX_L_DRX_P3 USB3_CTX_L_DRX_N3 5 4
3D@ EQ2 CM 3D@ USB3_CTX_L_DRX_P3 6 5
CX8 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_N3 8 23 USB3_CTX_RD_DRX_N3 CX11 1 2 0.1U_0402_10V6K 7 6
<10> USB3_CTX_DRX_N3 RX1- TX1- 7
CX10 1 2 0.1U_0402_10V6K USB3_CTX_C_RD_DRX_P3 9 22 USB3_CTX_RD_DRX_P3 CX9 1 2 0.1U_0402_10V6K RX9 1 @EMI@ 2 0_0402_5% 8
<10> USB3_CTX_DRX_P3 RX1+ TX1+ 9 8
3D@ USB3_OS1_P0 4 3D@ LX2 3D@EMI@ 10 9
USB3_DE1_P0 3 OS1 6 USB3_P0_PIN6 USB3_CTX_C_DRX_N3 3 2 11 10
USB3_EQ1_P0 2 DE1 GND 10 3 2 12 GND
EQ1 GND 18 USB3_P0_PIN18 GND
25 GND 21 USB3_CTX_C_DRX_P3 4 1
PGND GND 4 1
MCF12102G900-T_4P ACES_50463-0104A-001
CAM_DETECT
PS8713BTQFN24GTR2-A0_TQFN24_4X4 RX8 1 @EMI@ 2 0_0402_5% <9> CAM_DETECT
USB3.0 90ohm
Main SA00005OR20 (S IC PS8713BTQFN24GTR2-A1 TQFN USB3.0) PARADE USB3.0 90ohm (Used 2nd Symbol & Footprint)
+3VS 2nd SA00008M500 (S IC SN65LVPE512RGER VQFN 24P USB3 REDRI) TI Main SM070003V00(S COM FI_ INPAQ HCM1012GH900BP) +3VS
2nd SM070004000(S COM FI_ TAIYO MCF12102G900-T)
Change Main source CPN to RX10 1 @3D@ 2 10K_0402_5%
3rd SM070004300(S COM FI_ PANASONIC EXC24CH900U)
SA00005OR30 (S IC PS8713BTQFN24GTR2-A2 USB3.0 REPEATE) PARADE +3VALW_PCH
RX11 1 @3D@ 2 3.3K_0402_5%
Because Vendor Ver. change. Jason 2015/5/29
B RX12 1 @3D@ 2 0_0402_5% USB3_P0_PIN6 RX13 1 3D@ 2 10K_0402_5% B

Layout request to swap pin ! <9,29> FW_UPDATE

FW_UPDATE
RX14 1 @3D@ 2 3.3K_0402_5%
RX15 1 @3D@ 2 0_0402_5% USB3_P0_PIN18

DX1 @ESD@
RX16 1 @3D@ 2 4.7K_0402_5% USB3_CRX_L_DTX_P3 1 10 USB3_CRX_L_DTX_P3
RX17 1 @3D@ 2 4.7K_0402_5% USB3_CM_P0
USB3_CRX_L_DTX_N3 2 9 USB3_CRX_L_DTX_N3

RX18 1 @3D@ 2 4.7K_0402_5% USB3_CTX_L_DRX_N3 4 7 USB3_CTX_L_DRX_N3

RX19 1 @3D@ 2 4.7K_0402_5% USB3_ERD_P0
USB3_CTX_L_DRX_P3 5 6 USB3_CTX_L_DRX_P3

RX20 1 @3D@ 2 4.7K_0402_5% 3

RX21 1 @3D@ 2 4.7K_0402_5% USB3_OS2_P0
8

RX22 1 @3D@ 2 4.7K_0402_5% S DIO(BR) TVWDF1004AD0 DFN ESD

RX23 1 @3D@ 2 4.7K_0402_5% USB3_DE2_P0

RX24 1 @3D@ 2 4.7K_0402_5%

RX25 1 @3D@ 2 4.7K_0402_5% USB3_EQ2_P0

RX26 1 @3D@ 2 4.7K_0402_5%

RX27 1 @3D@ 2 4.7K_0402_5% USB3_OS1_P0
A A

RX28 1 @3D@ 2 4.7K_0402_5%

RX29 1 @3D@ 2 4.7K_0402_5% USB3_DE1_P0

RX30 1 @3D@ 2 4.7K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.
RX31 1 @3D@ 2 4.7K_0402_5% USB3_EQ1_P0 2015/07/09 2016/07/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3D CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0(A00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D071P
Date: Thursday, July 09, 2015 Sheet 64 of 64
5 4 3 2 1