This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2623353, IEEE
Transactions on Power Electronics

A Synchronous Buck DC-DC Converter Using a

Novel Dual-Mode Control Scheme to Improve
Efficiency
Jian-Min Wang, Member, IEEE and Sen-Tung Wu


Abstract—A novel dual-mode control scheme is developed here Coss1
to enable synchronous buck con verters (S BC) to operate in a Iin iL IO
continuous conduction mode under heavy-load conditions and in a D1
discontinuous conduction mode under light-load conditions. MA L
When an S BC operates in a discontinuous conduction mode, a MB
VDC VGS1 CO RO
quasi-resonant valley switching technique can be employed to VO
Coss2
turn on a synchronous switch, perform zero-voltage switching at VGS2
main switches, and improve the light-load efficiency. The D2
proposed scheme does not require the addition of an auxiliary (a)
circuit in the S BC, providing it with the advantages of low cost
T
and easily built-in integrated circuits. To verify its feasibility, an
S BC equipped with the proposed control scheme is de veloped, iL
with output voltage and output power of 5 V and 25 W, 0 t
respectively.
VGS2

Index Terms—quasi-resonant valley switching, ZVS , auxiliary 0 t

circuit
VGS1

I. INT RODUCT ION 0 t

heavy load light load

T he market for portable consumer electronic products (e.g.,

laptop computers and mobile communication devices) has
undergone rapid growth in the last few years. In turn,
(b)
Fig. 1(a) Synchronous buck converter and (b) key switching waveforms

consumers have become increasingly concerned about the shown by the red dotted lines in Fig. 1(b). Specifically, the
usage duration of their electronics devices. Currently, such operation of SBCs under light-load conditions is inadequate
devices are powered by batteries, and the voltage supply to such due to the low conversion efficiency.
products tends to decrease gradually. Therefore, to extend the In order to address the drawbacks of SBC, hybrid mode
battery life, synchronous buck converters (SBC) have been control strategies based on different loading conditions from
widely used in personal and portable devices (Fig. 1(a)). several different studies have been proposed [2–14]. The most
Conventional SBCs are controlled using complementary popular technique of the dual mode control is to combine with
pulse-width modulation (PWM), as shown in Fig. 1(b). Under CCM and discontinuous conduction mode (DCM). Generally,
heavy-load conditions, the low conduction loss inherent in a dual-mode operations can be divided into fixed-frequency
switch, MB, is used to operate an SBC in a continuous mode and variable-frequency mode.
conduction mode (CCM), thus increasing the conversion In variable-frequency control, a PFM technique based on the
efficiency. However, when the mean load current is lower than hysteresis of the output voltage determines the timing for the
the inductance current associated with a boundary conduction turning on and off of a metal-oxide-semiconductor field-effect
mode, the reverse inductance current creates excess loss [1], as transistor (MOSFET) [2–5]. In other words, the output power
decreases, thereby decreasing the switching frequency.
Therefore, the light-load efficiency of the SBC increases. The
Manuscript received XXX. XX, XXXX; revised XXX. XX, XXXX; drawback of this control strategy is a much wider range of
accepted for publication XXX. XX, XXXX. This work was supported by the switching frequencies, making EMI filter design difficult. In
Ministry of Science and Technology of Taiwan through Grant numbers MOST
105-2221-E-150 -047, and MOST 102-2221-E-150 -023 -MY3. addition, the output ripple voltage for this control strategy is
J. M. Wang is with the Department of Vehicle Engineering, National higher than that for the PWM control strategy.
Formosa University, Taiwan, ROC (phone: x-886-5-6315692; fax: Another variable-frequency technique involves detecting the
x-886-5-6321571; e-mail: jmw@sunws.nfu.edu.tw). valley of the inductor current. If the inductor current reaches the
S. T . Wu, is with the Department of Electronic Engineering, National
T aiwan University of Science and T echnology, Taipei, 10607, Taiwan, ROC. valley, the main switch will be triggered on. Thus, the SBC can
Color versions of one or more of the figures in this paper are available be operated at the boundary between CCM and DCM. The main
onlineat http://ieeexplore.ieee.org.

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Transactions on Power Electronics

switch operated in this region has the characteristics of auxiliary switches or passive devices containing resistors,
zero-current-switching (ZCS) [6]. The quasi-resonant inductors, or capacitors (RLC) for the SBC main switches to
switching technique is similar to the aforementioned control achieve ZVS; only logic circuits and comparators are needed.
strategy [7–9]. This scheme involves resonance generated As a result, the proposed scheme possesses various advantages
through the parasitic capacitance and inductance of switches. such as low cost and easily built-in integrated circuits (IC).
To improve the efficiency, it turns on the MOSFET when the SBCs exhibiting a 40 kHz switching frequency, 25 W output
vds resonance reaches a valley. The above-mentioned control power, 12 V input voltage, and 5 V output voltage were
strategies still have problems related to a wider variation range employed to verify the advantages of the proposed control
of switching frequencies when the output power drops. technique.
Due to the aforementioned drawbacks of variable-frequency Table I shows a general comparison of the dual-mode control
control, some authors have opted for fixed-frequency PWM strategies. The SBC with the proposed control strategy exhibits
techniques [10–14]. These control methods need to detect the better performance than the other two strategies, especially
zero point of the inductor current. When the inductor current with regards to the efficiency. In addition, the switching
reaches zero, the synchronous switch is turned off to prevent an frequency is almost fixed. Therefore, it is a simple process to
inverse inductor current. Another control strategy is to emulate suppress EMI and audio noise.
the inductor current with an auxiliary circuit, and the result is The rest of this manuscript is organized as follows: Section II
the same as for the previous method [13]. In order to improve explains the concepts and operating principles of the proposed
the efficiency of SBCs under light-load conditions, Ref. [14] control scheme; Section III presents the design of the control
adopted the ZVS technique. The key point of the control circuit; Section IV gives details of the power loss analysis;
strategy is that the synchronous switch is turned on twice in a Section V presents design considerations for relevant devices;
complete switching cycle; therefore, the main switch has a ZVS Section VI presents experimental results; Section VII gives the
characteristic without considering the vds of the synchronous conclusions.
switch for the on-state. That is, the synchronous switch
generates extra switching losses at the instant that the switch is II. PROPOSED DUAL-MODE CONVERT ER ST RUCT URE AND
turned on. In order to overcome this drawback, this paper OPERAT ING PRINCIPLES
proposes a novel control strategy. Figure 2(a) presents the block diagram of the proposed
Previous studies have proposed the use of soft-switching control scheme, including a fixed-frequency PWM controller
techniques that comprise ZVS and ZCS to improve the and an LZC. To achieve ZVS while avoiding reverse
efficiency of buck converters. ZVS is commonly applied to inductance currents, an external current transformer and a
computer, communication, and consumer electronics products
zero-hysteresis comparator must be used when inductance
because it eliminates the need for the switch to be turned on, a current levels are less than zero in order to generate v Z1_O
process that causes capacitive loss. These techniques generally signals to turn off the synchronous switch (MB). In other words,
require external active auxiliary circuits, and main switch (i.e., in the proposed control scheme, the SBC operating mode can be
ZVS) operations are completed using resonance currents divided into a DCM and a CCM. The error signal v EAO is
generated by LC cells. Although these techniques result in good generated by comparing the feedback voltage vFB of the error
performance, they are associated with increased device volume compensation amplifiers with the reference voltage Vref. This
and circuit complexity, as well as elevated device stress [15– signal can be used to determine the duty cycle of the main
22]. Digital control techniques are also feasible solutions [23– switch. In addition, v ZCD is mainly supplied by an auxiliary
25]. However, they require complex mathematical algorithms winding for detecting the drain voltage of MB. Furthermore, the
and the adoption of digital signal processors. Furthermore, the negative-edge of vZ2_O triggers LZC to generate v pulse signals,
overall costs associated with such techniques are considerably which turn on MB and the rest of the PWM controller to
high. implement the valley switching of MB and ZVS of the main
This study proposes a novel dual-mode control technique switch MA . Here, Vref1 is close to VO /2.
combined with QR valley switching and ZVS. In the DCM Figure 2(b) shows the theoretical waveform of the proposed
region, a limit-frequency QR valley switching technique turns controller, which involves DCM and CCM operations. The
on the main switch to achieve ZVS to increase the efficiency of DCM operation is described as follows. When the inductance
the SBC. Furthermore, this novel limit-frequency ZVS current drops to zero, the vZ1_O signal changes from a high level
controller (LZC) maintains the switching frequency under to a low level in order to turn off MB and prevent the occurrence
light-load conditions. The method requires no external of a reverse induction current. Subsequently, the LZC begins to
T ABLE I COMPARISON OF SBC CONT ROL T ECHNIQUES
Operation Mode Efficiency Load Range Output Voltage Ripple Audio Noise EMI filter design Line/load regulation
CCM/DCM Good Wide Large Medium Hard Good
(Variable-Frequency)[2–9]
CCM/DCM Medium Wide Small Small Easy Good
(Fixed-Frequency)[10–13]
CCM/DCM Good Wide Small Small Easy Good
(Fixed-Frequency)[14]
CCM/DCM Very Good Wide Small Small Easy Good
(Novel)

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detect valley voltages created by inductance and parasitic becomes feasible following MB valley conduction. During
capacitance (Coss) resonance. To prevent the switching CCM operation, the LZC enters a conventional synchronous
frequency from reaching a higher frequency, LZC generates a rectification control mode.
control signal, v pulse, for valley switching of MB based on the
frequency of v osc. When MB turns on after Δt, the PWM III. CIRCUIT IMPLEMENT AT ION
controller restarts to achieve ZVS of MA for the next switching QR control strategy usually has a problem about much
cycle. higher switching frequency. This drawback is typically
vZCD resolved by limiting the highest switching frequency, which
vds_MA
Coss1 iO can be done by adding a minimum off-time (during which
D1 L
vZ1 energy is transmitted to an output load) to a switching cycle [26,
Rsense iL
MA CT
R1 27]. Although this technique can prevent an increase in the
VDC is CO RO VO
MB frequency, it requires the addition of blanking time circuits and
VGS1 VGS2
vds_MB R2 time delay circuits, rendering the overall control circuit design
Driver
D2 Coss2 more complex. Instead, this study proposes an LZC that only
requires one additional pulse generator circuit to limit the
vZ1 vZ1_O vFB maximum frequency of the QR mode (Fig. 3). Additionally, MA
vPWM vEAO Voltage Loop

Limit-Frequency Comparator
Compensator Vref has characteristics of ZVS.
Zero-Hysteretic
Comparator
ZVS Controller Sawtooth When the inductance current iL drops to zero, the v Z1_O signal
vZCD Oscillator turns off MB through the AND gate. In the QR mode, Coss
vZ2_O vpulse
RZCD vZ2 vosc PWM Controller
induces resonance with L, as shown in Fig. 3(b). When the
Vref1 Hysteretic
Comparator vds_MB voltage resonance reaches a valley, the v ZO_2 signal
(a) immediately changes from a positive potential to a negative
Transient
Operation Region potential, and processing this signal using a differentiator and a
VO resistive divider (Rth1 and Rth2 ) yields an adjustable pulse signal
vp_th. To limit the maximum frequency, the PWM IC oscillator
Light Load Heave Load iO signals v osc and v p_th must be composed for comparison with
The control signal and the inductor
current waveforms operated in DCM
Tdelay The control signal and the inductor
current waveforms operated in CCM VTH to determine the valley switching timing (Fig. 3(a)). If the
Δt
iL TS vsoc_p signal (vsoc_p = v p_th + v soc_p, where vp_th = Vp_h ) is lower
than VTH , then the v pulse signal is maintained at a low potential
ΔIL

t t
without influencing the operation of the oscillator. This
MA operating mode is repeated until t0 is achieved.
VGS1
At t0 , vds_MB reaches the valley in resonance. At this moment,
t t
VGS2
MB vsoc_p is higher than VTH . Hence, v pulse changes from a low to a
high level. During this transient state, MB and Q are turned on
vZ1_O
t t simultaneously. This causes the oscillator to discharge rapidly
t t
and the inductor starts to store energy. After t1, MB and Q are
vds_MB turned off simultaneously. Thus, the PWM controller restarts to
VDC 2VO VDC change the designed oscillation frequency. As mentioned above,
t t
vds_MA the frequency of the PWM controller increases if v p_th is higher.
VDC
t
VDC
t
Conversely, the frequency of the PWM controller will decrease.
vZCD Vref1
t
Vref1 These results indicate that v p_th can be adjusted according to the
t
maximum switching frequency. Furthermore, the energy stored
vZ2_O in the inductor in the previous state causes the parasitical
t t capacitor to discharge, forcing MA to achieve ZVS in the
vpulse
subsequent switching cycle. The following circuit design is
vosc
t t divided into two parts—the ZVS of MA and valley switching of
VH
MB.
VL
t VCC
t
DCM Operation Region CCM Operation Region Rp1 vosc
Differential
vp
(b) vZ2_O Q1
Circuit
Rth1
vp_th vosc_p
Q C T RT PWM
Fig. 2. (a) Proposed dual mode control scheme and (b) key waveforms of the Rth2
vp1 Monostable vpulse
Controller
CMP trigger
proposed controller circuit
VTH
vosc
The CCM operation is described as follows. As the output
power increases, the operating mode of the SBCs is changed vPWM
MB
driver

VGS2
from DCM to CCM. Concurrently, the synchronous switch and vZ1_O vZCD

the main switch are turned on complementarily. This willnot be vPWM Delay time
VGS1
MA
influenced by v Z1_O. In conclusion, the controllers in the
Limit-Frequency ZVS Control Circuit
proposed control scheme can operate SBCs in the DCM under
(a)
light-load conditions. In addition, the MA ZVS operation

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Δt Tdelay vds_MA
VGS1 Coss1 D1 L iL iO
Quasi-Resonant
Mode Region MA
t VDC
VGS2 VGS1 D2 CO RO VO
VGS2 vds_MB
t
iL MB Coss2

Fig. 4. SBC equivalent circuit in resonance intervals

t
Tr
v Z1_O
vds_MB

t VDC 2VO
vds_MB
t

VDC 2VO
VTH
t
vds_MA Vp_h

VDC

vZCD Vref1
t
vosc_p t
tp
t TS
Fig. 5. SBC valley switching timing
vZ2_O
B. ZVS of M A
t
T delay and Δt of v pulse need to be considered if ZVS of MA is
achieved. Figure 6 presents the SBC-equivalent circuit when
vp_th Vp_h MA is turned off and MB is turned on. The voltage across the
t
inductance L is −VO . The inductance current iL is expressed as
VL follows:
vosc −V
t
𝑖 𝐿 (𝑡) = L O (t − t 0) (4)
VTH To ensure that the MA parasitic capacitance is fully discharged
in order to achieve ZVS, the stored inductor energy EL must be
vosc_p t greater than the energy stored in parasitic capacitors, ECoss1. The
vpulse
energy storage equation is expressed as follows:
t 2
t0 t1 (𝑖 𝐿𝑝 ) × L ≥ COSS1 × (VDC )2 (5)
(b) where iLp is the peak value of the inductance current.
Fig. 3. (a) The proposed LZC logic circuit and (b) Theoretical waveforms of Through Eqs. (2) and (3), the pulse time can be determined
proposed LZC driver under light-load condition.
as
√LCOSS1 ×VDC
∆t (min) ≥ (6)
A. QR valley switching of MB VO

Figure 4 shows an SBC-equivalent circuit in resonance This mode is completed when MB is turned off.
intervals. In this circuit, iL(t) and vds_MB(t) can be calculated as: vds_MA
V
𝑖 𝐿 (t) = − O sin(𝜔t) (1) Coss1 D1 L iL iO
𝑍
𝑣𝑑𝑠_𝑀𝐵(t) = VO − VO cos(𝜔t) (2) MA
1 L VDC D2
where 𝜔 = and Z = √ C，C= COSS1 + COSS2. VGS1 CO RO VO
√ LC
Figure 5 depicts the valley switching timing, where T S and T r VGS2 vds_MB
represent the switching cycle and the resonance cycle, MB Coss2
respectively. In this study, the conduction time of MB was
designed to be close to the switching cycle; therefore, the Fig. 6. SBC equivalent circuit in Δt intervals
controller reset time was set to tp . The magnitude of Vp_h can be
determined as follows: In this study, the monostable trigger circuit generates a PWM
V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 signal vpulse. As shown in Fig. 7, the RC circuit determines the
Vp_h = VTH − R C (TS − Tr ) (3) width of Δt by using the charging and discharging behavior.
T T
where V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 is the peak voltage (V𝑜𝑠𝑐_𝑝𝑒𝑎𝑘 = 3V) of the Therefore, Δt can be expressed as
sawtooth waveform generated from a TL494 oscillator, V
Δt = −RC𝑙𝑛 (1 − VTH1) (7)
CC
TS = 2𝜋√LC, and VTH = 4.8 V.

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where VTH1 is the high-level input voltage of the NOR gate. The where T r is the rise time and f s is the switching frequency. In
capacitance of Cp can be determined using Eqs. (2) and (7): addition, the loss of MB is similar to that of MA [29], and
VTH1 √LCOSS1 ×VDC therefore,
−R p Cp 𝑙𝑛 (1 − )≥ (8) VF+1.1R𝑑𝑠,MB×I O T
VCC VO 𝑇𝑟𝑎𝑑. ) × I O ) × r × 𝑓𝑠.
P𝑆𝑤𝑖𝑡𝑐ℎ_MB = (VF × I O + ( 2 2
The technique of using a monostable trigger circuit to
determine the pulse width of the v pulse signal is thus feasible. (13)
Monostable trigger circuit
VCC vp1 t
VGS1 (1-D)TS t
vp1 Cp Rp
vpulse vA t
vA vB VTH DTS
VGS2 t
vB t

vpulse t ΔiL
Δt IO
ids,MA t
Fig. 7. Structure and control sequence of a monostable trigger circuit.

T delay is another key point for MA to achieve ZVS. After the

PWM controller restarts, the MA conduction time is noted ΔiL
because the inductance currents can become positive at any ids,MB IO t
time and charge Coss1, which may result in the failure of the MA
ZVS. Therefore, the delay time T delay must be approximately
TS
one-fourth of the resonance cycle:
2𝜋 √LC
Fig. 8 Key waveform of the conventional SBC operating in CCM under
OSS1
Tdelay ≅ (9) light-load conditions
4
If MA becomes conductive immediately after passing
The proposed scheme facilitates the operation of SBCs in the
through Tdelay, the ZVS operation is complete. Subsequently, a
DCM under light-load conditions, in which MA achieves ZVS
new switching cycle restarts.
(Fig. 9). In this operating mode, the power losses of MA are
mainly conduction losses [11]:
IV. POWER LOSS ANALYSIS 𝑁𝑜𝑣. 𝑁𝑜𝑣.
2
P𝐶𝑜𝑛._MA = (I 𝑑𝑠,MA(𝑅𝑀𝑆) ) × R 𝑑𝑠,MA (14)
Because the aim of this study is to improve the light-load In the DCM, the root-mean-square current passing through
power losses of SBCs that employ conventional control
MA can be expressed as follows:
strategies, the device losses are analyzed under light-load
3
conditions. Devices such as high-side MOSFETs, low-side 𝑁𝑜𝑣.
(I 𝐿,𝑝𝑒𝑎𝑘 ) ×𝑓𝑠1×L
MOSFETs, and inductors cause most of the power losses in I 𝑑𝑠,MA(𝑅𝑀𝑆) = √( 3×(VDC−VO )
)
conventional SBCs. The total power losses in conventional
MOSFETs can thus be categorized as conduction losses and where
𝑇𝑟𝑎𝑑. 𝑇𝑟𝑎𝑑. I ×VO×(VDC −VO)
switching losses. Therefore, P𝐶𝑜𝑛._MA and P𝐶𝑜𝑛._MB can be I 𝐿,𝑝𝑒𝑎𝑘 = √ 2 ( O )
VDC ×𝑓𝑠1×L
expressed as follows [11, 28]:
𝑇𝑟𝑎𝑑. 𝑇𝑟𝑎𝑑.
2 However, the power losses of the low-side MOSFETs are a
P𝐶𝑜𝑛._MA = (I 𝑑𝑠,MA(𝑅𝑀𝑆) ) × R 𝑑𝑠,MA (10) concern. Although the proposed control strategy enables MB
𝑇𝑟𝑎𝑑. 2
P𝐶𝑜𝑛._MB = ( I 𝑇𝑟𝑎𝑑. )
𝑑𝑠,MB(𝑅𝑀𝑆) × R 𝑑𝑠,MB (11) conduction to occur twice within a switching cycle (T1 ), the
where R 𝑑𝑠,MA and R 𝑑𝑠,MB are the static drain–source second conduction time is transient, indicating that the
on-resistances for MOSFET conduction. conduction losses are negligible (given by the red dotted line in
Fig. 9). Accordingly, MB causes one conduction loss and two
Figure 8 shows the switch and current waveforms for
conventional SBC when it is operated in the load range of switching losses. The conduction losses of MB can be expressed
as follows [11]:
0 A < IO < ΔiL/2. The root-mean-square currents passing 2
𝑁𝑜𝑣. = ( I 𝑁𝑜𝑣.
through MA and MB can be expressed as P𝐶𝑜𝑛._MB 𝑑𝑠,MB(𝑅𝑀𝑆)) × R 𝑑𝑠,MB, (15)
𝑇𝑟𝑎𝑑. (∆𝑖 𝐿⁄2)2 where
I 𝑑𝑠,MA(𝑅𝑀𝑆) = √( + I O2 ) × D and
3 3
(I 𝐿,𝑝𝑒𝑎𝑘 ) ×𝑓𝑠1×L
𝑁𝑜𝑣.
I 𝑑𝑠,MB(𝑅𝑀𝑆) = √( ) .
𝑇𝑟𝑎𝑑. (∆𝑖𝐿⁄ 2)2
I 𝑑𝑠,MB(𝑅𝑀𝑆) = √( + I O2 ) × (1 − D), 3×VO
3
where I O is the mean output current. Next, the switching losses are analyzed. Since MB
The parasitic capacitance of the MOSFETs causes Vds and Ids conduction occurs twice in a switching cycle, switching losses
to overlap when the switch is turned on, and this problem can be divided into two categories. The black dotted line in Fig.
causes turn-on switching losses. The loss of MA can be 9 illustrates the first category, showing that MB is controlled in
expressed as follows [8]: the QR valley switching. Therefore, the turn-on switching loss
𝑇𝑟𝑎𝑑. 1 1 is derived as follows [8]:
P𝑆𝑤𝑖𝑡𝑐ℎ_MA = ( × V𝑑𝑠,MA × I O × Tr × 𝑓𝑠 ) + ( × COSS_MB × 1
2 2 𝑁𝑜𝑣.
P𝑆𝑤𝑖𝑡𝑐ℎ_MB_1 2
= 2 × COSS_MB × V𝑑𝑠,MB × 𝑓𝑠1 (16)
2
V𝑑𝑠,MA × 𝑓𝑠 ) (12)

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follows: input power VDC = 12 V, output power VO = 5 V,

PWM controller TL494, maximum output power PO(max) =
25 W , output voltage ripple ΔVO = 10%, and switching
frequency fs = 40 kHZ. General inductor designs should ensure
VGS1 D1TS1 t
that the inductance current maintains continuity at one-tenth of
the rated current [23, 30]. The inductance value can be
DTS1
VGS2 t calculated using (23)
∆I
I o(min) = 2L = 0.1IO = 0.5A (22)
iL,peak and
(V −VO)VO T
IO L (max) = inV ∆I = 73μH. (23)
ids,M A
t in L
The output filter inductance L in the prototype circuit is 73
μH. CH172060, which features high flux and is applicable to
iL,peak high current outputs, is adopted in the iron core of the inductor.
IO
The inductor turns are thus calculated as follows:
ids,M t
B
L
N = √ = 48, (24)
Al
VDC VO where Al=0.032μH.
vds,M B t The selected output capacitance Co must satisfy the output
voltage ripple requirement. Under steady-state conditions, the
VDC voltage changes caused by 20% load current variation are
vds,M
considered. Given the predetermined data of the output current
A t (IO = 5 A) and voltage (VO = 5 V), the output current variation
TS1 △Io = 1 A and output voltage variation △VO = 100 mV can be
Fig. 9 Key waveform of the proposed SBC operating in DCM under light-load
determined, respectively. On the basis of this result, the
conditions maximum ESR of the capacitor is estimated as follows [23, 29]:
100𝑚𝑉
The second part of the switching loss is similar to Eq.(13), ESR 𝑚𝑎𝑥 = 1𝐴 = 100mΩ (25)
with the only difference that the switching frequency changes According to the aluminum electrolytic capacitor datasheet,
from f s to fs1. The substituted equation as follows. ESR × C can be approximated to a constant number value of
V +1.1R𝑑𝑠,MB
𝑁𝑜𝑣.
P𝑆𝑤𝑖𝑡𝑐ℎ_MB_2 = (VF × I O + ( F ) × I O ) × Tr × 𝑓𝑠1 50–80 uF [23, 30]. If ESR × C = 50 μF, then C = 1000 μF. A
2
(17) value of 1000 μF/16.3 V is selected.
Regarding the inductance power losses, the equivalent series In the present study, a CS097060 iron core was used as the
resistance (ESR) of the inductor coils is the main cause of current transformer to avoid the defect of conventional
inductance losses. The inductance losses can be approximated resistance (e.g., additional power losses induced by a resistance
as follows, regardless of whether new or conventional control at high current applications). Due to the zero-hysteresis
techniques are adopted for the SBCs: comparator requires a check signal of maximum 15 V and the
P𝐼𝑛𝑑𝑢𝑐𝑡𝑜𝑟 = P𝑤𝑖𝑛𝑑𝑖𝑛𝑔_𝑙𝑜𝑠𝑠𝑒𝑠 + P𝑐𝑜𝑟𝑒_𝑙𝑜𝑠𝑠𝑒𝑠 current transformer turn ratio is 1:50, Rsense can be determined
as follows:
(18) 15
Here, the P𝑤𝑖𝑛𝑑𝑖𝑛𝑔_𝑙𝑜𝑠𝑠𝑒𝑠 can be expressed as I O2 × ESRL, and R sense = = 150Ω, (26)
𝑖𝑠
P𝑐𝑜𝑟𝑒_𝑙𝑜𝑠𝑠𝑒𝑠 can be obtained from the data-sheet of magnetics 𝑖
where 𝑖 𝑠 = N𝑂 = 0.1A
vendors.
Two N channel MOSFET IRFB2907 were used as the SBC
The total power losses of the SBCs produced using the novel main switch and synchronous switch. The parasitic capacitance
and conventional control schemes can be expressed
respectively as: of the switches was 2100 pF. According to (7), Δt(min)  952 ns
𝑇𝑟𝑎𝑑.
P𝑡𝑜𝑡𝑎𝑙_𝑙𝑜𝑠𝑠𝑒𝑠 𝑇𝑟𝑎𝑑.
= P𝐶𝑜𝑛._MA 𝑇𝑟𝑎𝑑.
+ P𝐶𝑜𝑛._MB 𝑇𝑟𝑎𝑑.
+ P𝑆𝑤𝑖𝑡𝑐ℎ_MA + can be determined. The pulse width set in this study was
𝑇𝑟𝑎𝑑. approximately 1050 ns. Finally, known parameters were
P𝑆𝑤𝑖𝑡𝑐ℎ_MB + P𝐼𝑛𝑑𝑢𝑐𝑡𝑜𝑟 (19)
substituted into (3) to determine the pulse voltage (Vp_h = 2V).
and
𝑁𝑜𝑣.
P𝑡𝑜𝑡𝑎𝑙_𝑙𝑜𝑠𝑠𝑒𝑠 𝑁𝑜𝑣.
= P𝐶𝑜𝑛._MA 𝑁𝑜𝑣.
+ P𝐶𝑜𝑛._MB 𝑁𝑜𝑣.
+ P𝑆𝑤𝑖𝑡𝑐ℎ_MB_1 +
𝑁𝑜𝑣. VI. EXPERIMENT AL RESULT S
P𝑆𝑤𝑖𝑡𝑐ℎ_MB_2 + P𝐼𝑛𝑑𝑢𝑐𝑡𝑜𝑟 . (20)
Figures 10(a) and (b) illustrate the control signal and
Finally, the reduced power losses of the proposed scheme
inductance current waveforms of the SBCs under light-load
can be estimated by subtracting the total losses of the proposed
(1% load) and heavy-load (100% load) operating conditions,
SBC from the total losses of the conventional SBC:
𝑇𝑟𝑎𝑑.
ΔP𝑙𝑜𝑠𝑠𝑒𝑠 = P𝑡𝑜𝑡𝑎𝑙_𝑙𝑜𝑠𝑠𝑒𝑠 𝑁𝑜𝑣.
− P𝑡𝑜𝑡𝑎𝑙_𝑙𝑜𝑠𝑠𝑒𝑠. (21) respectively. When the SBCs are operated in the DCM, MB is
turned off when the inductance current drops to zero to prevent
the converter from causing additional losses. In addition, within
V. DESIGN CONSIDERAT ION a switching cycle, the second conduction of MB leads to
The SBC design process conforms to the following circuit inductance charging supplying sufficient energy to complete
specifications. The input and output data specifications are as the MA ZVS operation (Fig. 10(a)). Figure 10(b) shows the

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Transactions on Power Electronics

SBCs operating in the CCM, indicating that MA and MB are

complementary operations identical to those of a conventional
synchronous rectification control IC.

(b)
Fig. 11 (a)Key ZVS-related waveforms; (b) Enlargement of ZVS-related
waveforms

(a)

(a)

(b)
Fig. 10 (a) Light-load control signals and inductance currents; (b) Heavy-load
control signals and inductance currents

The ZVS waveform of MA is shown in Fig. 11. The

magnification in Fig. 11(b) shows that MA conduction is
achieved when the voltage vds_MA drops to zero, confirming the
completion of the ZVS operation. This result demonstrates that
the proposed pulse width of approximately 1050 ns is
applicable. Figure 12 shows the waveform measured from the
proposed QR mode at P O = 0.25 W. Figure 12(a) illustrates the (b)
outcome of the generation of the pulse signal and sawtooth Figs. 12. (a)(b)Key valley switching-related waveforms
waveform signal (vsoc_p = v p_th + vsoc_p), verifying that the
operating frequency of the QR mode is limited at 43.5 kHz Figure 13 shows the designed SBC output voltage ripple at
approximately 100 mV, conforming to the aforementioned
when Vp_h = 2 V. In Fig. 12(b), the vpulse signal is generated
design conditions. The transient response of the output voltage
through a comparator that compares the vosc_p signal and the
VTH voltage when the vds_MB voltage resonance reaches the is depicted in Fig. 14. According to the measurement results,
the variation in the output voltage transient response is lower
valley, thereby triggering the restart of the PWM IC operation.
than 150 mV, regardless of whether the output power is
The proposed scheme can therefore strongly constrain the
changed from 2.5 to 25 W (Fig. 14(a)) or from 25 to 2.5 W (Fig.
operating frequency of the QR mode and prevent an
14(b)). In general, the design requirements of line regulation
excessively high switching frequency that is observed in
and load regulation are within ± 1%. Fig. 15 shows the
conventional control methods during operation under light-load
conditions. experimental results of the line and load regulations. As seen
from the figure, the measurement of SBC with the proposed
control method was 37 mV/A when the input voltage was 7.4 V.
In addition, the load regulation was still 37 mV/A when the
maximum input voltage was 16.8 V. According to the
experimental results, the proposed control method can meet the
specifications.
It is noticed that Table II shows the SBC power loss data
corresponding to (19) and (20). When PO = 0.25 W, the SBC
utilizing the ZVS control strategy exhibited a loss of
approximately 18 mW. In comparison, the SBC utilizing the
(a) conventional strategy exhibited a loss of 45 mW. When the
output power was approximately 2.5 W, the power losses of the
two SBCs were identical.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2623353, IEEE
Transactions on Power Electronics

Figure 16 compares the efficiencies of the SBCs utilizing the

novel and conventional control strategies. The blue and red
lines represent the proposed control technique and the
conventional control technique (with data detailed in Table III),
respectively. The green line is the efficiency estimated
according to the data in Table III. The yellow line in the plot
shows the efficiency of the SBC with the most popular PFM
technique. The experimental results confirm that the proposed
control strategy can boost the light-load efficiency of SBCs
considerably.

Fig. 16. Efficiency comparison between the novel and conventional scheme

TABLE II LOSS ANALYSIS OF T HE NOVEL AND CONVENT IONAL

SCHEMES
PO 𝑇𝑟𝑎𝑑 .
P𝑡𝑜𝑡𝑎𝑙 _𝑙𝑜𝑠𝑠𝑒𝑠
𝑁𝑜𝑣 .
P𝑡𝑜𝑡𝑎𝑙 _𝑙𝑜𝑠𝑠𝑒𝑠 ΔP losses
0.25W 45mW 18mW 27mW
0.50W 60mW 33mW 30mW
0.75W 66mW 45mW 21mW
Fig. 13. Output voltage ripple waveform 1.00W 82mW 57mW 25mW
1.25W 98mW 67mW 31mW
1.50W 112mW 76mW 36mW
1.75W 126mW 87mW 39mW
2.00W 136mW 100mW 36mW
2.25W 150mW 130mW 20mW
2.50W 172mW 172mW 0W

TABLE III EFFICIENCY OF T HE NOVEL AND CONVENT IONAL

SCHEMES
Estimated
Efficiency of the Efficiency of the
efficiency of
traditional proposed
PO proposed
(a) synchronous buck synchronous
synchronous
converter buck converter
buck converter
0.25 W 82.0% 94.0% 92.7%
0.50 W 88.8% 94.3% 93.3%
0.75 W 91.2% 94.5% 93.9%
1.00 W 91.8% 94.8% 94.3%
1.25 W 92.1% 95.0% 94.6%
1.50 W 92.5% 95.1% 94.9%
1.75 W 92.8% 95.2% 95.0%
2.00 W 93.2% 95.1% 95.0%
2.25 W 93.3% 94.5% 94.2%
2.50 W 93.1% 93.1% 93.1%

VII. CONCLUSION
(b)
Fig. 14. Output voltage transient response (a) with light-load (10%) changed to In this study, a novel dual-mode control scheme suitable for
heavy-load (100%); (Vo: 100 mV/div., Vpulse: 10 V/div., and time: 10 synchronous buck converters (SBC) was developed, and the
ms/div.); (b) with heavy-load (100%) changed to light -load (10%); (Vo: 100 operating principle of this strategy was explained. It was then
mV/div., Vpulse: 10 V/div., and time: 10 ms/div.)
analyzed to demonstrate its efficiency. The novel control
scheme mainly integrates a continuous conduction mode and a
discontinuous conduction mode (DCM). In particular, when the
SBC was operated in the DCM, the second synchronous switch
conduction that occurred before the main switch conduction
contributed to the zero-voltage switching (ZVS) of the main
switch. In addition, composing the pulse and sawtooth
waveform signals prompted the synchronous switch to achieve
valley switching under limited frequency conditions. This
scheme possesses the following advantages. First, it is
integrated with a synchronous rectification technique to reduce
Fig. 15 shows the line regulation and load regulation of the proposed control
scheme. the conduction losses of the converter and improve the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2623353, IEEE
Transactions on Power Electronics

efficiency of the overall circuit. Second, operating an SBC in of the output voltage causes vds of the synchronous to increase.
the DCM can achieve ZVS in the main switch without requiring If the synchronous switch is not turned on at the valley, the
additional auxiliary switches or passive devices comprising a switching losses will be more serious. This result is the
resistor, an inductor, and a capacitor. The simple pulse disadvantage of Ref. [14].
generators are employed to limit the highest switching DCM Region
(Stage 1) (Stage 2)
frequency of the quasi-resonant mode. Finally, in Appendix, a VGS1 VGS2 VGS1 VGS2
comparison between the proposed control method with variable
switching frequency and the control method with constant
switching frequency presented in [14] is provided. t

APPENDIX B
The purpose of this paper and Ref. [14] is to improve the vds A
t
efficiency when the SBC operates under light-load conditions. VTH
The analysis of the control strategy is described when the SBC
operates under light-load conditions. Figure 17(a) shows the vosc t
TS
waveforms of key control signals and v ds of the synchronous TS
(a)
switch for the SBC control strategy [14]. This technique utilizes
DCM Region
the fixed-frequency control strategy. In state1, in order to (Stage 1) (Stage 2)
VGS2
VGS1 VGS2 VGS1
achieve ZVS of the SBC main switch, the synchronous switch
has to turn on at point A. In the same switching period, when
the load condition changes from state1 to state2, the v ds of the
synchronous switch changes with the variation of loading as t

well (from point A to point B). This result causes switching

losse in the synchronous switch. The losses can be expressed as
D
[8]: vds C t
1 2 VTH
P𝑆𝑤𝑖𝑡𝑐ℎ_𝑙𝑜𝑠𝑠 = × COSS × 𝑣𝑑𝑠 × 𝑓𝑠 (27) vp_th vp_th
2
vosc
where +vp_th
𝑣𝑑𝑠 (t) = VO − VO cos(𝜔t) and COSS is the parasitic capacitance TS1 TS2
t

of the synchronous switch.

According to the description above, the control strategy [14] (b)
Fig. 17. (a)T he SBC oscillator signals vosc, control signal VGS2 and vds of the
causes extra switching losses. This paper provides a synchronous switch from Ref[14]. (b) T he SBC key signal(vosc+vp_th ), control
frequency-limited QR control strategy to overcome this signal VGS2 and vds of the synchronous switch with the proposed control
disadvantage. Figure 17(b) shows the waveforms of key control strategy.
signals and vds of the synchronous switch for the SBC using the
proposed control strategy. The purpose of this technique is to
control the synchronous switch to turn on by using v p_th at point
C for valley switching (state1). In state2, although the heavier
loading makes the vds valley duration different from the
previous state, v p_th can still trigger the synchronous switch at
point D. That is, if the synchronous switch’s valley is generated
in the gray region, the valley turn-on of the synchronous switch
can be assured under the frequency-limited condition.
The following experimental results from these two control
strategies utilize the designed components in the paper. The
(a)
only difference was that the switching frequency of the control
strategy from Ref. [14] was fixed at 40 kHz. The key measured
waveforms of the two control strategies for the SBC are shown
in Fig. 18 ( the output power was 0.7W). Figure 18(a) shows
that the vds of the synchronous switch with the control strategy
from Ref. [14] was 9 V. Based on Eq. (27), the switching loss
was about 4.05mW. Figure 18(b) shows the proposed control
strategy. The figure shows that the proposed method can lower
the vds of the synchronous switch (vds ＝1 V), and the switching
frequency was restricted to about 43.5 kHz. Compared with the
previous strategy, the proposed technique can save about 4 mW (b)
in switching losses. Table 4 provides the measured efficiency Fig. 18. Waveforms of VGS1 , VGS2 , vds_MB and key oscillator signals for (a) the
of the SBC using a power analyzer, PM1000. In here, the input Ref.[14] and (b) the proposed SBC (Ch1 : 20 V/div., Ch2: 20 V/div., Ch3:
5V/div., and Ch4: 2 V/div.)
and output power under two different voltage specifications are
measured. According to the experimental results, the increment

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Transactions on Power Electronics

T ABLE IV KEY LOSS ANALYSIS OF T HE NOVEL AND REF.[14] SCHEMES

𝑅𝑒𝑓 .[14 ] 𝑅𝑒𝑓 .[14 ] 𝑅𝑒𝑓 .[14 ] 𝑁𝑜 𝑣 . 𝑁𝑜 𝑣 .
VDC VO PO P𝑖𝑛 𝑁𝑜 𝑣 .
P𝑖𝑛 𝑣𝑑𝑠 _𝑆𝑅_𝑠𝑒𝑐𝑜𝑛𝑑 P𝑆𝑅_𝑠𝑒𝑐𝑜𝑛𝑑_𝑙𝑜𝑠𝑠𝑒𝑠 𝑣𝑑𝑠_𝑆𝑅_𝑠𝑒𝑐𝑜𝑛𝑑 P𝑆𝑅_𝑠𝑒𝑐𝑜𝑛𝑑_𝑙𝑜𝑠𝑠𝑒𝑠 𝐸𝑠𝑡 𝑖𝑚𝑎𝑡𝑒𝑑
ΔP𝑙𝑜𝑠𝑠𝑒 𝑠
𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑑
ΔP𝑙𝑜𝑠𝑠𝑒𝑠
12V 5V 0.35W 0.382W 0.375W 8V 3.20mW 1.0V 0.05mW 3.15mW 7.0mW
12V 5V 0.70W 0.737W 0.731W 9V 4.02mW 1.0V 0.05mW 4.00mW 6.0mW
24V 12V 1.35W 1.428W 1.407W 20V 20.0mW 5.0V 1.30mW 19.0mW 21.0mW
24V 12V 2.77W 2.862W 2.845W 21V 22.1mW 4.0V 0.91mW 21.1mW 17.0mW

References [20] H. L. Cheng and C. W. Lin, “ Design and implementation of a high-power

[1] A. Stratakos, “ High-efficiency, low-voltage dc–dc conversion for factor LED driver with zero-voltage switching-on characteristics,” IEEE
portable applications,” Ph.D. dissertation, Dept. Electr. Eng., Comput. Trans. Power Electron., vol. 29, no. 9, pp. 4949–4958, Sep. 2014.
Sci., Univ. California, Berkeley, 1999. [21] R. T . Naayagi, A. J. Forsyth, and R. Shuttleworth, “ High power
[2] W. R. Liou, M. L. Yeh, and Y. L. Kuo, “ A high efficiency dual-mode bidirectional DC–DC converter for aerospace application,” IEEE Trans.
buck converter IC for portable applications,” IEEE Trans. Power Power Electron., vol. 27, no. 11, pp. 4366–4379, Nov. 2012.
Electron., vol. 23, no. 2, pp. 667–677, Mar. 2008. [22] X. Wu, J. Yang, J. Zhang, and H. Xu, “ Design consideration of soft
[3] J.-C. T sai, T.-Y. Huang, W.-W. Lai, and K.-H. Chen, “Dual modulation switched buck PFC converter with Constant On-T ime (COT) control,”
technique be for high efficiency in high-switching buck converters over a IEEE Trans. Power Electron., vol. 26, no. 11, pp. 3144–3152, Nov. 2011.
wide load range,” IEEE Trans. Power Electron., vol. 58, no. 1, pp. 1671– [23] H. Bae, J. Lee, J. Yang, and B. H. Cho, “ Digital resistive current (DRC)
1680, Jul. 2011. control for the parallel interleaved DC–DC converters,” IEEE Trans.
[4] P.-J. Liu, J.-N. Tai, H.-S. Chen, J.-H. Chen, and Y.-J. E. Chen, “ Spur Power Electron., vol. 23, no. 5, pp. 2465–2476, Sep. 2008.
reduction design of frequency-hopping dc–dc converters,” IEEE Trans. [24] M. Barai, S. Sengupta, and J. Biswas, “ Dual-mode multiple-band digital
Power Electron., vol. 27, no. 11, pp. 4763–4771, Nov. 2012. controller for high-frequency DC–DC converter,” IEEE Trans. Power
[5] M. Gildersleeve, H. P. Forghani-Zadeh, and G. A. Rincon-Mora, “A Electron., vol. 24, no. 3, pp. 752–766, Mar. 2009.
comprehensive power analysis and a highly efficiency, mode-hopping [25] S. Saggini, D. T revisan, P. Mattavelli, and M. Ghioni, “Synchronous
DC–DC converter,” in Proc. Asia-Pacific Conf. on ASIC, Aug. 2002, asynchronous digital voltage-mode control for DC–DC converters,” IEEE
pp.153–156. Trans. Power Electron., vol. 22, no. 4, pp. 1261–1268, Jul. 2007.
[6] Vratislav Michal., “ Inductor Current Zero-Crossing Detector [26] Y. Panov and M.M. Jovanovic, “ Adaptive off-time control for variable
and CCM/DCM Boundary Detector for Integrated High-Current frequency, soft-switched flyback converter at light loads,” IEEE Trans.
Switched-Mode DC–DC Converters,” IEEE Trans. Power Electron, vol. Power Electron., vol. 17, no. 4, pp. 596–603, Jul. 2002.
29, no. 10, pp. 5384 - 5391, Oct. 2014. [27] L. Huber, B. T. Irving, and M. M. Jovanovic, “Effect of valley switching
[7] X. Wu, Z. Wang, and J. Zhang, “ Design considerations for dual-output and switching-frequency limitation on line-current distortions of
quasi-resonant flyback LED driver with current -sharing transformer,” DCM/CCM boundary boost PFC converters,” IEEE Trans. Power
IEEE Trans. Power Electron., vol. 28, no. 10, pp. 4820–4830, Oct. 2013. Electron., vol. 24, no. 2, pp. 339–347, Feb. 2009.
[8] Yu-Kang Lo; Chung-Yi Lin; Huang-Jen Chiu; Shih-Jen Cheng; [28] Chia-Hsing Li, Yu-Kang Lo, Huang-Jen Chiu and T ung Yen Chen,
Jing-Yuan Lin "Analysis and Design of a Push–Pull Quasi-Resonant “ Accurate power-loss estimation for continuous-current-conduction-mod
Boost Power Factor Corrector", IEEE Trans. Power Electron., Vol. 28, e synchronous Buck converters,” in Proc. Anti-Counterfeiting, Security
no. 1, pp.347 - 356, Jan. 2013. and Identification (ASID), Aug. 2012, pp.24–26.
[9] Chung-Chieh Fang, “Exact sampled-data analysis of quasi-resonant [29] “ Synchronous buck MOSFET loss calculations with Excel model,”
converters with finite filter inductance and capacitance,” International Fairchild semiconductor, Jon Klein, Power Management Applicat.
Journal of Circuit Theory and Applications, vol. 21, no. 6, pp. 49-63, Jan. AN-6005, 2014.
2002. [30] I. Pressman, Switching Power Supply Design, 2nd ed. ed. New York:
[10] S. Maity and Y. Suraj, “A fixed frequency dual-mode dc-dc buck McGraw- Hill, 1999.
converter with fast-transient response and high efficiency over a wide
load range,” in Proc. 28th Annu. IEEE APEC, 2013, pp. 415–420.
[11] M. D. Mulligan, B. Broach, and T . H. Lee, “A constant-frequency method
for improving light-load efficiency in synchronous buck converters,”
IEEE Power Electron Lett., vol. 3, no. 1, pp. 24–29, Mar. 2005.
[12] Y. Gao, S. Wang, H. Li, L. Chen, S. Fan, and L. Geng, “ A novel
zero-current-detector for DCM operation in synchronous converter,” in
Proc. IEEE Int. Symp. Ind. Electron., May 2012, pp. 99–104.
[13] X. Zhou, M. Donati, L. Amoroso, and F. C. Lee, “Improved light -load
efficiency for synchronous rectifier voltage regulator module,” IEEE
Trans. Power Electron., vol. 15, pp. 826–834, Sep. 2000.
[14] J.-M. Wang, S.-T . Wu, and G.-C. Jane, “ A novel control scheme of
synchronous buck converter for ZVS in light-load condition,”. IEEE
Trans. Power Electron.., vol. 26, no. 11, pp. 3265–3273, Nov. 2011.
[15] E. Adib and H. Farzanehfard, “Family of zero current zero voltage
transition PWM converters,” IET Power Electron., vol. 1, no. 2, pp. 214–
223, Jun. 2008.
[16] N. Z. Yahaya, K. M. Begam, and M. Awan, “Experimental analysis of a
new zero-voltage switching synchronous rectifier buck converter,” IET
Power Electron., vol. 4, no. 7, pp. 793–798, Aug. 2011.
[17] T. Mizoguchi, T . Ohgai, and T . Ninomiya, “ A family of single-switch
ZVS-CV DC-to-DC converters,” in Proc. IEEE Power Electron. Spec.
Conf., 1994, pp. 1392–1398.
[18] B. P. Divakar, K. W. E. Cheng, and D. Sutanto, “ Zero-voltage and zero
current switching buck-boost converter with low voltage and current
stresses,” IET Power Electron., vol. 1, no. 3, pp. 297–304, Sep. 2008.
[19] S. Urgun, “Zero-voltage transition-zero-current transition pulse width
modulation DC–DC buck converter with zero-voltage switching-zero
current switching auxiliary circuit,” IET Power Electron., vol. 5, no. 5, pp.
627–634, May 2012.

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