ATmega16 Microcontroller:

8-bit Microcontroller with 16K Bytes In-System Programmable Flash

Features
• High-performance, Low-power Atmel® AVR® 8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 × 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 16 Kbytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1 Kbyte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 2.7V - 5.5V for ATmega16L

– 4.5V - 5.5V for ATmega16

• Speed Grades

– 0 - 8 MHz for ATmega16L

– 0 - 16 MHz for ATmega16

• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L

– Active: 1.1 mA

– Idle Mode: 0.35 mA

– Power-down Mode: < 1 µA

Pin Configurations of ATmega16

Overview
The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Pin Descriptions
 Vcc - Digital supply voltage.
 GND - Ground.
 Port A (PA7..PA0) - Port A serves as the analog inputs to the A/D Converter. Port A also serves
as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive
characteristics with both high sink and source capability. When pins PA0 to PA7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are
activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock
is not running. 5 2466TS–AVR–07/10 ATmega16(L)
 Port B (PB7..PB0) - Port B is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port B output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
 Port C (PC7..PC0) - Port C is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port C output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition
becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up
resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
 Port D (PD7..PD0) - Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port D output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
 RESET - Reset Input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running.
 XTAL1 - Input to the inverting Oscillator amplifier and input to the internal clock operating
circuit.
 XTAL2 - Output from the inverting Oscillator amplifier.
 AVCC - AVCC is the supply voltage pin for Port A and the A/D Converter. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be
connected to VCC through a low-pass filter.
 AREF - AREF is the analog reference pin for the A/D Converter.