OutLine
• CMOS Fabrication Process
• Stick Diagrams
• Design Rules
1
CMOS Fabrication
Growing Silicon Ingot
Silicon Wafer
Silicon Ingot siliced
into Wafers
Wafer & Single Die
CMOS Cross Section
Complementary
p y metal–oxide–semiconductor ((CMOS))
Has many different uses:
Integrated Circuits
Data converters
Integrated transceivers
Image sensors
Logic circuits
CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• Lithography
g p y is a pprocess byy which a designed
g
layout of a microcircuit can be transformed on
to a wafer.
• O
On each step, different
ff materials are deposited or etched
• Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process
CMOS Fabrication
• Lithography is a process by which a designed
l
layoutt off a microcircuit
i i it can b
be ttransformed
f d on
to a wafer.
Mask
Inverter Cross-section
Cross section
• Typically
yp y use p
p-type
yp substrate for nMOS transistor
– Requires n-well for body of pMOS transistors
– Several alternatives: SOI, twin-tub, etc.
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
substrate tap well tap
Inverter Mask Set
• Transistors and wires are defined byy masks
• Cross-section taken along dashed line
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
Detailed Mask Views
• Six masks n wellll
– n-well
– Polysilicon Polysilicon
– n+ diffusion n+ Diffusion
– p+ diffusion p+ Diffusion
– Contact Contact
– Metal
M t l
Metal
Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse
ff n dopants into exposed wafer
f
– Strip off SiO2
p substrate
Oxidation
• Grow SiO2 on top
p of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Photoresist
• Spin
p on pphotoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2
p substrate
Lithography
• Expose
p p
photoresist through
g n-well mask
• Strip off exposed photoresist
Photoresist
SiO2
p substrate
Etch
• Etch oxide with hydrofluoric
y acid ((HF))
• Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
Strip Photoresist
• Strip
p off remaining
gpphotoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
SiO2
p substrate
N well
N-well
• n-well is formed with diffusion or ion implantation
p
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until Arsenic atoms diffuse into exposed Si
N well
N-well
• Ion Implanatation
p
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
Strip Oxide
• Strip
p off the remaining
g oxide using
g HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps
n well
p substrate
b t t
Polysilicon
• Deposit
p very
y thin layer
y of g
gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
P l ili
Thin gate oxide
n well
p substrate
Polysilicon Patterning
• Use same lithography
g p yp process to p
pattern p
polysilicon
y
Polysilicon
Polysilicon
P l ili
Thin gate oxide
n well
p substrate
Self-Aligned
Self Aligned Process
• Use oxide and masking g to expose
p where n+ dopants
p
should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
contact
t t
n well
p substrate
N diffusion
N-diffusion
• Pattern oxide and form n+ regions
g
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
N diffusion
N-diffusion
• Historicallyy dopants
p were diffused
• Usually ion implantation today
• But regions are still called diffusion
n+ n+ n+
n well
p substrate
N diffusion
N-diffusion
• Strip
p off oxide to complete
p p
patterning
g step
p
n+ n+ n+
n well
p substrate
P Diffusion
P-Diffusion
• Similar set of steps
p form p
p+ diffusion regions
g for p
pMOS
source and drain and substrate contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
Contacts
• Now we need to wire together
g the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
M e ta l
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
The Manufacturing Process
The Manufacturing Process (con’t)
Summary
• MOS Transistors are stack of g gate,, oxide,, silicon
• Can be viewed as electrically controlled switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors
• Now you know everything necessary to start designing
schematics and layout for a simple chip!
Stick Diagrams
Stick Diagrams
• Objectives:
j
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of stick
diagram.
– To learn how to draw stick diagrams for a given MOS
circuit.
circuit
Stick Diagrams
N+
N N+
N
Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
• Stick
Sti k diagrams
di convey layer
l i f
information
ti
through colour codes (or monochrome
encoding).
encoding)
• Acts as an interface between symbolic circuit
and the actual layout
layout.
Stick Diagrams
• Does show all components/vias
components/vias.
• It shows relative placement of components.
• G
Goes one step
t closer
l to
t the
th layout
l t
• Helps plan the layout and routing
A stick diagram is a cartoon of a layout
layout.
Stick Diagrams
• Does not show
– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub
boundaries.
– Any other low level details such as
parasitics..
Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
diff
Can also draw
in shades of
gray/line style.
style
Similarly for contacts, via, tub etc..
Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same
type cross or touch each other that
represents electrical contact.
Stick Diagrams – Some rules
Rule 2.
When ttwo or more ‘‘sticks’
Wh ti k ’ off diff
differentt type
t cross or touch
t h
each other there is no electrical contact.
(If electrical contact is needed we have to show the
connection explicitly).
Stick Diagrams – Some rules
Rule 3.
Wh a poly
When l crosses diff
diffusion
i iit
represents a transistor.
Note: If a contact is shown then it is not a transistor.
Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid touching
of p-diff with n-diff. All pMOS must lie on one side of
the line and all nMOS will have to be on the other side.
Stick Diagrams
VDD
VDD
X
X
x Stick x x
x Di
Diagra X
m
Gnd Gnd
Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
How to draw Stick Diagrams
Activity 2
• Sketch a stick diagram for a 4-input
4 input NOR
gate VDD A B C D
GND
Stick Diagrams
• Summary:
– What is stick diagram?
– Why stick diagram?
– Conventions and rules related to stick
diagram.
– Drawing stick diagrams
diagrams.
Design Rules
Why we need design rules
• Masks are tooling for manufacturing
manufacturing.
• Manufacturing processes have inherent
limitations in accuracy.
accuracy
• Design rules specify geometry of masks
which
hi h will
ill provide
id reasonable
bl yields.
i ld
• Design rules are determined by
experience.
Manufacturing problems
• Photoresist shrinkage
shrinkage, tearing
tearing.
• Variations in material deposition.
• V i ti
Variations iin ttemperature.
t
• Variations in oxide thickness.
• Impurities.
• Variations between lotslots.
• Variations across a wafer.
Transistor problems
• Varaiations in threshold voltage:
– oxide thickness;
– ion implanatation;
– poly variations.
• Ch
Changes iin source/drain
/d i diff
diffusion
i overlap.
l
• Variations in substrate.
MOSIS SCMOS design rules
• Designed to scale across a wide range of
technologies.
• Designed to support multiple vendors
vendors.
• Designed for educational use.
λ based design rules
• λ is the size of a minimum feature
feature.
• Specifying λ particularizes the scalable
rules.
rules
• Parasitics are generally not specified in
λ units.
it
Design Rules
• Typical rules:
– Minumum size
– Minimum spacing
– Alignment / overlap
– Composition
– Negative features
Types of Design Rules
• Scalable Design
g Rules ((e.g.
g SCMOS))
– Based on scalable “coarse grid” - λ (lambda)
– Idea: reduce λ value for each new process, but keep
rules
l th
the same
• Key advantage: portable layout
• Key disadvantage: not everything scales the same
– Not used in “real life”
• Absolute Design
g Rules
– Based on absolute distances (e.g. 0.75µm)
– Tuned to a specific process (details usually proprietary)
– Complex, especially for deep submicron
– Layouts not portable
SCMOS Design Rules
• Intended to be Scalable
– Original rules: SCMOS
– Submicron: SCMOS
SCMOS-SUBM
SUBM
– Deep Submicron: SCMOS-DEEP
• Authoritative
A th it ti Reference:
R f www.mosis.org
i
SCMOS Design Rule Summary
• Line size and spacing:
p g
– metal1: Minimum width=3λ, Minimum Spacing=3λ
3 metal 1
– metal2: Minimum width=3λ, Minimum Spacing=4λ
S
3 metal 2
SCMOS Design Rule Summary
–p
poly:
y Minimum width= 2λ,, Minimum Spacing=2λ
p g
2 poly
– ndiff/pdiff:
ff/ ff Minimum width= 3λ, Minimum Spacing=3λ,
S
minimum ndiff/pdiff seperation=10λ
3 pdiff/ndiff
Spacings
• Diffusion/diffusion: 4
• Poly/poly: 3
• P l /diff i
Poly/diffusion: 1
• Via/via: 2
• Metal1/metal1: 4
• Metal2/metal2: 4
Transistors
Transistors:
Min width=3λ
Min length=2λ
Design Rule Checking in
Magic
• Design violations
di l
displayedd as error paint
i t
• Find which rule is
violated with ":drc
:drc
why”
Poly must overhang
transistor by at
least 2 (MOSIS rule
#3.3)
CAD Tool Survey: Layout
Design
• Layout Editors
• Design Rule Checkers (DRC)
• Ci it E
Circuit Extractors
t t
• Layout vs. Schematic (LVS) Comparators
• Automatic Layout Tools
– Layout Generators
– ASIC: Place/Route for Standard Cells, Gate
Arrays
y
Layout Editors
• Goal: produce mask patterns for
fabrication
• Grid type:
– Absolute grid (MAX, LASI, LEdit, Mentor
ICStation Tanner Tools ,other
ICStation, other commercial
tools)
– Magic: lambda-based grid - easier to learn
learn,
but less powerful
Design Rule Checkers
• Goal: identify design rule violations
• Often a separate tool (built in to Magic)
• G
General l approach:
h ““scanline”
li ” algorithm
l ith
• Computationally intensive, especially for
large chips
