© KLMH

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 8 – Timing Closure

Original Authors:
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 1

Lienig
 Chapter 8 – Timing Closure

© KLMH
8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
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 8.1 Introduction

© KLMH
System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

Packaging and Testing

Chip

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 8.1 Introduction

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• IC layout must satisfy geometric constraints, electrical constraints,
power & thermal constraints as well as timing constraints
− Setup (long-path) constraints
− Hold (short-path) constraints

• Chip designers must complete timing closure

− Optimization process that meets timing constraints
− Integrates point optimizations discussed in previous chapters, e.g.,
placement and routing, with specialized methods to improve circuit performance

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 8.1 Introduction

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Components of timing closure covered in this lecture:

• Timing-driven placement (Sec. 8.3) minimizes signal delays

when assigning locations to circuit elements

• Timing-driven routing (Sec. 8.4) minimizes signal delays

when selecting routing topologies and specific routes

• Physical synthesis (Sec. 8.5) improves timing by changing the netlist

− Sizing transistors or gates: increasing the width:length ratio of transistors
to decrease the delay or increase the drive strength of a gate
− Inserting buffers into nets to decrease propagation delays
− Restructuring the circuit along its critical paths

• Performance-driven physical design flow (Sec. 8.6)

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 8.1 Introduction

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• Timing optimization engines must estimate circuit delays quickly and accurately
to improve circuit timing

• Timing optimizers adjust propagation delays through circuit components,

with the primary goal of satisfying timing constraints, including
− Setup (long-path) constraints, which specify the amount of time a data input signal
should be stable (steady) before the clock edge for each storage element
(e.g., flip-flop or latch)
− Hold-time (short-path) constraints, which specify the amount of time a data input
signal should be stable after the clock edge at each storage element

t cycle ≥ t combDelay + t setup + t skew t combDelay ≥ t hold + t skew

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 8.1 Introduction

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• Timing closure is the process of satisfying timing constraints
through layout optimizations and netlist modifications

• Industry jargon: “the design has closed timing”

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 8.2 Timing Analysis and Performance Constraints

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8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
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 8.2 Timing Analysis and Performance Constraints

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Sequential circuit, “unrolled” in time

Combinational Combinational Combinational

Logic FF Logic FF Logic FF
Copy 1 Copy 2 Copy 3

Clock

© 2011 Springer Verlag

Storage elements Combinational logic

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 9

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 8.2 Timing Analysis and Performance Constraints

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• Main delay concerns in sequential circuits
− Gate delays are due to gate transitions
− Wire delays are due to signal propagation along wires
− Clock skew is due to the difference in time the sequential elements activate

• Need to quickly estimate sequential circuit timing

− Perform static timing analysis (STA)
− Assume clock skew is negligible, postpone until after clock network synthesis

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 8.2.1 Static Timing Analysis

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• STA: assume worst-case scenario where every gate transitions

• Given combinational circuit, represent as directed acyclic graph (DAG)

− Every edge (node) has weight = wire (gate) delay

• Compute the slack = RAT – AAT for each node

− RAT is the required arrival time, latest time signal can transition
− AAT is the actual arrival time
− By convention, AAT is defined at the output of every node

⇒ Negative slack at any output means the circuit does not meet timing

⇒ Positive slack at all outputs means the circuit meets timing

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 8.2.1 Static Timing Analysis

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Combinational circuit as DAG
a (0.15)
y (2) (0.2)
w (2) (0.2) f
(0.1)
b (0.1) x (1) (0.3) (0.25)
z (2)
c (0.1)

a (0) (0.15) y (2)

(0) (0.1) (0.2)

s (0) b (0) (0.1) x (1) w (2) (0.2) f (0)

© 2011 Springer Verlag

(0.6) (0.3) (0.25)

c (0) (0.1) z (2)

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 8.2.1 Static Timing Analysis

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Compute AATs at each node:

AAT (v) = max ( AAT (u ) + t (u, v) )

u∈FI ( v )

where FI(v) is the fanin nodes, and t(u,v) is the delay between u and v
(AATs of inputs are given)

a (0) (0.15) y (2)

A0 A 3.2
(0) (0.1) (0.2)

s (0) b (0) (0.1) x (1) w (2) (0.2) f (0)

A0 A0 A 1.1 A 5.65 A 5.85
(0.6) (0.3) (0.25)

© 2011 Springer Verlag

c (0) (0.1) z (2)
A 0.6 A 3.4

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 8.2.1 Static Timing Analysis

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Compute RATs at each node:

RAT (v) = min (RAT (u ) − t (u, v) )

u∈FO ( v )

where FO(v) are the fanout nodes, and t(u,v) is the delay between u and v
(RATs of outputs are given)

a (0) (0.15) y (2)

R 0.95 R 3.1
(0) (0.1) (0.2)

s (0) b (0) (0.1) x (1) w (2) (0.2) f (0)

R -0.35 R -0.35 R 0.75 R 5.3 R 5.5
(0.6) (0.3) (0.25)

© 2011 Springer Verlag

c (0) (0.1) z (2)
R 0.95 R 3.05

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 8.2.1 Static Timing Analysis

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Compute slacks at each node:

slack (v) = RAT (v) − AAT (v)

a (0) (0.15) y (2)

A0 A 3.2
(0) R 0.95 (0.1) R 3.1 (0.2)
S 0.95 S -0.1

s (0) b (0) (0.1) x (1) w (2) (0.2) f (0)

A0 A0 A 1.1 A 5.65 A 5.85
R -0.35 (0.6) R -0.35 R 0.75 (0.3) (0.25) R 5.3 R 5.5
S -0.35 S -0.35 S -0.35 S -0.35 S -0.35

© 2011 Springer Verlag

c (0) (0.1) z (2)
A 0.6 A 3.4
R 0.95 R 3.05
S 0.35 S -0.35
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 15

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm

© KLMH
• Establish timing budgets for nets
− Gate and wire delays must be optimized during timing driven layout design
− Wire delays depend on wire lengths
− Wire lengths are not known until after placement and routing

• Delay budgeting with the zero-slack algorithm

− Let vi be the logic gates
− Let ei be the nets
− Let DELAY(v) and DELAY(e) be the delay of the gate and net, respectively
− Timing budget TB(v) of a gate corresponds to DELAY(v) + DELAY(e)

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm

© KLMH
Input: timing graph G(V,E)
Output: timing budgets TB for each v ∈ V
1. do
2. (AAT,RAT,slack) = STA(G)
3. foreach (vi ∈ V)
4. TB[vi] = DELAY(vi) + DELAY(ei)
5. slackmin = ∞
6. foreach (v ∈ V)
7. if ((slack[v] < slackmin) and (slack[v] > 0))
8. slackmin = slack[v]
9. vmin = v
10. if (slackmin ≠ ∞)
11. path = vmin
12. ADD_TO_FRONT(path,BACKWARD_PATH(vmin,G))
13. ADD_TO_BACK(path,FORWARD_PATH(vmin,G))
14. s = slackmin / |path|
15. for (i = 1 to |path|)
16. node = path[i] // evenly distribute
17. TB[node] = TB[node] + s // slack along path
18. while (slackmin ≠ ∞)
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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm

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Forward Path Search (FORWARD_PATH(vmin,G))
Input: node vmin with minimum slack slackmin, timing graph G
Output: maximal downstream path path from vmin such that no node v ∈ V affects
the slack of path
1. path = vmin
2. do
3. flag = false
4. node = LAST_ELEMENT(path)
5. foreach (fanout node fo of node)
6. if ((RAT[fo] == RAT[node] + TB[fo]) and (AAT[fo] == AAT[node] + TB[fo]))
7. ADD_TO_BACK(path,fo)
8. flag = true
9. break
10. while (flag == true)
11. REMOVE_FIRST_ELEMENT(path) // remove vmin

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm

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Backward Path Search (BACKWARD_PATH(vmin,G))
Input: node vmin with minimum slack slackmin, timing graph G
Output: maximal upstream path path from vmin such that no node v ∈ V affects the
slack of path
1. path = vmin
2. do
3. flag = false
4. node = FIRST_ELEMENT(path)
5. foreach (fanin node fi of node)
6. if ((RAT[fi] == RAT[node] – TB[fi]) and (AAT[fi] == AAT[node] – TB[fi]))
7. ADD_TO_FRONT(path,fi)
8. flag = true
9. break
10. while (flag == true)
11. REMOVE_LAST_ELEMENT(path) // remove vmin

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]

O1: <13,4,17>
<1,4,5> [0] O2: <6,8,14>
I1 <3,4,7> [0]
2
I2
<0,5,5> [0]
<7,4,11> [0] <13,4,17> [0]
4 O1
I3 6
<1,6,7> [0]

<6,8,14> [0]
3 0 O2
I4 <6,5,11> [0]
<3,5,8> [0]
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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

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• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum nonzero slack

O1: <13,4,17>
<1,4,5> [0] O2: <6,8,14>
I1 <3,4,7> [0]
2
I2
<0,5,5> [0]
<7,4,11> [0] <13,4,17> [0]
4 O1
I3 6
<1,6,7> [0]

<6,8,14> [0]
3 0 O2
I4 <6,5,11> [0]
<3,5,8> [0]
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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum slack
• Distribute the slacks and update the timing budgets

O1: <17,0,17>
<1,0,1> [1] O2: <6,8,14>
I1 <3,0,4> [1]
2
I2
<0,2,2> [0]
<9,0,9> [1] <16,0,16> [1]
4 O1
I3 6
<1,4,5> [0]

<6,8,14> [0]
3 0 O2
I4 <6,4,10> [0]
<3,4,7> [0]
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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum slack
• Distribute the slacks and update the timing budgets

O1: <17,0,17>
<1,0,1> [1] O2: <6,8,14>
I1 <4,0,4> [1]
2
I2
<0,0,0> [2]
<9,0,9> [1] <16,0,16> [1]
4 O1
I3 6
<1,4,5> [0]

<6,8,14> [0]
3 0 O2
I4 <6,4,10> [0]
<3,4,7> [0]
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 23

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum slack
• Distribute the slacks and update the timing budgets

O1: <16,0,16>
<1,0,1> [1] O2: <6,8,14>
I1 <4,0,4> [1]
2
I2
<0,0,0> [2]
<9,0,9> [1] <16,0,16> [1]
4 O1
I3 6
<1,2,3> [2]

<6,8,14> [0]
3 0 O2
I4 <6,2,8> [2]
<3,2,5> [0]
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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum slack
• Distribute the slacks and update the timing budgets

O1: <17,0,17>
<1,0,1> [1] O2: <10,4,14>
I1 <4,0,4> [1]
2
I2
<0,0,0> [2]
<9,0,9> [1] <16,0,16> [1]
4 O1
I3 6
<1,0,1> [3]

<10,4,14> [0]
3 0 O2
I4 <7,0,7> [3]
<3,1,4> [0]
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 25

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 8.2.2 Delay Budgeting with the Zero-Slack Algorithm Example

© KLMH
• Example: Use the zero-slack algorithm to distribute slack
• Format: <AAT, Slack, RAT>, [timing budget]
• Find the path with the minimum slack
• Distribute the slacks and update the timing budgets

O1: <17,0,17>
<1,0,1> [1] O2: <10,4,14>
I1 <4,0,4> [1]
2
I2
<0,0,0> [2]
<9,0,9> [1] <16,0,16> [1]
4 O1
I3 6
<1,0,1> [3]

<10,4,14> [4]
3 0 O2
I4 <7,0,7> [3]
<3,0,3> [1]
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 26

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 8.3 Timing-Driven Placement

© KLMH
8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
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 8.3 Timing-Driven Placement

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• Timing-driven placement optimizes circuit delay
to satisfy timing constraints
• Let T be the set of all timing endpoints

• Constraint satisfaction is measured by worst negative slack (WNS)

WNS = min(slack ( τ) )
τ∈Τ

• Or total negative slack (TNS)

TNS = ∑ slack (τ)
τ∈Τ, slack ( τ ) < 0

• Classifications: net-based, path-based, integrated

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 8.3.1 Net-Based Techniques

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• Net weights are added to each net – placer optimizes weighted wirelength

• Static net weights: computed before placement (never changes)

 ω1 if slack > 0
− Discrete net weights: w =  where ω1 > 0, ω2 > 0, and ω2 > ω1
ω
 2 if slack ≤ 0

α
 slack 
− Continuous net weights: w = 1 −  where t is the longest path delay
 t  and α is a criticality exponent

− Based on net sensitivity to TNS and slack

w = wo + α( slack target − slack ) ⋅ s wSLACK + β ⋅ s wTNS

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 8.3.1 Net-Based Techniques

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• Dynamic net weights: (re)computed during placement

− Estimate slack at every iteration: slack k = slack k −1 − s LDELAY ⋅ ∆L

where ∆L is the change in wirelength

1
 2 (υ k −1 + 1) if among the top 3% of critical nets
− Update net criticality: υ k = 
1
 υ k −1 otherwise
2

− Update net weight: wk = wk −1 ⋅ (1 + υ k )

• Variations include updating every j iterations, different relations

between criticality and net weight

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 8.3.2 Embedding STA into Linear Programs for Placement

© KLMH
• Construct a set of constraints for timing-driven placement
− Physical constraints define locations of cells
− Timing constraints define slack requirements

• Optimize an optimization objective

− Improving worst negative slack (WNS)
− Improving total negative slack (TNS)
− Improving a combination of both WNS and TNS

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 8.3.2 Embedding STA into Linear Programs for Placement

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• For physical constraints, let:
− xv and yv be the center of cell v ∈ V

− Ve be the set of cells connected to net e ∈ E

− left(e), right(e), bottom(e), and top(e) respectively be the coordinates

of the left, right, bottom, and top boundaries of e’s bounding box

− δx(v,e) and δy(v,e) be pin offsets from xv and yv for v’s pin connected to e

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 8.3.2 Embedding STA into Linear Programs for Placement

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• Then, for all v ∈ Ve:

left(e) ≤ xv + δ x (v, e)
right(e) ≥ xv + δ x (v, e)
bottom(e) ≤ yv + δ y (v, e)
top(e) ≥ yv + δ y (v, e)

• Define e’s half-perimeter wirelength (HPWL):

L(e) = right (e) − left (e) + top (e) − bottom (e)

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 8.3.2 Embedding STA into Linear Programs for Placement

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• For timing constraints, let
− tGATE(vi,vo) be the gate delay from an input pin vi to the output pin vo for cell v

− tNET(e,uo,vi) be net e’s delay from cell u’s output pin uo to cell v’s input pin vi

− AAT(vj) be the arrival time on pin j of cell v

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 8.3.2 Embedding STA into Linear Programs for Placement

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• For every input pin vi of cell v :

AAT (vi ) = AAT (u o ) + t NET (u o , vi )

• For every output pin vo of cell v :

AAT (vo ) ≥ AAT (vi ) + tGATE (vi , vo )

• For every pin τp in a sequential cell τ:

slack ( τ p ) ≤ RAT ( τ p ) − AAT ( τ p )

• Ensure that every slack(τp) ≤ 0

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 8.3.2 Embedding STA into Linear Programs for Placement

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• Optimize for total negative slack:
max : ∑ slack (τ
τ p ∈Pins ( τ ), τ∈Τ
p)

• Optimize for worst negative slack:

max : WNS

• Optimize а linear combination of multiple parameters:

min : ∑ L(e) − α ⋅ WNS

e∈E

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 8.4 Timing-Driven Routing

© KLMH
8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
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 8.4 Timing-Driven Routing

© KLMH
• Timing-driven routing seeks to minimize:
− Maximum sink delay: delay from the source to any sink in a net
− Total wirelength: routed length of the net

• For a signal net net, let

− s0 be the source node
− sinks = {s1, … ,sn} be the sinks
− G = (V,E) be a corresponding weighted graph where:
− V = {v0,v1, … ,vn} represents the source and sink nodes of net, and
− the weight of an edge e(vi,vj) ∈ E represents the routing cost between vi and vj

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 8.4 Timing-Driven Routing

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• For any spanning tree T over G, let:
− radius(T) be the length of the longest source-sink path in T
− cost(T) be the total edge weight of T

• Trade off between “shallow” and “light” trees

• “Shallow” trees have minimum radius

− Shortest-paths tree
− Constructed by Dijkstra’s Algorithm

• “Light” trees have minimum cost

− Minimum spanning tree (MST)
− Constructed by Prim’s Algorithm

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 39

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 8.4 Timing-Driven Routing

© KLMH
2 3 2
2
3 3
6 6
7
5 5 5
s0 s0 s0

radius(T) = 8 radius(T) = 13 radius(T) = 11

cost(T) = 20 cost(T) = 13 cost(T) = 16

© 2011 Springer Verlag

“Shallow” “Light” Tradeoff between
shallow and light

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 8.4.1 The Bounded-Radius, Bounded-Cost Algorithm

© KLMH
• Trades off radius for cost by setting upper bounds on both

• In the bounded-radius, bounded-cost (BRBC) algorithm, let:

− TS be the shortest-paths tree
− TM be the minimum spanning tree

• TBRBC is the tree constructed with parameter ε that satisfies:

radius (TBRBC ) ≤ (1 + ε ) ⋅ radius (TS )

and
 2
cost (TBRBC ) ≤ 1 +  ⋅ cost (TM )
 ε
• When ε = 0, TBRBC has minimum radius
• When ε = ∞, TBRBC has minimum cost
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 41

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 8.4.2 Prim-Dijkstra Tradeoff

© KLMH
• Prim-Dijkstra Tradeoff based on Prim’s algorithm and Dijkstra’s algorithm

• From the set of sinks S, iteratively add sink s based on different cost function

− Prim’s algorithm cost function: cost ( si , s j )

− Dijkstra’s algorithm cost function: cost ( s0 , si ) + cost ( si , s j )

− Prim-Dijkstra Tradeoff cost function: γ ⋅ cost ( s0 , si ) + cost ( si , s j )

• γ is a constant between 0 and 1

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 8.4.2 Prim-Dijkstra Tradeoff

© KLMH
4 4

7
11

8 8
7 7

9 s0 9 s0

radius(T) = 19 radius(T) = 15
cost(T) = 35 cost(T) = 39

© 2011 Springer Verlag

γ = 0.25 γ = 0.75

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 8.4.3 Minimization of Source-to-Sink Delay

© KLMH
• Iteratively forms a tree by adding sinks, and optimizes for critical sink(s)

• In the critical-sink routing tree (CSRT) problem, minimize:

n

∑ α(i) ⋅ t (s , s )
i =1
0 i

where α(i) are sink criticalities for sinks si, and t(s0,si) is the delay from s0 to si

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 8.4.3 Minimization of Source-to-Sink Delay

© KLMH
• In the critical-sink Steiner tree problem, construct a
minimum-cost Steiner tree T for all sinks except for the most critical sink sc

• Add in the critical sink by:

− H0: a single wire from sc to s0

− H1: the shortest possible wire that can join sc to T, so long as the path
from s0 to sc is the shortest possible total length

− HBest: try all shortest connections from sc to edges in T and from sc to s0.
Perform timing analysis on each of these trees and pick the one
with the lowest delay at sc

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 45

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 8.5 Physical Synthesis

© KLMH
8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 46

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 8.5 Physical Synthesis

© KLMH
• Physical synthesis is a collection of timing optimizations to fix negative slack

• Consists of creating timing budgets and performing timing corrections

• Timing budgets include:

− allocating target delays along paths or nets
− often during placement and routing stages
− can also be during timing correction operations

• Timing corrections include:

− gate sizing
− buffer insertion
− netlist restructuring

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 47

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 8.5.1 Gate Sizing

© KLMH
• Let a gate v have 3 sizes A, B, C, where: size (vC ) > size (v B ) > size (v A )

• Gate with a larger size has lower output resistance

• When load capacitances are large:

t ( vC ) < t ( v B ) < t ( v A )

• Gate with a smaller size has higher output resistance

• When load capacitances are small:

t ( vC ) > t ( v B ) > t ( v A )

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 8.5.1 Gate Sizing

© KLMH
• Let a gate v have 3 sizes A, B, C, where: size (vC ) > size (v B ) > size (v A )
40
40
35
35 33
30 30
30
25 27 A
24 28
Delay (ps)

25 23 26 27
21 B
24
20 18 C
20
15
15
10

© 2011 Springer Verlag

0.5 1.0 1.5 2.0 2.5 3.0
Load Capacitance (fF)
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 8.5.1 Gate Sizing

© KLMH
d C(d) = 1.5
a
v e C(e) = 1.0
b
f C(f) = 0.5

d C(d) = 1.5 d C(d) = 1.5

a a
vA e C(e) = 1.0 vC e C(e) = 1.0
b b
f C(f) = 0.5 f C(f) = 0.5

t(vA) = 40 t(vC) = 28

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 8.5.2 Buffering

© KLMH
• Buffer: a series of two serially-connected inverters

• Improve delays by
− speeding up the circuit or serving as delay elements
− changing transition times
− shielding capacitive load

• Drawbacks:
− Increased area usage
− Increased power consumption

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 8.5.2 Buffering

© KLMH
d C(d) = 1
d C(d) = 1
e C(e) = 1 e C(e) = 1
a a f C(f) = 1
vB f C(f) = 1 vB
b b g C(g) = 1
g C(g) = 1 y
C(vB) = 5 fF h C(h) = 1 C(vB) = 3 fF h C(h) = 1

t(vB) = 45 ps t(vB) = 33 ps

C(y) = 3 fF
t(y) = t(vB) + t(y) = 66 ps

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 8.5.3 Netlist Restructuring

© KLMH
• Netlist restructuring only changes existing gates, does not change functionality

• Changes include
− Cloning: duplicating gates
− Redesign of fanin or fanout tree: changing the topology of gates
− Swapping communicative pins: changing the connections
− Gate decomposition: e.g., changing AND-OR to NAND-NAND
− Boolean restructuring: e.g., applying Boolean laws to change circuit gates

• Can also do reverse transformations of above, e.g., downsizing, merging

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 8.5.3 Netlist Restructuring

© KLMH
• Cloning can reduce fanout capacitance

d C(d) = 1 a d C(d) = 1
e C(e) = 1 vA e C(e) = 1
a b
vB f C(f) = 1 f C(f) = 1
b
g C(g) = 1 vB g C(g) = 1
h C(h) = 1 h C(h) = 1

• and reduce downstream capacitance

d
d a
e v e
b
a

© 2011 Springer Verlag

v f f
b
… g
v’ … g
… h
h
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 54

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 8.5.3 Netlist Restructuring

© KLMH
Redesigning the fanin tree can change AATs

a <4> (1) a <4>

(1) f <5>
b <3>
(1) f <6> b <3> (1)
c <1> c <1>
(1) (1)
d <0> d <0>

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 55

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 8.5.3 Netlist Restructuring

© KLMH
Redesigning fanout trees can change delays on specific paths

path1
path1
y1 (1)

(1) (1)
(1) (1)

y2 (1) y2 (1)

path2 path2

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 56

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 8.5.3 Netlist Restructuring

© KLMH
Swapping commutative pins can change the final delay

a <0> (1) c <2> (1)

f <5> f <3>
(1) (1)
b <1> (1) b <1> (1)
c <2> (2) a <0> (2)

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 57

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 8.5.3 Netlist Restructuring

© KLMH
Gate decomposition can change the general structure of the circuit

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 58

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 8.5.3 Netlist Restructuring

© KLMH
Boolean restructuring uses laws or properties,
e.g., distributive law, to change circuit topology
(a + b)(a + c) = a + bc

a <4> a <4>
(1) (1) x <5>
b <1> b <1>
(1) x <6> (1)
c <2>
(1)
c <2>
(1) y <6> (1)

(1) (1) y <6>

© 2011 Springer Verlag

x(a,b,c) = (a + b)(a + c) x(a,b,c) = a + bc
y(a,b,c) = (a + c)(b + c) y(a,b,c) = ab + c

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 59

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 8.6 Performance-Driven Design Flow

© KLMH
8.1 Introduction
8.2 Timing Analysis and Performance Constraints
8.2.1 Static Timing Analysis
8.2.2 Delay Budgeting with the Zero-Slack Algorithm
8.3 Timing-Driven Placement
8.3.1 Net-Based Techniques
8.3.2 Embedding STA into Linear Programs for Placement
8.4 Timing-Driven Routing
8.4.1 The Bounded-Radius, Bounded-Cost Algorithm
8.4.2 Prim-Dijkstra Tradeoff
8.4.3 Minimization of Source-to-Sink Delay
8.5 Physical Synthesis
8.5.1 Gate Sizing
8.5.2 Buffering
8.5.3 Netlist Restructuring
8.6 Performance-Driven Design Flow
8.7 Conclusions
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 60

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 8.6 Performance-Driven Design Flow

© KLMH
Baseline Physical Design Flow

1. Floorplanning, I/O placement, power planning

2. Logic synthesis and technology mapping
3. Global placement and sequential element legalization
4. Clock network synthesis
5. Global routing and layer assignment
6. Congestion-driven detailed placement and legalization
7. Detailed routing
8. Design for manufacturing
9. Physical verification
10. Mask optimization and generation

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 8.6 Performance-Driven Design Flow

© KLMH
Floorplanning Example

Digital-to-Analog Converter
Analog Processing Video Video
Analog-to-Digital and Pre/Post-
processing Codec DSP Embedded
Control + DSP Controller for Protocol
Dataplane Processing
Audio Audio Processing
Pre/Post- Codec
processing

Baseband DSP Baseband Security

PHY MAC/Control

© 2011 Springer Verlag

Main Applications
Memory
CPU

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 8.6 Performance-Driven Design Flow

© KLMH
Global Placement Example

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 63

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 8.6 Performance-Driven Design Flow

© KLMH
Clock Network Synthesis Example

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 64

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 8.6 Performance-Driven Design Flow

© KLMH
Global Routing Congestion Example

© 2011 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 65

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 8.6 Performance-Driven Design Flow

© KLMH
Chip Planning and Logic Design
Performance-Driven Block Shaping, Sizing
I/O Placement
and Placement
Chip Planning
With Optional Net Weights
Performance-Driven
Single Global Net Routes
Block-Level Trial Synthesis and and Buffering
Delay Budgeting Floorplanning
fails
RTL
Logic Synthesis and Timing Estimation
Power Planning
Technology Mapping
passes

Block-level or Top-level Global Placement

© 2011 Springer Verlag

(see full flow chart in Figure 8.26)

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 8.6 Performance-Driven Design Flow

© KLMH
Block-level or Top-level Global Placement

Global Placement Obstacle-Avoiding Single

Global Net Topologies
With Optional Net Weights Physical Buffering

Delay Estimation OR Layer Assignment

Using Buffers
Virtual Buffering
fails Static Buffer Insertion
Timing Analysis
passes with
fixable violations
Physical Synthesis

© 2011 Springer Verlag

(see full flow chart in Figure 8.26)

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 8.6 Performance-Driven Design Flow

© KLMH
Physical Synthesis

Timing-Driven Boolean Restructuring

Timing Correction
Restructuring and Pin Swapping

AND
fails Static Redesign of Fanin
Timing Analysis Gate Sizing
and Fanout Trees
passes
Routing

© 2011 Springer Verlag

(see full flow chart in Figure 8.26)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 68

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 8.6 Performance-Driven Design Flow

© KLMH
Routing

Legalization of Global Routing

Clock Network Synthesis
Sequential Elements
With Layer Assignment

fails
Timing-driven
Static
Timing-Driven Routing Timing Analysis Legalization + Congestion-
passes
Driven Detailed Placement

(Re-)Buffering and 2.5D or 3D

Detailed Routing
Timing Correction Parasitic Extraction

Sign-off

© 2011 Springer Verlag

(see full flow chart in Figure 8.26)

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 8.6 Performance-Driven Design Flow

© KLMH
Sign-off
ECO Placement and Routing fails
fails Design Rule Checking
Manufacturability,
Static Timing Analysis Electrical, Reliability Layout vs. Schematic
passes
Verification
Antenna Effects
passes
Electrical Rule Checking
Mask Generation

© 2011 Springer Verlag

(see full flow chart in Figure 8.26)

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 Summary of Chapter 8 – Timing Constraints and Timing Analysis

© KLMH
• Circuit delay is measured on signal paths
− From primary inputs to sequential elements; from sequentials to primary outputs
− From sequentials to sequentials

• Components of path delay

− Gate delays: over-estimated by worst-case transition per gate
(to ensure fast Static Timing Analysis)
− Wire delays: depend on wire length and (for nets with >2 pins) topology

• Timing constraints
− Actual arrival times (AATs) at primary inputs and output pins of sequentials
− Required arrival times (RATs) at primary outputs and input pins of sequentials

• Static timing analysis

− Two linear-time traversals compute AATs and RATs for each gate (and net)
− At each timing point: slack = RAT-AAT
− Negative slack = timing violation; critical nets/gates are those with negative slack

• Time budgeting: divides prescribed circuit delay into net delay bounds

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 Summary of Chapter 8 – Timing-Driven Placement

© KLMH
• Gate/cell locations affect wire lengths, which affect net delays
• Timing-driven placement optimizes gate/cell locations to improve timing
− Interacts with timing analysis to identify critical nets, then biases placement opt.
− Must keep total wirelength low too, otherwise routing will fail
− Timing optimization may increase routing congestion

• Placement by net weighting

− The least invasive technique for timing-driven placement
− Performs tentative placement, then changes net weights based on timing analysis

• Placement by net budgeting

− Allocates delay bounds for each net; translates delay bounds into length bounds
− Performs placement subject to length constraints for individual nets

• Placement based on linear programming

− Placement is cast as a system of equations and inequalities
− Timing analysis and optimization are incorporated using additional inequalities

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 Summary of Chapter 8 – Timing-Driven Routing

© KLMH
• Timing-driven routing has several aspects
− Individual nets: trading longer wires for shorter source-to-sink paths
− Coupling capacitance and signal integrity: parallel wires act as capacitors
and can slow-down/speed-up signal transitions
− Full-netlist optimization: prioritize the nets that should be optimized first

• Individual net optimization

− One extreme: route each source-to-sink path independently (high wirelength)
− Another extreme: use a Minimum Spanning Tree (low wirenegth, high delay)
− Tunable tradeoff: a hybrid of Prim and Dijkstra algorithms

• Coupling capacitance and signal integrity

− Parallel wires are only worth attention when they transition at the same time
− Identify critical nets, push neighboring wires further away to limit crosstalk

• Full-netlist optimization
− Run trial routing, then run timing analysis to identify critical nets
− Then adjust accordingly, repeat until convergence

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 Summary of Chapter 8 – Physical Synthesis

© KLMH
• Traditionally, place-and-route have been performed after the netlist is known
• However, fixing gate sizes and net topologies early
does not account for placement-aware timing analysis
− Gate locations and net routes are not available

• Physical synthesis uses information from trial placement to modify the netlist
• Net buffering: splits a net into smaller (approx. equal length) segments
− A long net has high capacitance, the driver may be too weak

• Gate/buffer sizing: increases driver strength & physical size of a gate

− Large gates have higher input pin capacitance, but smaller driver resistance
− Larger gates can drive larger fanouts, longer nets; faster transitions
− Large gates require more space, larger upstream drivers

• Gate cloning: splits large fanouts

− Cloned gates can be placed separately, unlike with a single larger gate

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 8: Timing Closure 74

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