ARM Cortex M3

Dr Somashekar K
Professor
Dept. of ECE
 What Is the ARM Cortex-M3
Processor?
• The ARM Cortex™-M3 processor, the first of
the Cortex generation of processors released
by ARM in 2006, was primarily designed to
target the 32-bit microcontroller market.
• The Cortex-M3 processor provides excellent
performance at low gate count and comes
with many new features previously available
only in high-end processors.
 Why ARM Cortex – M3?
• Greater performance efficiency: allowing more
work to be done without increasing the
frequency or power requirements
• Low power consumption: enabling longer battery
life, especially critical in portable products
including wireless networking applications
• Enhanced determinism: guaranteeing that critical
tasks and interrupts are serviced as quickly as
possible and in a known number of cycles
 Why ARM Cortex – M3?
• Improved code density: ensuring that code fits in even the smallest
memory footprints
• Ease of use: providing easier programmability and debugging for the
growing number of 8-bit and 16-bit users migrating to 32 bits
• Lower cost solutions: reducing 32-bit-based system costs close to those
of legacy 8-bit and 16-bit devices and enabling low-end, 32-bit
microcontrollers to be priced at less than US$1 for the first time
• Wide choice of development tools: from low-cost or free compilers to
full-featured development suites from many development tool vendors
Cortex-M3 Processor versus Cortex-
M3-Based MCUs
 Cortex-M3 Processor versus Cortex-
M3-Based MCUs
• Cortex-M3 processor is the central processing
unit (CPU) of a microcontroller chip.
• In addition, a number of other components
are required for the whole Cortex-M3
processor-based microcontroller.
 The Thumb-2 Technology
• The Thumb-2 technology extended the Thumb Instruction Set Architecture
(ISA) into a highly efficient and powerful instruction set that delivers
significant benefits in terms of ease of use, code size, and performance.
• The extended instruction set in Thumb-2 is a superset of the previous 16-bit
Thumb instruction set, with additional 16-bit instructions alongside 32-bit
instructions.
• It allows more complex operations to be carried out in the Thumb state, thus
allowing higher efficiency by reducing the number of states switching
between ARM state and Thumb state.
 The Thumb-2 Technology
• Cortex-M3 supports only the Thumb-2 (and
traditional Thumb) instruction set. Instead of
using ARM instructions for some operations,
as in traditional ARM processors, it uses the
Thumb-2 instruction set for all operations.
 Cortex-M3 Processor Applications
• Low-cost microcontrollers
• Automotive
• Data communications
• Industrial control
• Consumer products
• There are already many Cortex-M3 processor-
based products in the market, including low-end
products priced as low as US $1, making the cost
of ARM microcontrollers comparable to or lower
than that of many 8-bit microcontrollers.
Cortex M3 Architecture
 Cortex M3 Architecture
• The Cortex™-M3 is a 32-bit microprocessor. It has
a 32-bit data path, a 32-bit register bank, and 32-
bit memory interfaces.
• The processor has a Harvard architecture, which
means that it has a separate instruction bus and
data bus.
• This allows instructions and data accesses to take
place at the same time, and as a result of this, the
performance of the processor increases because
data accesses do not affect the instruction
pipeline.
 Cortex M3 Architecture
• The instruction and data buses share the same
memory space (a unified memory system).
• In other words, you cannot get 8 GB of memory space
just because you have separate bus interfaces.
• For complex applications that require more memory
system features, the Cortex-M3 processor has an
optional Memory Protection Unit (MPU), and it is
possible to use an external cache if it’s required.
• Both little endian and big endian memory systems are
supported.
Registers
 Registers
• R0–R12: General-Purpose Registers
R0–R12 are 32-bit general-purpose registers
for data operations. Some 16-bit Thumb®
instructions can only access a subset of these
registers (low registers, R0–R7).
 Registers
• R13: Stack Pointers
• The Cortex-M3 contains two stack pointers (R13). They are banked so that
only one is visible at a time.
• The two stack pointers are as follows:
 Main Stack Pointer (MSP): The default stack pointer, used by the operating
system (OS) kernel and exception handlers
 Process Stack Pointer (PSP): Used by user application code
• The lowest 2 bits of the stack pointers are always 0, which means they are
always word aligned.
 Registers
• R14: The Link Register
When a subroutine is called, the return
address is stored in the link register.
• R15: The Program Counter
The program counter is the current program
address. This register can be written to control
the Program flow.
 Registers
• Special Registers
• The Cortex-M3 processor also has a number of
special registers.
 Program Status registers (PSRs)
 Interrupt Mask registers (PRIMASK, FAULTMASK,
and BASEPRI)
 Control register (CONTROL)
• These registers have special functions and can be
accessed only by special instructions. They cannot
be used for normal data processing.
Special Registers
Special Registers
 Operation Modes
• Cortex-M3 processor has two modes and two
privilege levels.
• The operation modes (thread mode and handler
mode) determine whether the processor is
running a normal program or running an
exception handler like an interrupt handler or
system exception handler.
• The privilege levels (privileged level and user
level) provide a mechanism for safeguarding
memory accesses to critical regions as well as
providing a basic security model.
Operation Modes
Operation Modes
 Built -In Nested Vectored Interrupt
Controller
• Features
Nested interrupt support
Vectored interrupt support
Dynamic priority changes support
Reduction of interrupt latency
Interrupt masking
 Nested interrupt support
• All the external interrupts and most of the system
exceptions can be programmed to different
priority levels.
• When an interrupt occurs, the NVIC compares the
priority of this interrupt to the current running
priority level.
• If the priority of the new interrupt is higher than
the current level, the interrupt handler of the
new interrupt will override the current running
task.
 Vectored interrupt support
• The Cortex-M3 processor has vectored
interrupt support.
• When an interrupt is accepted, the starting
address of the interrupt service routine (ISR) is
located from a vector table in memory.
• There is no need to use software to determine
and branch to the starting address of the ISR.
• Thus, it takes less time to process the
interrupt request.
Dynamic Priority Changes Support
• Priority levels of interrupts can be changed by
software during run time.
• Interrupts that are being serviced are blocked
from further activation until the ISR is
completed, so their priority can be changed
without risk of accidental reentry.
 Reduction of Interrupt Latency
• The Cortex-M3 processor also includes a
number of advanced features to lower the
interrupt latency.
• These include automatic saving and restoring
some register contents, reducing delay in
switching from one ISR to another, and
handling of late arrival interrupts.
 Interrupt Masking
• Interrupts and system exceptions can be
masked based on their priority level or
masked completely using the interrupt
masking registers BASEPRI, PRIMASK, and
FAULTMASK.
• They can be used to ensure that time-critical
tasks can be finished on time without being
interrupted.
The Memory Map
 The Memory Map
• The Cortex-M3 has a predefined memory map.
• This allows the built-in peripherals, such as the
interrupt controller and the debug components,
to be accessed by simple memory access
instructions.
• The Cortex-M3 design has an internal bus
infrastructure optimized for this memory usage.
• Data memory can still be put into the CODE
region, and program code can be executed from
an external Random Access Memory (RAM)
region.
 The Bus Interface
• There are several bus interfaces on the Cortex-
M3 processor.
• They allow the Cortex-M3 to carry instruction
fetches and data accesses at the same time.
Code memory buses
System bus
Private peripheral bus
 Code Memory Bus
• The code memory region access is carried out
on the code memory buses, which physically
consist of two buses, one called I-Code and
other called D-Code.
• These are optimized for instruction fetches for
best instruction execution speed.
 System Bus
• The system bus is used to access memory and
peripherals.
• This provides access to the Static Random
Access Memory (SRAM), peripherals, external
RAM, external devices, and part of the system
level memory regions.
 Private Bus
• The private peripheral bus provides access to
a part of the system-level memory dedicated
to private peripherals, such as debugging
components.
 The MPU
• The Cortex-M3 has an optional MPU.
• This unit allows access rules to be set up for
privileged access and user program access.
• When an access rule is violated, a fault
exception is generated, and the fault
exception handler will be able to analyze the
problem and correct it, if possible.
 The MPU
• The MPU can be used in various ways.
• In common scenarios, the OS can set up the MPU
to protect data use by the OS kernel and other
privileged processes to be protected from
untrusted user programs.
• The MPU can also be used to make memory
regions read-only, to prevent accidental erasing
of data or to isolate memory regions between
different tasks in a multitasking system.
• Overall, it can help make embedded systems
more robust and reliable.
 The Instruction Set
• The Cortex-M3 supports the Thumb-2
instruction set.
• This is one of the most important features of
the Cortex-M3 processor because it allows 32-
bit instructions and 16-bit instructions to be
used together for high code density and high
efficiency.
• It is flexible and powerful yet easy to use.
 Cortex-M3 Advantages
• No state switching overhead, saving both
execution time and instruction space.
• No need to separate ARM code and Thumb
code source files, making software
development and maintenance easier.
• It’s easier to get the best efficiency and
performance, in turn making it easier to write
software, because there is no need to worry
about switching.
ARM Disadvantage
Interrupt and Exceptions
 Debugging Support
• The Cortex-M3 processor includes a number of
debugging features such as program execution
controls:
 including halting
 stepping,
 instruction breakpoints,
 data watch-points,
 registers and memory accesses,
 traces.
 Link Register R14
• R14 is the link register (LR). Inside an assembly
program, you can write it as either R14 or LR.
LR is used to store the return program counter
(PC) when a subroutine or function is called—
for example, when you’re using the branch
and link (BL) instruction:
Link Register R14
 Link Register R14
• Despite the fact that bit 0 of the PC is always 0
(because instructions are word aligned or half
word aligned), the LR bit 0 is readable and
writable.
• This is because in the Thumb instruction set, bit 0
is often used to indicate ARM/Thumb states.
• To allow the Thumb-2 program for the Cortex-M3
to work with other ARM processors that support
the Thumb-2 technology, this least significant bit
(LSB) is writable and readable.
 Program Counter R15
• R15 is the PC. You can access it in assembler
code by either R15 or PC.
• Because of the pipelined nature of the Cortex-
M3 processor, when you read this register, you
will find that the value is different than the
location of the executing instruction, normally
by 4.
• 0x1000 : MOV R0, PC ; R0 = 0x1004
 Special Registers
• Program Status registers (PSRs)
• Interrupt Mask registers (PRIMASK,
FAULTMASK, and BASEPRI)
• Control register (CONTROL)
• Special registers can only be accessed via MSR
and MRS instructions; they do not have
memory addresses:
 Program Status Registers
• The PSRs are subdivided into three status
registers:
 Application Program Status register (APSR)
 Interrupt Program Status register (IPSR)
 Execution Program Status register (EPSR)
• The three PSRs can be accessed together or
separately using the special register access
instructions MSR and MRS.
• When they are accessed as a collective item, the
name xPSR is used.
Program Status Registers
 Program Status Registers

In ARM assembler, when accessing xPSR (all three PSRs as one), the symbol PSR is used:
 PRIMASK, FAULTMASK, and BASEPRI
Registers

a number of functions are available in the device driver libraries provided by the
microcontroller vendors
 PRIMASK, FAULTMASK, and BASEPRI
Registers
• In assembly language, the MRS and MSR
instructions are used. For example:
• The PRIMASK, FAULTMASK, and BASEPRI
registers cannot be set in the user access level.
 The Control Register
• The control register is used to define the privilege
level and the SP selection. This register has 2 bits.
• CONTROL[1]: In the Cortex-M3, the CONTROL[1]
bit is always 0 in handler mode. However, in the
thread or base level, it can be either 0 or 1.
• CONTROL[0]: The CONTROL[0] bit is writable only
in a privileged state. Once it enters the user state,
the only way to switch back to privileged is to
trigger an interrupt and change this in the
exception handler.
The Control Register
 Operation Mode

Switching of Operation Mode by Programming the Control Register or by

Exceptions.
 Operation Mode

Simple Applications Do Not Require User Access Level in Thread Mode.

Operation Mode

Switching Processor Mode at Interrupt.

 Operation Mode

Switching Processor Mode and Privilege Level

at Interrupt.
Exception Types in Cortex-M3
 Vector Tables
• When an exception event takes place on the
Cortex-M3 and is accepted by the processor core,
the corresponding exception handler is executed.
• The vector table is an array of word data inside
the system memory, each representing the
starting address of one exception type.
• The vector table is relocatable, and the relocation
is controlled by a relocation register in the NVIC.
• After reset, this relocation control register is reset
to 0; therefore, the vector table is located in
address 0x0 after reset.
Vector Table Definition after Reset
Cortex-M3 Stack Implementation

Stack Operation Basics: One Register in Each

Stack Operation.
Cortex-M3 Stack Implementation

Stack Operation Basics: Multiple Register Stack

Operation.
Cortex-M3 Stack Implementation

Stack Operation Basics: Combining Stack POP

and RETURN.
Cortex-M3 Stack Implementation

Cortex-M3 Stack PUSH Implementation.

The Two-Stack Model in the Cortex-
M3

CONTROL[1]=0: Both Thread Level and Handler

Use Main Stack.
The Two-Stack Model in the Cortex-
M3

CONTROL[1]=1: Thread Level Uses Process

Stack and Handler Uses Main Stack.
Reset Sequence

Initial Stack Pointer Value and

Initial Program Counter Value
Example.