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INA827
SBOS631B – JUNE 2012 – REVISED NOVEMBER 2017

INA827 Wide Supply Range, Rail-to-Rail Output

Instrumentation Amplifier With a Minimum Gain of 5
1 Features 3 Description
1• Eliminates Errors from External Resistors at Gain The INA827 is a low-cost instrumentation amplifier
of 5 (INA) that offers extremely low power consumption
and operates over a very wide single- or dual-supply
• Common-Mode Range Goes Below range. The device is optimized for the lowest possible
Negative Supply gain drift of only 1 ppm per degree Celsius in G = 5,
• Input Protection: Up to ±40 V which requires no external resistor. However, a single
• Rail-to-Rail Output external resistor sets any gain from 5 to 1000.
• Outstanding Precision: The INA827 is optimized to provide excellent
– Common-Mode Rejection: 88 dB, minimum common-mode rejection ratio (CMRR) of over 88 dB
(G = 5) over frequencies up to 5 kHz. In G = 5,
– Low Offset Voltage: 150 µV, maximum CMRR exceeds 88 dB across the full input common-
– Low Drift: 2.5 µV/°C, maximum mode range from the negative supply all the way up
– Low Gain Drift: 1 ppm/°C, max (G = 5 V/V) to 1 V of the positive supply. Using a rail-to-rail
output, the INA827 is well-suited for low-voltage
– Power-Supply Rejection: operation from a 3-V singlesupply as well as dual
100 dB, min (G = 5) supplies up to ±18 V. Additional circuitry protects the
– Noise: 17 nV/√Hz, G = 1000 V/V inputs against overvoltage of up to ±40 V beyond the
• High Bandwidth: power supplies by limiting the input currents to a save
level.
– G = 5: 600 kHz
– G = 100: 150 kHz The INA827 is available in a small VSSOP-8 package
and is specified for the –40°C to +125°C temperature
• Supply Current: 200 µA, typical range. For a similar instrumentation amplifier with a
• Supply Range: gain range of 1 V/V to 1000 V/V, see the INA826.
– Single Supply: 3 V to 36 V
Device Information(1)
– Dual Supply: ±1.5 V to ±18 V
PART NUMBER PACKAGE BODY SIZE (NOM)
• Specified Temperature Range:
INA827 VSSOP (8) 3.00 mm × 3.00 mm
–40°C to +125°C
(1) For all available packages, see the orderable addendum at
• Package: 8-pin VSSOP the end of the data sheet.

2 Applications Simplified Schematic

• Industrial Process Controls V+

• Multichannel Systems 0.1 mF

• Power Automation 8
• Weigh Scales
1
• Medical Instrumentation -IN 10 kW 50 kW
A1
• Data Acquisition VO = G ´ (VIN+ - VIN-)
2 80 kW
8 kW G=5+
RG
7
RG A3
8 kW +
3 Load VO
-
10 kW 50 kW
6
A2
4 REF
+IN
TI Device

5 0.1 mF

V-
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA827
SBOS631B – JUNE 2012 – REVISED NOVEMBER 2017 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 23
2 Applications ........................................................... 1 8 Application and Implementation ........................ 24
3 Description ............................................................. 1 8.1 Application Information............................................ 24
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 25
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 27
6 Specifications......................................................... 4 10 Layout................................................................... 27
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 27
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 27
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 28
6.4 Thermal Information .................................................. 4 11.1 Documentation Support ........................................ 28
6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 28
6.6 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 28
7 Detailed Description ............................................ 16 11.4 Trademarks ........................................................... 28
7.1 Overview ................................................................. 16 11.5 Electrostatic Discharge Caution ............................ 28
7.2 Functional Block Diagram ....................................... 16 11.6 Glossary ................................................................ 28
7.3 Feature Description................................................. 17 12 Mechanical, Packaging, and Orderable
Information ........................................................... 28

4 Revision History
Changes from Revision A (July 2013) to Revision B Page

• Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Overview section,
Functional Block Diagram section, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
• Deleted device graphic from top of page 1 ............................................................................................................................ 1
• Changed Features section: changed sub-bullets of Supply Range bullet ............................................................................. 1
• Changed MSOP to VSSOP throughout document ................................................................................................................ 1
• Changed single supply value in first paragraph of Description section ................................................................................. 1
• Added Simplified Schematic title ............................................................................................................................................ 1
• Deleted Package and Ordering Information table .................................................................................................................. 3
• Changed Pin Configuration and Functionssection: changed section title, changed Pin Functions title, added I/O column .. 3
• Changed test conditions of Input, PSRR and VCM parameters in Electrical Characteristics table ........................................ 5
• Changed minimum specifications of Power Supply, VS parameter in Electrical Characteristics table .................................. 6
• Changed Typical Characteristics section: moved conditions from title to conditions line under curve .................................. 7
• Changed conditions of Figure 7 and Figure 8 ........................................................................................................................ 8
• Changed conditions of Figure 37 and Figure 38 .................................................................................................................. 13
• Changed power-supply range in Operating Voltage section ............................................................................................... 22
• Changed power supply low level in Low-Voltage Operation section ................................................................................... 22
• Added Design Requirements, Detailed Design Procedure, and Application Curves to the Typical Application section ..... 25

Changes from Original (June 2012) to Revision A Page

• Changed front-page graphic................................................................................................................................................... 1

• Updated Figure 15.................................................................................................................................................................. 8
• Updated Figure 16.................................................................................................................................................................. 8
• Updated Figure 61................................................................................................................................................................ 24

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5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View

-IN 1 8 +VS

RG 2 7 VOUT

RG 3 6 REF

+IN 4 5 -VS

Pin Functions
NAME NO. I/O DESCRIPTION
–IN 1 I Negative input
+IN 4 I Positive input
REF 6 I Reference input. This pin must be driven by low impedance.
RG 2, 3 — Gain setting pin. Place a gain resistor between pin 2 and pin 3.
VOUT 7 O Output
–VS 5 — Negative supply
+VS 8 — Positive supply

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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply –20 20
Voltage V
Input –40 40
REF input –20 20 V
(2)
Output short-circuit Continuous
Operating, TA –55 150
Temperature range Junction, TJ 175 °C
Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single supply 3 36
Supply voltage V
Dual supply ±1.5 ±18
Specified temperature –40 125 °C
Operating temperature –50 150 °C

6.4 Thermal Information

INA827
(1)
THERMAL METRIC DGK (VSSOP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 215.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.3 °C/W
RθJB Junction-to-board thermal resistance 97.8 °C/W
ψJT Junction-to-top characterization parameter 10.5 °C/W
ψJB Junction-to-board characterization parameter 96.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
RTI, VOS = VOSI + (VOSO / G) 40 150 µV
VOSI Input stage
TA = –40°C to +125°C 0.5 2.5 µV/°C
Offset voltage (1)
RTI, VOS = VOSI + (VOSO / G) 500 2000 µV
VOSO Output stage
TA = –40°C to +125°C 5 30 µV/°C
G = 5, VS = ±1.5 V to ±18 V 100 120
PSRR Power-supply rejection ratio G = 10, VS = ±1.5 V to ±18 V 106 126 dB
G > 100, VS = ±1.5 V to ±18 V 120 140
Differential 2 || 1
ZIN Impedance GΩ || pF
Common-mode 10 || 5
RFI filter, –3-dB frequency 25 MHz
VS = ±1.5 V to ±18 V, VO = 0 V (V–) – 0.2 (V+) – 0.9
VCM Operating input range (2) VS = ±1.5 V to ±18 V, VO = 0 V, TA = +125°C (V–) – 0.05 (V+) – 0.8 V
VS = ±1.5 V to ±18 V, VO = 0 V, TA = –40°C (V–) – 0.3 (V+) – 0.95
Input overvoltage range TA = –40°C to +125°C (V+) – 40 (V–) + 40 V
G = 5, VCM = V– to (V+) – 1 V 88 100
DC to 60 Hz G = 10, VCM = V– to (V+) – 1 V 94 106
G > 100, VCM = V– to (V+) – 1 V 110 126
CMRR Common-mode rejection ratio dB
G = 5, VCM = V– to (V+) – 1 V 88
At 5 kHz G = 10, VCM = V– to (V+) – 1 V 94
G > 100, VCM = V– to (V+) – 1 V 104
BIAS CURRENT
35 50
IB Input bias current nA
TA = –40°C to +125°C 95
–5 0.7 5
IOS Input offset current nA
TA = –40°C to +125°C 10
NOISE VOLTAGE (3)
eNI Input f = 1 kHz, G = 1000, RS = 0 Ω 17 18
Voltage noise nV/√Hz
eNO Output f = 1 kHz, G = 5, RS = 0 Ω 250 285
G = 5, fB = 0.1 Hz to 10 Hz, RS = 0 Ω 1.4
RTI Referred-to-input µVPP
G = 1000, fB = 0.1 Hz to 10 Hz, RS = 0 Ω 0.5
f = 1 kHz 120 fA/√Hz
iN Noise current
fB = 0.1 Hz to 10 Hz 5 pAPP
GAIN

80 kW
G Gain equation 5+ V/V
RG

G Range of gain 5 1000 V/V

G = 5, VO = ±10 V ±0.005% ±0.035%
GE Gain error
G = 10 to 1000, VO = ±10 V ±0.1% ±0.4%
G = 5, TA = –40°C to +125°C ±0.1 ±1
Gain versus temperature (4) ppm/°C
G > 5, TA = –40°C to +125°C 8 25
G = 5 to 100, VO = –10 V to +10 V, RL = 10 kΩ 2 5
Gain nonlinearity ppm
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ 20 50

(1) Total offset, referred-to-input (RTI): VOS = VOSI + (VOSO / G).

(2) Input voltage range of the INA827 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See the Typical Characteristics section for more information.
(3)
eNO 2
(eNI)2 +
G
Total RTI voltage noise = .
(4) The values specified for G > 5 do not include the effects of the external gain-setting resistor, RG.

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Electrical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
Voltage swing RL = 10 kΩ (V–) + 0.1 (V+) – 0.15 V
Load capacitance stability 1000 pF
Short-circuit current Continuous to common ±16 mA
FREQUENCY RESPONSE
G=5 600
G = 10 530
BW Bandwidth, –3 dB kHz
G = 100 150
G = 1000 15
G = 5, VO = ±14.5 V 1.5
SR Slew rate V/µs
G = 100, VO = ±14.5 V 1.5
G = 5, VSTEP = 10 V 10
To 0.01% G = 100, VSTEP = 10 V 12
G = 1000, VSTEP = 10 V 95
tS Settling time µs
G = 1, VSTEP = 10 V 11
To 0.001% G = 100, VSTEP = 10 V 18
G = 1000, VSTEP = 10 V 118
REFERENCE INPUT
RIN Input impedance 60 kΩ
Voltage range V– V+ V
Gain to output 1 V/V
Reference gain error 0.01 %
POWER SUPPLY
Single 3.0 36
VS Power-supply voltage V
Dual ±1.5 ±18
VIN = 0 V 200 250
IQ Quiescent current µA
TA = –40°C to +125°C 250 320
TEMPERATURE RANGE
Specified –40 125 °C
Operating –50 150 °C
θJA Thermal resistance 215 °C/W

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6.6 Typical Characteristics

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)

250 30
SD: 40.1 µV SD: 0.51 µV/°C
MEAN: −7.6 µV MEAN: 0.08 µV/°C
25
200

20
150
Units

Units
15
100
10

50
5

0 0
−150
−130
−110
−90
−70
−50
−30
−10
10
30
50
70
90
110
130
150

−3

−2

−1

3
VOSI (µV) G001
VOSI Drift (µV/°C ) G002

Figure 1. Typical Distribution of Input Offset Voltage Figure 2. Typical Distribution of Input Offset Voltage Drift
200 16
SD: 5.3 µV/°C
MEAN: −7.7 µV/°C
160
12

120
Units

Units

8
80

4
40

0 0
−2000
−1800
−1600
−1400
−1200
−1000
−800
−600
−400
−200
0
200
400
600
800
1000
1200
1400
1600
1800
2000

−25

−20

−15

−10

−5

10

15

20

25
VOSO (µV) G002
VOSO Drift (µV/°C ) G004

Figure 3. Typical Distribution of Output Offset Voltage Figure 4. Typical Distribution of Output Offset Voltage Drift
700 500
SD: 0.59 nA
600 MEAN: 0.01 nA
400
500

300
400
Units

Units

300
200

200
100
100

0 0
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4

IB (nA) G005 IOS (nA) G006

Figure 5. Typical Distribution of Input Bias Current Figure 6. Typical Distribution of Input Offset Current

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)

Single supply, VS = +3 V, G = 5 Single supply, VS = +3 V, G = 100

Figure 7. Input Common-Mode Voltage vs Output Voltage Figure 8. Input Common-Mode Voltage vs Output Voltage
4.5 4.5
Common−Mode Voltage (V)

3.5 Common−Mode Voltage (V) 3.5

2.5 2.5
Vref = 0V Vref = 0V
Vref = 2.5V Vref = 2.5V
1.5 1.5

0.5 0.5

−0.5 −0.5
−0.5 0.5 1.5 2.5 3.5 4.5 5.5 −0.5 0.5 1.5 2.5 3.5 4.5 5.5
Output Voltage (V) G009
Output Voltage (V) G009

Single supply, VS = +5 V, G = 5 Single supply, VS = +5 V, G = 100

Figure 9. Input Common-Mode Voltage vs Output Voltage Figure 10. Input Common-Mode Voltage vs Output Voltage
6 16

12
4
Common−Mode Voltage (V)

Common−Mode Voltage (V)

8
Vs = +/− 12V
2 Gain = 5 4 Vs = +/− 15V
Gain = 100
0 0

−4
−2
−8
−4
−12

−6 −16
−6 −4 −2 0 2 4 6 −16 −12 −8 −4 0 4 8 12 16
Output Voltage (V) G011
Output Voltage (V) G012

Dual supply, VS = ±5 V Dual supply, VS = ±15 V, ±12 V, G = 5

Figure 11. Input Common-Mode Voltage vs Output Voltage Figure 12. Input Common-Mode Voltage vs Output Voltage

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
16 8 16

12 6 12
Common−Mode Voltage (V)

8 4 8

Input Current (mA)

Output Voltage (V)

Vs = +/− 12V
4 Vs = +/− 15V 2 4

0 0 0

−4 −2 −4
IIN
−8 −4 VOUT −8

−6 −12
−12
−8 −16
−16 −30 −20 −10 0 10 20 30
−16 −12 −8 −4 0 4 8 12 16
Input Voltage (V)
Output Voltage (V) G013
G014

G = 1, VS = ±15 V
Dual supply, VS = ±15 V, ±12 V, G = 100
Figure 14. Input Overvoltage vs Input Current
Figure 13. Input Common-Mode Voltage vs Output Voltage
160 140

Common-Mode Rejection Ratio (dB)

Common-Mode Rejection Ratio (dB)

140 120
120
100
100
80
80
60
60
G=5
40
40 G=5 G = 10
G = 10
20 20 G = 100
G = 100
G = 1000 G = 1000
0 0
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) C015 Frequency (Hz) C016

1-kΩ source imbalance

Figure 15. CMRR vs Frequency (RTI) Figure 16. CMRR vs Frequency (RTI)
180 180
160 160
140 140
120 120
PSRR (dB)

PSRR (dB)

100 100
80 80
60 60
G=5 G=5
40 G = 10 40 G = 10
20 G = 100 20 G = 100
G = 1000 G = 1000
0 0
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) G018
Frequency (Hz) G019

Figure 17. Positive PSRR vs Frequency (RTI) Figure 18. Negative PSRR vs Frequency (RTI)

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
70 10k
G=5 G=5
60
G = 10 G = 10
50 G = 100 G = 100

Noise Density (nV/ Hz)

G = 1000 1k G = 1000
40
30
Gain (dB)

20 100
10
0
10
−10
−20
−30 1
100 1k 10k 100k 1M 10M 100m 1 10 100 1k 10k 100k
Frequency (Hz) G022
Frequency (Hz) G023

Figure 19. Gain vs Frequency Figure 20. Voltage Noise Spectral Density vs Frequency
(RTI)
500
Current Noise Density (fA/ Hz)

400
Noise (1 mV/div)

300

200

100

0
1 10 100 1k 10k
Time (1 s/div)
Frequency (Hz) G024 G025

Figure 21. Current Noise Spectral Density vs Frequency Figure 22. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 5)
(RTI)
Noise (500 nV/div)

Noise (2 pA/div)

Time (1 s/div) Time (1 s/div)

G026 G027

Figure 23. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000) Figure 24. 0.1-Hz to 10-Hz RTI Current Noise

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
100
140 −45°C −45°C
90
25°C 25°C
120 85°C 80 85°C
Input Bias Current (nA)

Input Bias Current (nA)

125°C 125°C
70
100
60
80
50
60 40
30
40
20
20
10
0 0
−0.5 0.0 0.5 1.0 1.5 2.0 2.5 −18 −14 −10 −6 −2 2 6 10 14 18
Common−Mode Voltage (V) G028
Common−Mode Voltage (V) G029

VS = +2.7 V VS = ±15 V

Figure 25. Input Bias Current vs Common-Mode Voltage Figure 26. Input Bias Current vs Common-Mode Voltage
100 2.5
Unit 1 Unit 1
Unit 2 2 Unit 2
80 Unit 3

Input Offset Current (nA)

Input Bias Current (nA)

1.5

60
1

0.5
40

0
20
−0.5

0 −1
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (°C) G030
Temperature (°C) G031

Figure 27. Input Bias Current vs Temperature Figure 28. Input Offset Current vs Temperature
50 300
Unit 1 Unit 1
40
Unit 2 Unit 2
30 Unit 3 Unit 3
Quiescent Current (µA)

250
20
Gain Error (ppm)

10
0 200
−10
−20
150
−30
−40
−50 100
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
Temperature (°C) G032
Temperature (°C) G034

Figure 29. Gain Error vs Temperature (G = 5) Figure 30. Supply Current vs Temperature

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
10 10
8 8
6 6
Non−Linearity (ppm)

Non−Linearity (ppm)
4 4
2 2
0 0
−2 −2
−4 −4
−6 −6
−8 −8
−10 −10
−10 −8 −6 −4 −2 0 2 4 6 8 10 −10 −8 −6 −4 −2 0 2 4 6 8 10
Output Voltage (V) G035
Output Voltage (V) G036

Figure 31. Gain Nonlinearity (G = 5) Figure 32. Gain Nonlinearity (G = 10)

10 50
8 40
6 30
Non−Linearity (ppm)

4 Non−Linearity (ppm) 20
2 10
0 0
−2 −10
−4 −20
−6 −30
−8 −40
−10 −50
−10 −8 −6 −4 −2 0 2 4 6 8 10 −10 −8 −6 −4 −2 0 2 4 6 8 10
Output Voltage (V) G037
Output Voltage (V) G038

Figure 33. Gain Nonlinearity (G = 100) Figure 34. Gain Nonlinearity (G = 1000)
80 100
VS = ±15 V −45°C VS = ±15 V −45°C
60 80
25°C 25°C
85°C 60 85°C
40 125°C 125°C
Offset Voltage (µV)

Offset Voltage (µV)

40
20 20
0 0

−20 −20
−40
−40
−60
−60 −80
−80 −100
−15.5 −15 −14.5 13.5 14 14.5
Common−Mode Voltage (V) G057
Common−Mode Voltage (V) G058

VS = ±15 V VS = ±15 V

Figure 35. Offset Voltage vs Figure 36. Offset Voltage vs

Negative Common-Mode Voltage Positive Common-Mode Voltage

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)

VS = +3 V VS = +3 V

Figure 37. Offset Voltage vs Figure 38. Offset Voltage vs

Negative Common-Mode Voltage Positive Common-Mode Voltage
15 −14
−45°C −45°C
14.9 −14.1
25°C 25°C
14.8 85°C −14.2 85°C
125°C 125°C
Output Voltage (V)

Output Voltage (V)

14.7 −14.3
14.6 −14.4
14.5 −14.5
14.4 −14.6
14.3 −14.7
14.2 −14.8
14.1 −14.9
14 −15
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Output Current (mA) G039
Output Current (mA) G040

VS = ±15 V VS = ±15 V

Figure 39. Positive Output Voltage Swing vs Figure 40. Negative Output Voltage Swing vs
Output Current Output Current
35 20
Vs = ±15V Settle to 0.01%
18
30 Vs = ±2.5V Settle to 0.001%
16
Output Voltage (Vpp)

25 14
Settling Time (µs)

12
20
10
15
8

10 6
4
5
2
0 0
1k 10k 100k 1M 2 4 6 8 10 12 14 16 18 20
Frequency (Hz) G043
Step Size (V) G044

VS = ±15 V

Figure 41. Large-Signal Frequency Response Figure 42. Settling Time vs Step Size

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
0.2

Output Voltage (10 mV/div)

0.1
Output Voltage (V)

CL = 0 pF
CL = 100 pF
CL = 220 pF
0 CL = 500 pF
CL = 1 nF
CL = 220 nF
−0.1

−0.2
Time (5 ms/div) Time (5 ms/div)
G046
G045
G = 5, RL = 1 kΩ, CL = 100 pF

Figure 43. Small-Signal Response Over Capacitive Loads Figure 44. Small-Signal Response
(G = 5)
Output Voltage (10 mV/div)

Output Voltage (10 mV/div)

Time (5 ms/div) Time (20 ms/div)

G052 G053

G = 10, RL = 10 kΩ, CL = 100 pF G = 100, RL = 10 kΩ, CL = 100 pF

Figure 45. Small-Signal Response Figure 46. Small-Signal Response

Output Voltage
Output Settling

Output Settling (0.002%/div)

Output Voltage (10 mV/div)

Output Voltage (5 V/div)

Time (100 ms/div) Time (50 ms/div)

G054 G061

G = 1000, RL = 10 kΩ, CL = 100 pF G = 5, RL = 10 kΩ, CL = 100 pF

Figure 47. Small-Signal Response Figure 48. Large-Signal Response and Settling Time

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Typical Characteristics (continued)

at TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5 (unless otherwise noted)
Output Voltage Output Voltage
Output Settling Output Settling

Output Settling (0.002%/div)

Output Settling (0.002%/div)

Output Voltage (5 V/div)

Output Voltage (5 V/div)

Time (50 ms/div) Time (50 ms/div)
G062 G063

G = 10, RL = 10 kΩ, CL = 100 pF G = 100, RL = 10 kΩ, CL = 100 pF

Figure 49. Large-Signal Response and Settling Time Figure 50. Large-Signal Response and Settling Time
10M
Output Voltage
Output Settling
Output Settling (0.002 %/div)

1M
Output Voltage (5 V/div)

Impedance (Ω)
100k

10k

1k

100
1m 10m 100m 1 10 100 1k 10k 100k 1M 10M
Time (100 ms/div) Frequency (Hz)
G064 G055

G = 1000, RL = 10 kΩ, CL = 100 pF

Figure 51. Large-Signal Response and Settling Time Figure 52. Open-Loop Output Impedance
5
4
3
Offset Voltage (µV)

2
1
0
−1
−2
−3
−4
−5
0 40 80 120 160 200
Time (s) G056

Figure 53. Change In Input Offset Voltage vs Warm-Up Time

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7 Detailed Description

7.1 Overview
The INA827 is a monolithic instrumentation amplifier (INA) based on a 36-V and a current feedback input
architecture. The INA827 also integrates laser-trimmed resistors to ensure excellent common mode rejection and
low gain error. The combination of the current feedback input and the precision resistors allows this device to
achieve outstanding dc precision as well as frequency response and high frequency common mode
rejection(TBD this is more like a Layout text. Overview is generally an overview of the device.)
The Overview section provides a top-level description of what the device is and what it does. Detailed
descriptions of the features and functions appear in subsequent subsections. Guidelines ● Include a summary of
standards met by the device (if any). ● List modes and states of operation (from the user's perspective) and key
features within each functional mode for quick reference. Use the following sections to provide detail on these
modes and features.

7.2 Functional Block Diagram

V+

0.1 mF

1
-IN 10 kW 50 kW
A1
VO = G ´ (VIN+ - VIN-)
2 80 kW
8 kW G=5+
RG
7
RG A3
8 kW +
3 Load VO
-
10 kW 50 kW
6
A2
4 REF
+IN
TI Device

5 0.1 mF

V-
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Figure 54. INA827 Block Diagram

Figure 55. Simplified Block Diagram (TBD only simplified op amp goes here but this is a PNG and I can't
edit it)

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7.3 Feature Description

7.3.1 Setting the Gain
Device gain is set by a single external resistor (RG), connected between pins 2 and 3. The value of RG is
selected according to Equation 1:
80 kW
5+
RG (1)
Table 1 lists several commonly-used gains and resistor values. The on-chip resistors are laser-trimmed to
accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain
accuracy and drift specifications of the INA827.

Table 1. Commonly-Used Gains and Resistor Values

DESIRED GAIN (V/V) RG (Ω) NEAREST 1% RG (Ω)
5 — —
10 16.00k 15.8k
20 5.333k 5.36k
50 1.778k 1.78k
100 842.1 845
200 410.3 412
500 161.6 162
1000 80.40 80.6

7.3.1.1 Gain Drift

The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The RG contribution
to gain accuracy and drift can be directly inferred from the gain of Equation 1.
The best gain drift of 1 ppm per degree Celsius can be achieved when the INA827 uses G = 5 without RG
connected. In this case, the gain drift is limited only by the slight temperature coefficient mismatch of the
integrated 50-kΩ resistors in the differential amplifier (A3). At gains greater than 5, the gain drift increases as a
result of the individual drift of the resistors in the feedback of A1 and A2, relative to the drift of the external gain
resistor RG. Process improvements to the temperature coefficient of the feedback resistors now enable a
maximum gain drift of the feedback resistors to be specified at 35 ppm per degree Celsius, thus significantly
improving the overall temperature stability of applications using gains greater than 5.
Low resistor values required for high gains can make wiring resistance important. Sockets add to wiring
resistance and contribute additional gain error (such as possible unstable gain errors) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitances greater than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see the Typical
Characteristics section.

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7.3.2 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 56 shows an optional circuit for trimming the output offset voltage. The
voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF
pin to preserve good common-mode rejection.

VIN-
V+
RG INA827 VO
100 mA
REF 1/2 REF200
VIN+

100 W
OPA333
±10 mV 10 kW
Adjustment Range
100 W

100 mA
1/2 REF200

V-
Copyright © 2016, Texas Instruments Incorporated

Figure 56. Optional Trimming of Output Offset Voltage

7.3.3 Input Common-Mode Range

The linear input voltage range of the INA827 input circuitry extends from the negative supply voltage to 1 V
below the positive supply, and maintains 88-dB (minimum) common-mode rejection throughout this range. The
common-mode range for most common operating conditions is described in Figure 14 and Figure 35 through
Figure 38. The INA827 can operate over a wide range of power supplies and VREF configurations, thus making a
comprehensive guide to common-mode range limits for all possible conditions impractical to provide.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see Figure 57) provides a check for the most common overload conditions. The A1 and A2 designs are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 can continue to be in linear operation and responding to changes in the
noninverting input voltage. This difference can give the appearance of linear operation but the output voltage is
invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA827 employs a current-feedback topology with PNP input
transistors; see Figure 57. The matched PNP transistors (Q1 and Q2) shift the input voltages of both inputs up by
a diode drop and (through the feedback network) shift the output of A1 and A2 by approximately +0.8 V. With
both inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the
linear range, allowing differential measurements to be made at the GND level. As a result of this input level-
shifting, the voltages at pins 2 and 3 are not equal to the respective input pin voltages (pins 1 and 4). For most
applications, this inequality is not important because only the gain-setting resistor connects to these pins.

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7.3.4 Inside the INA827

See Figure 61 for a simplified representation of the INA827. A more detailed diagram (shown in Figure 57)
provides additional insight into the INA827 operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions and preserve excellent noise performance. When excessive voltage is applied, these transistors
limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is applied across RG, causing a signal current to flow
through RG, R1, and R2. The output difference amplifier (A3) removes the common-mode component of the input
signal and refers the output signal to the REF pin.
The equations shown in Figure 57 describe the output voltages of A1 and A2. The VBE and voltage drop across
R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
V+ V+
RG
(External)

50 kW
R1 R2
A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G V+
8 kW V- V- 8 kW
A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G 10 kW
Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V
10 kW A3 VOUT

V+
VO = G ´ (VIN+ - VIN-) + VREF V-
Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V 50 kW
REF

V-
V+ V+

-IN
Q1 Q2

VD/2 C1 C2
Overvoltage V- A1 A2 V- Overvoltage
Protection Protection

RB VB RB
VCM
VD/2
V-

+IN

Figure 57. INA827 Simplified Circuit Diagram

7.3.5 Input Protection

The INA827 inputs are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one
input and +40 V on the other input does not cause damage. However, if the input voltage exceeds [(V–) – 2 V]
and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see Figure 14. This polarity reversal can easily be avoided by adding a 10-kΩ resistance in series with
both inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 14
illustrates this input current limit behavior. The inputs are protected even if the power supplies are disconnected
or turned off.

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7.3.6 Input Bias Current Return Path

The INA827 input impedance is extremely high—approximately 20 GΩ. However, a path must be provided for
the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that
this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 58 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the INA827 common-mode range, and the input amplifiers saturate. If the differential source resistance is low,
the bias current return path can be connected to one input (as shown in the thermocouple example in Figure 58).
With higher source impedance, using two equal resistors provides a balanced input with possible advantages of
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.

Microphone,
hydrophone, TI Device
and so forth.

47 kW 47 kW

Thermocouple TI Device

10 kW

TI Device

Center tap provides

bias current return.
Copyright © 2016, Texas Instruments Incorporated

Figure 58. Providing an Input Common-Mode Current Path

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7.3.7 Reference Pin

The INA827 output voltage is developed with respect to the voltage on the reference pin. Often, in dual-supply
operation, the reference pin (pin 6) is connected to the low-impedance system ground. Offsetting the output
signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply environment) can be useful in single-
supply operation. The signal can be shifted by applying a voltage to the device REF pin, which can be useful
when driving a single-supply ADC.
For best performance, keep any source impedance to the REF pin below 5 Ω. Referring to Figure 61, the
reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ
resistor. The imbalance in resistor ratios results in degraded common-mode rejection ratio (CMRR).
Figure 59 shows two different methods of driving the reference pin with low impedance. The OPA330 is a low-
power, chopper-stabilized amplifier and therefore offers excellent stability over temperature. The OPA330 is
available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference
in a small SOT23-6 package.
+5 V

VIN-
+5 V

RG INA827 VOUT VIN-

REF
VIN+ RG INA827 VOUT
+5 V
+5 V REF
VIN+

OPA330 +2.5 V
REF3225 +5 V

a) Level shifting using the OPA330 as a low-impedance buffer b) Level shifting using the low-impedance output of the REF3225
Copyright © 2016, Texas Instruments Incorporated

Figure 59. Options for Low-Impedance Level Shifting

7.3.8 Dynamic Performance

Figure 19 illustrates that, despite having low quiescent current of only 200 µA, the INA827 achieves much wider
bandwidth than other instrumentation amplifiers (INAs) in its class. This achievement is a result of using TI’s
proprietary high-speed precision bipolar process technology. The current-feedback topology provides the INA827
with wide bandwidth even at high gains. Settling time also remains excellent at high gain because of a 1.5-V/µs
high slew rate.

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7.3.9 Operating Voltage

The INA827 operates over a power-supply range of +3 V to +36 V (±1.5 V to ±18 V). Supply voltages higher than
40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are
shown in the Typical Characteristics section.

7.3.9.1 Low-Voltage Operation

The INA827 can operate on power supplies as low as ±1.5 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of
the internal nodes limit the input common-mode range with low power-supply voltage. Figure 7 to Figure 13 and
Figure 35 to Figure 38 describe the linear operation range for various supply voltages, reference connections,
and gains.

7.3.10 Error Sources

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, these errors must be
minimized by choosing high-precision components such as the INA827 that have improved specifications in
critical areas that effect overall system precision. Figure 60 shows an example application.
+15 V
RS+ = 10 kW

VDIFF = 1 V 16 kW TI Device VOUT

REF

RS- = 9.9 kW
VCM = 10 V
Signal Bandwidth: 5 kHz -15 V
Copyright © 2016, Texas Instruments Incorporated

Figure 60. Example Application With G = 10 V/V and 1-V Differential Voltage

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Resistor-adjustable INAs such as the INA827 yield the lowest gain error at G = 5 because of the inherently well-
matched drift of the internal resistors of the differential amplifier. At gains greater than 5 (for instance, G = 10 V/V
or G = 100 V/V) gain error becomes a significant error source because of the resistor drift contribution of the
feedback resistors in conjunction with the external gain resistor. Except for very high gain applications, gain drift
is by far the largest error contributor compared to other drift errors (such as offset drift). The INA827 offers the
lowest gain error over temperature in the marketplace for both G > 5 and G = 5 (no external gain resistor).
Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 5
(no external resistor) and G = 10 (with a 16-kΩ external resistor). As shown in Table 2, although the static errors
(absolute accuracy errors) in G = 5 are almost twice as great as compared to G = 10, there is a great reduction
in drift errors because of the significantly lower gain error drift. In most applications, these static errors can
readily be removed during calibration in production. All calculations refer the error to the input for easy
comparison and system evaluation.

Table 2. Error Calculation

INA827
G = 10 ERROR G = 1 ERROR
SPECIFICATION
ERROR SOURCE ERROR CALCULATION (ppm) (ppm)
ABSOLUTE ACCURACY AT +25°C
Input offset voltage (µV) VOSI / VDIFF 150 150 150
Output offset voltage (µV) VOSO / (G × VDIFF) 2000 200 400
Input offset current (nA) IOS × maximum (RS+, RS–) / VDIFF 5 50 50
94 (G = 10),
CMRR (dB) VCM / (10CMRR / 20 × VDIFF) 200 398
88 (G = 5)
Total absolute accuracy error (ppm) 600 998
DRIFT TO +105°C
25 (G = 10),
Gain drift (ppm/°C) GTC × (TA – 25) 2000 80
1 (G = 5)
Input offset voltage drift (μV/°C) (VOSI_TC / VDIFF) × (TA – 25) 5 200 200
Output offset voltage drift (μV/°C) [VOSO_TC / ( G × VDIFF)] × (TA – 25) 30 240 240
Total drift error (ppm) 2440 760
RESOLUTION
Gain nonlinearity (ppm of FS) 5 5 5

2
eNO 6
(eNI2 + eNI = 17
Voltage noise (1 kHz) BW ´ ´ 6 6
G VDIFF eNO = 250

Total resolution error (ppm) 11 11

TOTAL ERROR
Total error Total error = sum of all error sources 3051 1769

7.4 Device Functional Modes

The INA827 has a single functional mode and is operational when the power-supply voltage is greater than 3 V
(±1.5 V). The maximum power-supply voltage for the INA827 is 36 V (±18 V).

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 61 shows the basic connections required for device operation. Good layout practice mandates that bypass
capacitors are placed as close to the device pins as possible.
The INA827 output is referred to the output reference (REF) pin, which is normally grounded. This connection
must be low-impedance to assure good common-mode rejection. Although 5 Ω or less of stray resistance can be
tolerated when maintaining specified CMRR, small stray resistances of tens of ohms in series with the REF pin
can cause noticeable degradation in CMRR.
V+

0.1 mF

8
(1)
RS
1
-IN 10 kW 50 kW
A1
VO = G ´ (VIN+ - VIN-)
2 80 kW
8 kW G=5+
RG
7
RG A3
8 kW +
3 Load VO
-
10 kW 50 kW
(1) 6
RS A2
4 REF
+IN
TI Device

5 0.1 mF

V-
Copyright © 2016, Texas Instruments Incorporated

(1) This resistor is optional if the input voltage remains above [(V–) – 2 V] or if the signal source current drive capability is limited to less than
3.5 mA. See the Input Protection section for more details.

Figure 61. Basic Connections

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8.2 Typical Application

An example programmable logic controller (PLC) input application using an INA827 is shown in Figure 62.

Figure 62. ±10-V, 4-mA to 20-mA PLC Input

8.2.1 Design Requirements

This design has these requirements:
• Supply voltage: ±15 V, 5 V
• Inputs: ±10 V, ±20 mA
• Output: 2.5 V, ±2.3 V

8.2.2 Detailed Design Procedure

There are two modes of operation for the circuit shown in Figure 62: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, the current input mode transfer function is given by Equation 2.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
• G represents the gain of the instrumentation amplifier (2)
The transfer function for the voltage input mode is shown by Equation 3.
R2
VOUT-V = VD ´ G + VREF = - VIN ´ ´ G + VREF
R 1 + R2
(3)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ
is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be extremely
small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
Equation 4 can be used to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2 R ´ VD
VD = VIN ´ ® R2 = 1 = 4.167 kW
R 1 + R2 VIN - VD (4)
The value obtained from Equation 4 is not a standard 0.1% value, so 4.12 kΩ is selected. R1 and R2 also use
0.1% tolerance resistors to minimize error.
The ideal gain of the instrumentation amplifier is calculated with Equation 5.
V - VREF 4.8 V - 2.5 V V
G = OUT = = 5.75 V
VD 400 mV (5)

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Typical Application (continued)

Using the INA827 gain equation, the gain-setting resistor value is calculated as shown by Equation 6.

(6)
107 kΩ is a standard 0.1% resistor value that can be used in this design. Finally, the output RC filter components
are selected to have a –3-dB cutoff frequency of 1 MHz.

8.2.3 Application Curves

Figure 63. PLC Output Voltage vs Input Voltage Figure 64. PLC Output Voltage vs Input Current

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9 Power Supply Recommendations

The nominal performance of the INA827 is specified with a supply voltage of ±15 V and a mid-supply reference
voltage. The device can also be operated using power supplies from ±1.5 V (3 V) to ±18 V (36 V) and non mid-
supply reference voltages with excellent performance. Parameters that can vary significantly with operating
voltage and reference voltage are illustrated in the Typical Characteristics section.

10 Layout

10.1 Layout Guidelines

Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place 0.1-μF bypass capacitors close to the supply pins. Apply these guidelines throughout the analog circuit to
improve performance and provide benefits such as reducing the electromagnetic-interference (EMI) susceptibility.

10.1.1 CMRR vs Frequency

The INA827 pinout is optimized for achieving maximum CMRR performance over a wide range of frequencies.
However, care must be taken to ensure that both input paths are well-matched for source impedance and
capacitance to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance
at the gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain
switching using switches or PhotoMOS® relays to change the value of RG, choose the component so that the
switch capacitance is as small as possible.

10.2 Layout Example

Figure 65. INA827 Example Layout

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• INA826 Precision, 200-μA Supply Current, 3-V to 36-V Supply Instrumentation Amplifier with Rail-to-Rail
Output (SBOS562)
• OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zero-Drift Series (SBOS432)
• REF32xx 4ppm/°C, 100μA, SOT23-6 Series Voltage Reference (SBVS058)
• TBD list anything else?

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated

Product Folder Links: INA827

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

INA827AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 IPSI
& no Sb/Br)
INA827AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 IPSI
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Sep-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA827AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Sep-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA827AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
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