t

1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Comparative Evaluation of Digital Control

Algorithms for DC-DC Boost Converter
Exhibiting Inverse Response

l 2 3 4 5
Vinayak Rao ; K. Tarakanath ; Sachin C. Patwardhan ; D.S. More and Vivek Agarwa1
1,4Dept. of Electrical Engg. ; W CE; Sangli; India
2,3,5Dept. of Electrical Engg. ; IIT Bombay; Mumbai; India
E-mail: Ivinayak.rao@walchandsangli. ac. in; 2tarakanath@ee. iitb. ac. in; 3sachinp@che; iitb. ac.in;
4dsm. wce@gmail. com; 5agarwal@ee. iitb. ac. in

Abstract-A dc-dc boost type converter is conventionally change in the duty ratio; causes inductor to draw large
controlled using a PID controller. However; when a control current. But; the inductor opposes this sudden change in
algorithm is realized through a digital hardware; there is no current because of its nature and thus the voItage drops
need to persist with this simplistic form. This work presents a
initially and then reverts back to follow the reference in
comparative study of servo and regulatory performances of
closed loop [6]. Due to this phenomenon the linear model
two digital control algorithms; viz. modified Dahlin's
controller (MDC) and Vogel-Edgar controller (VEC) j when
of boost type dc-dc converter exhibits RHP-zero which
employed for control of a boost type dc-dc converterj which limits the bandwidth of the closed loop operation [7].
it exhibits an inverse response. Each of this controller is To fulfil the performance objectives for the case of
equipped with a tuning parameter that has a transparent boost converter; proper control scheme is required to be
relationship with the c10sed loop servo behaviour. The developed to control the output voItage of dc-dc power
efficacy of MDC and VEC is established by carrying electronic converter. In literature; there have been various
simulation studies using Sim Power Systems Toolbox of control schemes which choose analog implementation [8;
MATLAB. The simulation exercise reveals that MDC and
9] for regulating the output voltage of the dc-dc boost
VEC can be tuned to achieve better servo and regulatory
converter. The implementation of these controllers is
performances when compared with the servo and regulatory
performances of a conventional PID controller.
either realized through operational amplifiers as given in
Keywords-DC-DC Boost Converter; Digital Control;
[10] or these continuous controllers are discretized at a
Continuous Conduction Mode (CCM); Inverse Response suitable sampling rate by using transformations like
Systems; Voltage Regulation forward Euler; backward Euler; or Tustin transformation
and are then implemented using the microprocessor chips
I. INTRODUCTION [11]. Such kind of discretization of the continuous time
W ith the increase in the use of renewable energy controllers may lead to deterioration in the performance of
sources for various applications such as in energy the closed loop system [12]. Also in [2]; we find that
harnessing and in automobiles the use of power electronic synchronization of the interleaved dc-dc converter was
dc-dc converters has increased tremendously in the last easier and efficient with the controller implementation being
decade [1-3]. From the basic preliminary topologies buck; with DSP's in digital domain. To achieve better dynamic
boost and buck-boost type dc-dc converters; the boost type response; the need of various direct digital control schemes
dc-dc converters is found to be used in many applications; arises that helps in directly developing and synthesizing the
like connecting renewable energy sources like fuel cell controller in digital domain. The digital controllers also
etc. to the dc-grid; or in case of hybrid electric vehicles; provide advantage that these could be easily synthesized;
thermo electric generators and in case of dc drives etc. accurate calculation of the controlIed input can be realized
Hence; the boost type dc-dc converter becomes the driving through digital controllers [13].
force which motivates to draw our attention to implement A PID controller was conventionally deployed for the
various control schemes. dc-dc boost type converter control. While restricting to
Also; the boost type dc-dc converter control finds PID structure simplified the implementation when the
more complexity due to the presence of RHP-zero in the controllers were realized through analog hardware; there is
control to output transfer function when operated in CCM no need to persist with this simplistic form when a control
[4; 5]. This RHP-zero has a significant effect during algorithm is realized through digital hardware. An
transient performance on the output voItage. Whenever arbitrary transfer function of any order can be easily
there is a reference change or any external disturbances realized through the digital hardware. Moreover; in the
enter the system; the duty ratio changes to drive the output digital control literature; there have been significant
voItage to desired steady state. As a consequence of this advances in the domain of model based digital control

978-1-4673-8587-9/16/$31.00 ©2016 IEEE [1]

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

algorithms [14]; that have not been looked at either in dead-time considered is equal to that of the plant's dead
simulation studies or in experimental work from the time and the steady-state gain equal to 1. This helps in
perspective of regulating the output voItage in dc-dc shaping the servo response and mitigating the severity of
power electronic converter. These digital control schemes the input moves. Let
are based on a discrete plant model and can be designed [l-a]z-(1 +N)
VMDC(Z) (1)
explicitly in the discrete domain. Thus; these don't require =
[l-az-l]
continuous to discrete conversions; which is known to where; a exp -=
( Ts);
Tcl represent the desired
'cl
deteriorate the performance of the controllers [12] and can
closed loop time constant and Ts represents the sampling
be directly implemented using either microcontroller or
interval.
FPGA.
Now; from Fig. 1; the controller which will generate a
This work aims at assessing the applicability of the
closed loop response given by (1) is obtained as folIows;
digital control algorithms described in the review paper VMDC (Z) 1
[14] for solving servo and regulatory control problems G c-DC(Z) -
-
[l-VMDC (Z)] Gp(z)
(2)
associated with a boost type dc-dc converter exhibiting However; if the plant model has zero(s) outside the
non-minimum phase behaviour. Since; sampling time unit circle; then direct inverse of the plant will make the
plays a crucial role in the implementation of digital control controller unstable. Thus; a modification in the Dahlin's
schemes; the linear perturbation model in s-domain controller has been proposed [14]; for such. Let the

K((z-Ai) ....(z-Ak)(z-A�+1 )""(z-Ari_l)Z-N)

obtained at the desired operating point is converted to z­ generalized plant Gp (z) be given as folIows;
domain using appropriate sampling time and thus obtained
discrete model is used for designing various digital Gp(z) =
(Z-Pl) ....·(Z-Pn)
(3)
controllers. The servo and regulatory performance of the where; the superscripts '-' and '+' are used here to
designed digital controllers are evaluated using simulation represent the zeros inside the unit circle and outside the

� 1-1_I,....:y�(Z�).
studies carried out using MATLAB/SIMULINK. unit circle respectively. 'N' is the delay present in plant.
This paper is organized into five sections. Design
procedure for the digital controller algorithms are briefly G,(,) 1-1---+1.1 G,,(z)
discussed in Section II. Section III presents the details of
the controller synthesis for dc-dc converter. Simulation
results are presented in Section IV and the main Fig. I: Closed Loop Digital Control Structure

conclusions reached through the simulation studies are The controller equation with the modifications in
presented in Section V. Dahlin's controller is given as follows [14]:
II. DESIGN OF DIGITAL CONTROLLERS G C_MDC(Z)
1
() [l-a]z-l
K [l-az-l]-[l-a]z-l-N
)
=

Fast settling time is the one of the desired objective ( (Z-Pl) ....·(Z-Pn)
x zm(1-At+1 )"'(1-Ari_l)(Z- Al ) ...(z-Ak)
(4)
when any control scheme is deployed with the plant. In the
Thus; it is seen that equation (4) has not used the
domain of digital control the deadbeat controllers are
direct plant inverse. It has compensated for the zeros
designed with the objective of reaching the steady state in
outside unit circle by adjusting the steady-state gains and
minimum number of sampies. However; deadbeat
by incorporating zeros at origin.
controllers are known to be aggressive in nature; i. e. they
can demand very large magnitude input moves. This may B. Vogel-Edgar Controller(VEC)
cause the plant output to have very large overshoots while
tracking any change in set-point. The modified Dahlin's Vogel Edgar controller is another type of Pole-Zero
controller and Vogel-Edgar controller are the well-known placement controller developed by Vogel and Edgar in
modifications [14] to the output deadbeat and state 1982 [14]. It also uses the direct synthesis approach;
deadbeat type of controllers; respectively; which provide which involves defining the desired closed loop transfer
explicit tuning parameter to avoid this difficulty and shape function and then arriving at the controller equation using
the servo response. The design procedure for these two simple algebra. The closed loop transfer function defined
controllers is briefly discussed in this section. for designing a Vogel-Edgar controller is as folIows:
(l-a)
(l-az-l) X
VVEC(Z)
A.
=

Modified Dahlin 's Controller (MDC)

(z-Ai) ....(z- Ak)(z-A�+1 ) ....(z-Ari_l) -N
n (5)
(l-Al ) ....(l-Ak)(l-A�+1 ) ....(l-Ari_l)Z Z

W((l-a)*(z-Pi) ...(z-Pn))
The systems under consideration are open loop stable
i. e. all poles are strictIy inside the unit circle. The design The controller transfer function is given by;
procedure for Dahlin's controller; is similar to direct
G c_VEC(Z) (6)
synthesis method of controller design. The design involves =
denVEC (Z)
specifying the closed-Ioop transfer function VMDC(Z)to be where; denVEC(z) {zn-1(l- a * Z ) -l
=

the first order with a dead-time (FODT) [14]; where the (l-AI') ... (l-AiJ *

[2]
 (1 - A t+1) ... (1 - A� l)} - {(1 - a) R(1 - D) [ R(1 - 0) + Re(1 +
t
1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

(z - A1J ... (z - Ak) - C (R + Re)s] + (R + Re)(Req + LS ) (1 + C (R + Re) s)

where; den(s)

(z - At+1) ... (z - A�_l)Z-N}

=

Here; a boost converter of power rating (P) of 2. 5

This controller also has only one tuning parameter i. e. W atts have been used; with a switching frequency of 25
Tel which is the desired c10sed loop time constant. The KHz. For the chosen input and output voltage values; the
advantage of this controller over Dahlin's controller is that voItage ripple (LlVo) is around 0. 1% of the Vo; the value of
it can be used for both minimum phase and non-minimum the capacitor is given by:
Iout(max)xD
phase systems without any modification because; it C m. (9)
m fsXLl.Vo
=

doesn't use; the inverse of plant transfer function. While

in this controller; the design procedure tries to move the where; 0 (Vo - Vin) jVo and ' out( max) P jVo
= =

zeroes which are outside unit circle to a position where it The current ripple (Llh) is chosen == 5% of the load

( )
will be inside unit circle; with the use of tuning parameter current and the inductor value can then be calculated using
Tel ' eqn (10)
V. (Vo V )
- in
L
*
m Ll.ILxfsxVo (10)
C.
=

Digital PID Controller

Using (9) and (10); the parameters of boost converter
To benchmark the performances of the digital control have been calculated as in [16] and have been Iisted in
algorithms; a conventional PID controller is designed. The Table 1.

22.0617(1.544X10-4S+1)(-7.8287X10-sS+1)
PID controller design procedure here is the loop shaping Now; using the values given in Table 1 in eqn (8);
design [15]; which has been conventionally used for Gp(s) becomes;
controlling the output voltage of the boost converter. PID G (s)
p 1.3345x10-Ss2+1.8847x10-3S+1
(11)
=

controller is designed in continuous domain and the then

discretized for a chosen sampling time (Ts); using the For the discretization of the continuous time plant
Tustin transformation. The resulting PID control transfer transfer function (11); requires appropriate choice of
sampling time. Also; the method used for discretization is
function is given by eqn. (7). Using the design procedure

the phase margin of 60°; at a crossover frequency of RHP ­

the exact discretization which assurnes the continuous
IN [15]; PID controller has been designed for obtaining
time plant along with ZOR. These have been explained as
folIows:
zero/25 and corresponding values are Kp 78.4 x =

10-3; K i 3.3; Kd=

0.245 X 10-3 andTf 0.8109 x
= =
A. Choice of Sampling Time (Ts)

( ((:h(l)(�/TsI)(�'-+l�))))
10-3 .
For any digital control implementation; Shannon
G
c_PIO
-
-
K
P
+K
1
s(Z+l)) ) + Kd
(T2(z-1 (7) sampling theorem gives the upper bound for the sampling
time based on the minimum sampling frequency needed to
1+
capture the system dynamics [17]. In [18] they have
III. DISCRETE MODEL OF BOOST CONVERTER presented a criteria's required to fulfil while implementing
digital control schemes with power electronics converter.
In this section; the design of modified Dahlin's and The lower bound arises for the sampling time from the
Vogel Edgar controllers for a power electronics boost type time required for the digital signal processor to compute
dc-dc converter using direct digital control design the controller output. In the present work; the sampling
techniques has been presented. interval is chosen to be approximately 10 times of the
Figure 2 shows the circuit diagram of dc-dc boost average computation time required. Thus; for the
converter with the resistive load. The values of different considered boost type dc-dc converter a sampling time
parameters are given in Table 1. (Ts) =12011s has been chosen; which is significantly
L D smaller when compared with the dominant system time
constant.
+ TABLE I: PARAMETERS OF DC-DC BOOST CONVERTER
R Vo Description Parameter Values
Input voltage Vin (V) 10
Output Voltage Vo (V) 15
Duty Ratio D 0.33
25

d
Switching frequency fs (KHz)
Fig. 2: Schematic Circuit Diagram of Boost Type dc-dc Converter Inductance L (mH) 3.1
Inductor ESR R Q) 0.3
90
The control to output transfer function for the boost Load resistance(nominal) R ( Q)
converter is given by; Capacitance C (/-IF) 1930
G (s) = '::,0(5) = � (1+CRcsl[R2(1-D)2_(R+Rc)(Req+LS)] (8) Capacitor ESR Rc(Q) 0.08
p des) 1-D den(s) Averaged equivalent parasitic resistance Ren(Q) 0.36

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

B. Discretization using ZOH The overall comparison of the controllers have been
divided into two parts: one is the servo performance and
For Ts=120IlS; the zero order hold (ZOR) equivalent
other is the regulatory performance of the controllers.
discrete time plant of (ll) is as follows [17].
v.,?(z) -O.019982x(z-2.947)X(z-O.3935) A. Servo Performance
Gp(z) = =
(12)
dez) z2-1.982z+0.9832
In the discrete control to output transfer fimction (12) Servo Performances have been analysed by giving a
has a zero outside the unit circle. step-up and step-down change in set-point. Tables 2 and 3
The Modified Dahlin's controller for considered boost shows the comparisons of performance indices for various
converter; with Tcl as tuning parameter is having the form tuning parameters. The tuning parameter (Tcl) for servo
as given below; performance were chosen based on the open loop time
GC_MDC (Z) =
( 1 )[1-a]z-1 constant of the plant; which was found to be approximately
-0.019982 [1-az-1]-[1-a]z-1)
X
( z2-1.982z+0.9832 ) (13)
equal to 20ms from the open loop step response of the plant
model. So the Tcl of about 12 ms; 15ms and 18 ms were
z(1-2.947)(z-0.3935) chosen for shaping the servo response.
The Vogel-Edgar controller synthesized is having the Tables 2 and 3 compare performances of MDC and
form as folIows; VE controllers for a positive and a negative step change in
1 ((l-a)x(z2-1.982Z+0.9832)) the set-point. It was found that Tcl=15ms generates good
GC_VE(z) =
(14)
<-0.01998) denVE(z) compromise between faster settling timelrise time and %
where; denVE(z) {Z2 (1 - a * Z-1)
=
overshoot. When compared with the PID controller
(1 - 2.497)(1 - O.393S)} performance it was found that both the controllers with the
- {(1 - a)(z - 2.947)(z - O.393S)Z-N} choice Tcl=15ms result in quick rise to the fmal set-point
and significantly less settling time. Also when different
IV. SIMULATION RESULTS
tuning parameters were compared for step-down set-point
The performances of all the designed digital change; it was found that 15ms was performing better in
controllers have been evaluated for various servo and terms of the chosen performance indices. Figs. 3 and 4
regulatory control scenarios. The simulation experiments show the servo responses; simulated for step change in the
are carried out using a nonlinear model developed from set-point from 15V-19V (step up change in set-point) and
Sim Power Systems Toolbox of MATLAB/SIMULINK 15V-13V (step-down change in set-point) respectively.
using parameters listed in Table l. The non-linear model TABLE 2: COMPARISON OF PERFORMANCE INDICES FOR STEP-UP
CHANGE IN SET-POINT
uses a power MOSFET switch; inductor; output capacitor;
'[cl (ms) Controller %Mp tr (ms) ts (ms) IAE
diode and resistance blocks which are connected to form a 12 MDC 10.268 13.64 63.65 0.083
boost converter along with a dc voItage source. This VE 12.583 11.95 65.49 0.087
15 MDC 4.832 17.55 76.93 0.094
Toolbox gives us the ability to simulate the boost
VE 6.34 14.5 80.6 0.097
converter using the components from the toolbox; which 18 MDC 1.938 21.23 91.09 0.108
acts analogues to the physical hardware. Thus the non­ VE 1.767 19.08 91.86 0.107
PID 0.1185 46.87 140.7 0.126
linear model was developed and simulation was performed
along with the above designed digital controllers in the TABLE 3: COMPARISON OF PERFORMANCE INDICES FOR STEP-DOWN
CHANGE IN SET-POINT
%Mp
closed loop form as shown in Fig l. The Gp (z) in the Fig. (ms) Controller tr(ms) ts (ms) IAE
'[cl
1 was replaced with the non-linear model developed; to 12 MDC 13.449 20.88 98.41 0.0567
which the controllable input is the duty ratio from the VE 13.39 20.95 88.06 0.0569
15 MDC 11.211 21.27 60.73 0.5133
controller. VE 11.117 21.32 60.08 0.0515
For; the plant transfer fimction given by eqn (12); 18 MDC 9.97 23.44 76.57 0.0587
MDC and VE controllers have been designed and VE 10.750 23.68 75.73 0.0588
PID 1.301 22.81 58.22 0.0563
comparative analysis have been done w. r. t. PID controller;
for different tuning parameters; based on basic B. Regulatory Performance
performance indices such as %overshoot/undershoot
The regulatory performance demands that the
(%Mp); settIing time (ts); rise time (tr); Integral of
controller should regulate the output voItage at a desired
Absolute Error (IAE) and controller variation (Iu). set-point as fast as possible. But faster regulatory response
IAE =
Lf;!11 r(i) -y(i)1 (15) leads to aggressive control efforts which might not be
Iu=
Lf;!1Iu(i) -u(i -1)1 (16) permissible for some systems. In the system of our
where; M = settling time(ts)/sampling time (Ts) consideration i. e. dc-dc boost type converter; the
u(i) = controller output at any instant 'i'. aggressive control effort would lead to rapid change in the
y(i) = plant output at any instant 'i'. inductor current which may cause dip in voltage as
r(i) = reference signal at any instant 'i'. inductor opposes any rapid change in current through it.

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

It is thus necessary to have a tuning Tel of MDC and increase in the Iu. The choice of Tel = 3ms gives a
VE such that the control effort doesn't become aggressive satisfactory regulatory behaviour for both MDC and VE
as well as the regulatory behaviour is satisfactorily controller when compared to PID controller. The
fulfilied. The regulatory behaviour; have been simulated corresponding regulatory responses are shown in Figs. 6
by inducing an input voltage change i. e. (1OV-7V: Step and 7 respectively.
down change in input voltage) and (10V-13V: step up Examination of Figs. 3 and 4 reveals that the Vogel
change in input voItage). Tables 4 and 5 presents the Edgar and modified Dahlin's controller with Tel = 15ms
comparison of various tuning parameters for which better are able to manage quick transition to the desired set-point
regulatory behaviour for step-up and step-down change in without requiring Iarge input changes and without
input voltage disturbances. violation of input constraints. Modified Dahlin's
It is thus necessary to have a tuning Tel of MDC and Controller has slightly smaller overshoot than Vogel­
VE such that the control effort doesn't become aggressive Edgar Controller even though both have approxirnately
as weil as the regulatory behaviour is satisfactorily same settling time. Their performance is significantly
fulfilled. The regulatory behaviour; have been simulated better than the PID controller for step up change.
by inducing an input voltage change i. e. (lOV-7V: step

i: I
down change in input voltage) and (10V-13V: step up
change in input voItage). Tables 4 and 5 presents the
comparison of various tuning parameters for which better
regulatory behaviour for step-up and step-down change in 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15
Time (s)
input voltage disturbances. Here in the table we have (a)

fl��•• :,=": •••••• ••••••1

included one extra performance index 'lu' which shows
the variation of the control effort at any instant compared
to the previous instant.
TABLE 4: COMPARISON OF PERFORMANCE INDICES FOR STEP-DOWN "

CHANGE IN INPUT VOLTAGE 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15

%Mp
Time (s)

"[cl (ms) Controller ts(ms) IAE IU (b)

(*10-4) Fig. 3: Step up Change in Set-point: (a) Output Voltage;
15 MDC 16.43 143.3 0.1345 0.6405 (b) Controller Output
VE 16.32 115.78 0.131 1.016
12 MDC 15.15 146.41 0.1262 0.7902 � 15

VE 15.13 147.25 0.1245 1.2894 :5b14.5

9 MDC 13.61 147.22 0.1107 1.00 I8 �

;>
14

VE 13.59 159.29 0.1095 1.68 I9 -= 13.5

6 MDC 11.57 297.6 0.103 I 1.4771 8' �

13 ·· R(+... _ ·-:··_··_·
.
l\.1DC(15ms
_:<·�V�------I
VE 11.54 299.57 0.0956 2.5210 0.01 0.2 0.03 0.04 0.05 0.06 0.07 0.08

3 MDC 8.53 160 0.0341 2.5773 Time(s)

f:�FEJID . • ••• . J
VE 8.52 150 0.0209 4.4549 (a)
PID 10.00 299.98 0.1099 0.8905

mm m m
TABLE 5: COMPARISON OF PERFORMANCE INDICES FOR STEP-UP CHANGE
IN INPUT VOLTAGE
"[cl (ms) Controller %Mp ts(ms) IAE IU
(*10-4) 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
15 MDC 28.07 162.27 0.2426 0.7891 Time(s)
VE 27.26 158.52 0.2299 1.0703 (b)
12 MDC 25.66 142.40 0.2124 0.8878 Fig. 4: Step-down Change in Set-point: (a) Output Voltage;
VE 25.23 139.16 0.2065 1.2545 (b) Controller Output
9 MDC 23.26 132.53 0.1819 1.0202
VE 22.54 131.45 0.1730 1.5626
6 MDC 19.15 98.36 0.1341 1.3358
VE 18.80 97.08 0.1291 2.0899
3 MDC 12.57 90.01 0.0438 2.3953
VE 12.18 94.49 0.0362 4.030
PID 9.23 123.68 0.0945 1.29 I9 0.01 0.03 0.05 0.07
Time
0.09
(s)
0.11 0.13 0.15

(a)
From Tables 4 and 5 it is seen that for Tel = 15ms;
which had been chosen appropriate for servo performance;
here it shows a poor regulatory performance i. e. it has
higher percent overshoot/undershoot. Thus; for faster
regulatory response with a smaller overshoot/undershoot;
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15
lower values of Tel have been used and the performance Time (s)
parameters have been compared. (b)
It is seen from Tables 4 and 5 that as Tel is decreased Fig. 5: Step-down Change in Input Voltage:
(a) Output Voltage (b) Controller Output
the percent overshoot/undershoot decreases but there is an

[5]
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1s IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES-2016)

From Figs. 5 and 6 it can be seen that tuning of MDC need can facilitate improved servo and regulatory
and VE Tel = 3ms have brought the disturbance rejection behaviour simuItaneously. Currently the work is in
performance in comparable to that of PID; without making progress on implementing MDC and VEC using FPGA
any compromises in the control effort. From Table 4 and 5 based hardware.
it can be seen that with decrease in tuning parameters of
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