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Lesson Plan

This document provides a lesson plan for the course ECE2003 - Digital Logic Design for the Fall 2019-20 semester. It lists 30 lectures over the course of the semester, along with their corresponding dates and topics. The lectures cover fundamental topics in digital logic design, including number systems, logic gates, Boolean algebra, K-maps, adders/multipliers, sequential circuits, finite state machines, and modeling digital circuits using Verilog HDL. There are two midterm exams scheduled, one on August 13th and another on October 22nd.

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51 views1 page

Lesson Plan

This document provides a lesson plan for the course ECE2003 - Digital Logic Design for the Fall 2019-20 semester. It lists 30 lectures over the course of the semester, along with their corresponding dates and topics. The lectures cover fundamental topics in digital logic design, including number systems, logic gates, Boolean algebra, K-maps, adders/multipliers, sequential circuits, finite state machines, and modeling digital circuits using Verilog HDL. There are two midterm exams scheduled, one on August 13th and another on October 22nd.

Uploaded by

gokul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE2003 – DIGITAL LOGIC DESIGN

FALL 2019-20
Lesson Plan
S. No. Lecture Date Lecture Topic
1 11/07/2019 Brief review of Number Systems
2 16/07/2019 Digital Logic Gates and its electrical characteristics
3 18/07/2019 Review of RTL, DTL, TTL, ECL
4 23/07/2019 CMOS families
5 25/07/2019 Basic Definitions, Axiomatic Definition of Boolean Algebra
6 27/07/2019 Basic Theorems and Properties of Boolean Algebra
7 30/07/2019 Boolean Functions, Canonical and Standard Forms
8 01/08/2019 The Map Method - K-map
9 06/08/2019 Product of Sums simplifications
10 08/08/2019 Sum of Products Simplification
11 13/08/2019 NAND and NOR Implementation
CAT-1
12 27/08/2019 Design Procedure, Binary Adder-Subtractor
13 29/08/2019 Parallel Adder, Binary Multiplier
14 3/09/2019 MagnitudeComparator-4 bit, Parity generator and checker.
15 10/09/2019 Decoders, Encoders, Multiplexers, De-multiplexer,
16 12/09/2019 Application of Mux and Demux
17 17/09/2019 Lexical Conventions, Ports and Modules, Operators
18 19/09/2019 Gate Level Modeling & Data Flow Modeling
19 24/09/2019 Behavioral level Modeling, Testbench
20 26/09/2019 Latches, Flip-Flops-SR, D, JK & T
CAT-2
21 8/10/2019 Shift Registers-SISO, SIPO, PISO,PIPO
22 10/10/2019 Design of synchronous sequential circuits- State table and state
diagrams
23 15/10/2019 Design of counters-Modulo-n
24 17/10/2019 Johnson, Ring, Up/Down
25 22/10/2019 Design of Mealy and Moore FSM
26 24/10/2019 Sequence detection
27 29/10/2019 Modeling of Combinational Circuits using Verilog HDL
28 31/10/2019 Modeling of Combinational Circuits using Verilog HDL
29 5/11/2019 Modeling of Sequential Logic Circuits using Verilog HDL
30 7/11/2019 Modeling of Sequential Logic Circuits using Verilog HDL

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