DELAY ESTIMATION IN STATIC DESIGN By Prasad Pande
FAST COMPLEX GATES: DESIGN TECHNIQUE 1
• Transistor Sizing –
propagation delay issue exists for larger device sizes
• Progressive Sizing -
FAST COMPLEX GATES: DESIGN TECHNIQUE 2
• Transistor Ordering
FAST COMPLEX GATES: DESIGN TECHNIQUE 3
• Isolating fan-in from fan-out using buffer insertion – chain of inverters
FAST COMPLEX GATES: DESIGN TECHNIQUE 4
• Reducing the voltage swing causes
tpHL = 0.52 (CL VDD/ IDSATn )
= 0.52 (CL Vswing)/ IDSATn )
- linear reduction in delay
- also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on the receiving end to restore the signal level
(memory design)
FAST COMPLEX GATES: DESIGN TECHNIQUE 5
• Alternative Logical Structures – e.g. Y = ABCDEFGH
How designer should opt?
LOGICAL EFFORT
• Definition –
The ratio of the input capacitance of the gate to the input capacitance of
an reference inverter that can deliver the same output current.
• Logical effort indicates how much worse a gate is at producing output
current as compared to an inverter, given that each input of the gate
may only present as much input capacitance as the inverter.
• Logical effort is represented by g.
REFERENCE INVERTER INPUT CAPACITANCE
Assumption for analysis purpose : single unit/valued of capacitance C for gate as well as diffusion
For Reference inverter (2:1) –
input capacitance of single inverter is
equal to 3C
LOGICAL EFFORT
• Basic Gates - Logical effort g
LOGICAL EFFORT
• Basic Gates with more inputs - Logical effort g
LOGICAL EFFORT
• Basic Gates with more inputs - Summary
ELECTRICAL EFFORT
GATE DELAY MODEL (LINEAR)
• Normalized gate delay can be expressed as
d=f +p
where, f is the effort delay or stage effort that related to gate’s load
f =g.h
and p is the parasitic delay inherent to the gate when no load is attached
(depends in gate structure)
Hence, the gate delay can be calculated as
d=g.h +p
PARASITIC DELAY
• Parasitic delay is delay of gate driving no load and is set by internal parasitic capacitance
• The reference inverter has three units of diffusion capacitance on the output, so the parasitic delay is
3RC = τ = Pinv
• τ is the ratio of diffusion capacitance to gate capacitance in a particular process. It is usually close
to 1 and will be considered to be 1. Hence The normalized parasitic delay is 1 for inverter.
• Crude method of calculations is to count only diffusion capacitance on the output node.
• Sizes of the transistors in gates does not affect p
• Example - The 3-input NAND and NOR each have 9 units of diffusion capacitance on the output, so
the parasitic delay is three times as great (3 τ, or simply 3).
PARASITIC DELAY
NORMALIZED DELAY VS. FAN-OUT
DELAY IN MULTISTAGE LOGIC NETWORKS
DELAY IN MULTISTAGE LOGIC NETWORKS
• The path effort F is the product of the stage efforts f of each stage
F = Π fi = Π gi hi
DELAY IN MULTISTAGE LOGIC NETWORKS
• What if Branch appears in network?
DELAY IN MULTISTAGE LOGIC NETWORKS
• Branching Effort b
• It is ratio of the total capacitance seen by a stage to the capacitance on the path
• The path branching effort B is the product of the branching efforts between stages
B = Π bi
• Path Effort F by taking branching effort into account can be defined as the product
of the logical, electrical, and branching efforts of the path
F = GBH
DELAY IN MULTISTAGE LOGIC NETWORKS
• Delay is smallest when each stage bears same effort
• If a path has N stages and each bears the same effort, that effort must be
• Thus, the minimum possible delay of an N-stage path with path effort F and path parasitic
delay P is
• It shows that the minimum delay of the path can be estimated knowing only the number of
stages, path effort, and parasitic delays without the need to assign transistor sizes.
DELAY IN MULTISTAGE LOGIC NETWORKS
• Now, the path delay in multistage network D can be calculated by calculating path effort
delay DF and path parasitic delay P
SUMMARY
PROBLEM 1: OPTIMIZE PATH(MINIMUM DELAY)
PROBLEM 2: MINIMUM DELAY ALONG PATH
Estimate the minimum delay of the path from A to B in figure given and choose transistor sizes
to achieve this delay. The initial NAND2 gate may present a load of 8 of transistor width on
the input and the output load is equivalent to 45 of transistor width.
PROBLEM 2: MINIMUM DELAY ALONG PATH
Estimate the minimum delay of the path from A to B in figure given and choose transistor sizes
to achieve this delay. The initial NAND2 gate may present a load of 8 of transistor width on
the input and the output load is equivalent to 45 of transistor width.
PROBLEM 2: TRANSISTOR SIZING
f ˆ = gi . hi
y = 45 × (5/3)/5 = 15
x = (15 + 15) × (5/3)/5 = 10
verify that the initial 2-input NAND gate has the
specified size of (10 + 10 + 10) × (4/3)/5 = 8
PROBLEM 3: NUMBER OF STAGES
A control unit generates a signal from a unit-sized inverter. The signal must
drive unit-sized loads in each bit-slice of a 64-bit data-path. what is the
best number of inverters to add and what delay can be achieved?
PROBLEM 4: SELECTION OF LOGICAL PATH
PROBLEM 4: SELECTION OF LOGICAL PATH
PROBLEM 5: DESIGNING W. R. TO ELECTRICAL
EFFORT
PROBLEM 5:
Prasad Pande
