©footage firm, inc.

by Syed Huzaif Ali, Xiong Li,

Anant S. Kamath, and Bilal Akin

A Simple Plug-In Circuit

for IGBT Gate Drivers
to Monitor Device Aging
Toward smart gate drivers

I
n this article, a simple, cost-effective circuit is pro- porated in conventional gate driver (GD) circuits is pro-
posed for in situ monitoring of aging and degrada- posed. As one of its key advantages, a Vce, on monitoring
tion in discrete IGBT devices through the measure- circuit does not require complex compensation and reca-
ment of on-state collector-emitter voltage drop libration like some of the earlier methods. The proposed
(Vce,on) and gate-threshold voltage (Vth) . For this circuit can measure Vce,on and Vth in microseconds dur-
purpose, comprehensive device degradation tests are ing system start/stop diagnostic test routine. The mea-
conducted through cyclic thermal stress applications. surement results of the proposed circuit are also com-
Based on the test results, Vce,on and Vth are found to be pared with those from the high-precision curve tracer
reliable precursors for a practical device health assess- (Keysight B1506A), which validates its utility as well.
ment, and a monitoring circuit, that can be easily incor-
Aging Detection Methods for IGBT
Digital Object Identifier 10.1109/MPEL.2018.2849653
Today, most modern power converters deploy IGBTs, there-
Date of publication: 10 September 2018 fore their lifetimes are dependent upon the condition of

2329-9207/18©2018IEEE September 2018 z IEEE Power Electronics Magazine 45

 System
ACD
8%
12%

ACD Others
Inverter 9%
21% 37%
System
Inverter
6%
59%
Data
Data
Acquisition
Acquisition
System
Others System
7%
27% 14%

(a) (b)

FIG 1 The failures in PV systems over five years: (a) unscheduled maintenance events and (b) maintenance cost breakdowns due to
failures. PV: photovoltaic; ACD: ac disconnects.

IGBTs [1]. According to one comprehensive survey con-

ducted on a solar farm, most of the system failures occur in
power converters (inverters). Among these, power devices
Humidity occupy a major portion of repair/maintenance costs, as
19% shown in Figure 1(a) and (b) [2]. These failures and corre-
Dirt sponding downtimes can cause a significant amount of
6% Temperature
Steady-State operation loss. There are several factors that affect device
and/or Cyclical degradation and aging; thermal stress has been identified as
Vibration/
Shock 55% the major cause of device aging and package-related fail-
20% ures, as shown in Figure 2 [3], and may cause bond wire lift-
off, delamination, solder joint, and gate-oxide issues as
depicted in Figure 3 [4].
One frequently discussed method is measuring the
IGBT’s junction temperature, T j, which refers to the semi-
FIG 2 The major stressors that act on IGBTs and cause aging. conductor die temperature, and using that measured T j in
the classical Coffin-Mason or other modified stress model
for estimating the IGBT’s lifetime [1]. Measuring T j is not an
Bond Wire easy task because the die is generally encapsulated in thick
Bond Pad
Si Die plastic-molded packages that restrict noninvasive T j mea-
Solder surements. Therefore, different electrical parameters have
Cu Base Plate Thermal been investigated for estimating T j without modifying the
Paste die or encapsulating package [5]. Nevertheless, estimating
Heat Sink T j requires recalibration and/or complex thermal modeling
(a) to compensate for the aging effects.
Another approach is based on using the device’s param-
Bond
Wire Crack Is Initiated eter information to estimate its lifetime. In [6], an easy-
to-implement remaining useful lifetime (RUL) estimation
model for power field-effect transistors has been proposed
based on the variations in on-state resistance (R ds,on). This
Silicon
model directly uses an R ds,on variation because of aging, in
Die
15.0 kV × 100 300 µm contrast to other models that first calculate T j based on
(b) (c) electrical parameters [5]; it then estimates a switch’s life-
time using stress models based on the calculated T j [1].
FIG 3 The IGBT structure and its failure analysis: (a) a discrete-
package IGBT structure, (b) the red spots in an acoustic analysis Several electrical parameters and their measurement
snapshot reveals significant delamination, and (c) a cross-sec- circuits have been reported in the literature as useful
tioned image showing a crack initiation. Si: silicon; Cu: copper. failure precursors for IGBT as well. Among these failure

46 IEEE Power Electronics Magazine z September 2018

precursors, Vce,on measurement meth- which analyzes only the effects of
ods have been studied extensively [7]. aging under thermal stress.
Besides, a comprehensive discussion is
During these tests, all Furthermore, devices’ conditions
presented in [8] about noninvasive con- of the conditions are have been verified at regular inter-
dition-monitoring topologies and the vals during aging tests for the pos-
maintained exactly
corresponding issues in their imple- sible decrease in the resistance bet­­
mentation. Nevertheless, one of the the same, with the ween collector-emitter terminals (i.e.,
major issues is the integration of aging exception of the loss-of-breakdown voltage, BVces
monitoring circuit(s) into the existing capability) using the handheld ohm-
design of converters, particularly the maximum junction meter. To measure failure precursors
GD circuit. temperature (Tj,max ), at regular intervals, a Keysight curve
In [9], the authors have shown the tracer B1506 has been used as part of
utility of Vce,on results for degradation which analyzes only the test setup, of which the measure-
detection, but used pseudo Vth mea- the effects of aging ment and test details as well as fur-
surements for estimating T j . They ther results have been discussed in
have used T j information for Vce,on cor-
under thermal stress. [13] and [14]. More importantly, ther-
rection, however, Vth was affected by mal cycle duration has been corrected
aging and a pseudo Vth measurement after every few hundred cycles to com-
requires a Kelvin emitter connection, which is uncommon pensate the aging effects for estimating T j, as described in
in discrete-package IGBTs. In [10] and [11], circuit details [4]. End-of-life behavior for different samples has been sum-
are given for capturing a variety of failure precursors with marized in Tables 1 and 2 for above- and below-SOA test
pseudo real-time capability but require too many additional cases, respectively [14].
components and may not fit easily in a compact GD. In Figure 6(a) and (c), the Vce,on results for a few samples
The main goal of this article is to demonstrate a smart tested above and below SOA or manufacturer-specified
GD circuit, which can monitor aging related parameters. T j,max limits are shown. Generally, the contacts crack under
With this connection, this article proposes a start/stop thermomechanical stress and fatigue leads to increased
diagnostic test routine to detect aging in IGBTs by monitor- electrical contact resistance; this causes a rise in Vce,on
ing Vth and Vce,on sequentially with a cost-effective circuit. curves, but Vce,on curves at a nominal collector current (I ce)
The circuit is specifically designed to be easily embedded of 5 A follow the “dip-before-rise” behavior, as shown in Fig-
in conventional GDs. The smart GD circuit integrated with ure 6(a) for above-SOA tests. Once the minimum value has
Vth and Vce,on monitoring capability has not been reported been reached, the slope changes to positive and continues
in literature. to increase until complete device failure occurs.
It is speculated that the degradation in both electrical
Identified Failure Precursors and thermal impedances compete with each other to dic-
Previously, gate-threshold voltage (Vth) has been used to tate the overall Vce,on profile. Aging in die attach causes
detect gate oxide-related failures [12]. Similarly, Vce,on has degradation in both thermal and electrical impedances.
also been identified as a useful failure precursor for detect- The degraded thermal impedance increases T j and intrin-
ing package related failures [8]. To understand the effects of sic carrier concentration, which subsequently lowers Vce,on .
thermal stress and confirm the utility of failure precursors After reaching that minimum value, the increased electri-
and their aging profile, a custom accelerated aging test bed cal resistance starts to dominate and dictates the Vce,on
has been used. The schematic design is shown in Figure 4, profile. It is important to note that both increased minority
and the actual snapshot of setup is shown in Figure 5. carrier lifetime and/or reduced gate-threshold voltage due
A set of tests is performed on different IGBT samples to the increased junction temperature can cause Vce,on to
under various thermal stress scenarios. Two cycling schemes decrease. Contrarily, a rising temperature can decrease
are implemented depending on whether the device is operat- the carrier mobility, thereby increasing Vce,on . Thus, at any
ing within safe operating area (SOA) limits. For the previously time throughout aging, a number of physical phenomena
mentioned SOA test, one thermal cycle lasts for more than are competing with one another and determine the overall
2 min, i.e., the Ton /Toff = 45 s/130 s, whereas for the below- Vce,on variation under thermomechanical stresses. These
SOA test, one thermal cycle has a Ton /Toff = 38 s/80 s. The competing mechanisms are illustrated in Figure 7 and more
T j,max is calculated using a thermal model from the manufac- details are given in the previous article [14].
turer datasheet values and the measured case temperature Contrarily, an always-increasing trend in the Vce,on
(Tc) of the individual IGBT. In fact, the thermal cycle dura- variations can be seen for the below-SOA case in Fig-
tion depends on the time required to reach the desired Tc or ure 6(c). This shift lies in agreement with the expected out-
T j,max based on the thermal time constant. During these tests, come of such tests [15]. Furthermore, this always-increasing
all of the conditions are maintained exactly the same, with trend validates the hypothesis that the accelerated temper-
the exception of the maximum junction temperature (T j,max), ature cycling below the maximum temperature of 200 °C

September 2018 z IEEE Power Electronics Magazine 47

48
DUT Cooling Fan

dc Power Supply

IEEE Power Electronics Magazine

Auxiliary Board Main Board
Id,1

Transistor Package
Transistor Heat Sink
Auxiliary Circuit 1 Circuit 1

G1auxiliary DUT, 1 No Heat Sink

NI-USB 6255

z September 2018
Auxiliary G1

VCtrl_FAN
Gate Gate Tc,1 Data Acquisition
Swt.1 Driver Driver
System
Vds,1 Id,1Vds,1

Data Storage
Trigger Signal Computer
Tc,1
Auxiliary Circuit 7 Circuit 7
Auxiliary ∗T
c,1,high TI C2000
Gate
DUT, 7 ∗T
c,1,low
DSP
G7auxiliary Signals
Auxiliary Gate G7 Gate
Swt.7 Driver Driver
DUT
Tc,7 ∗∆T ...∗∆T
Gate c,1 c,7
Signals ∗T
c,7,high
∗T
dc Bus c,7,low

FIG 4 The schematic of a test bench. DUT: device under test; TI: Texas Instruments; IR: infrared; DSP: digital signal processor; NI: national instrument; USB: universal serial bus; Swt.:
switch.
 To NI DAQ
Voltage Gate Drivers DSP Controller
Sensing Board
Circuit JTAG to USB

Cooling DUT Temperature Sensor

Fan

FIG 5 A custom-designed aging test setup with a Keysight B1506 curve tracer.

restricts the solder degradation to a lower level. As a result,

Table 1. The IGBT thermal aging
only the positive components of Vce,on dominate the overall results at approximately 200 °C [14].
Vce,on variations under the given conditions. These results
also show good agreement with the results presented in ΔT Cycle Number Switch Condition
Name Range of Cycles at Failure
[16], where similar trends in Vce,on evolution are observed.
Aside from the package-related failures, gate-oxide IGBT-1A (40–220 °C) 1,600 Always off; low resistance
between the G-E terminals
degradation is another important failure mechanism. IGBT-2A 1,400
and high resistance be-
Gate-oxide degradation in microelectronic components is tween the C-E terminals
IGBT-3A (40–200 °C) 2,594
a well-studied phenomenon. Although the gate-oxide layer
thickness in an IGBT is typically above 150 nm, the gate- IGBT-5A 2,674
oxide follows a similar degradation mechanism. When the IGBT-6A (30–200 °C) 2,159
device’s operating temperature exceeds 100 °C, the traps IGBT-7A 2,191
start to accumulate in the gate oxide [17]. Such traps fur-
ther build up a leakage path causing a decreased oxide IGBT-9A (60–200 °C) 3,331
area and ultimately decreased gate capacitance. Mean- IGBT-10A 3,291
while, this leakage path within the gate oxide increases the IGBT-12A (30–205 °C) 2,308
gate-leakage current. As shown in Figure 6(b) and (d), the
IGBT-13A 2,411
decrease in parasitic capacitances eventually leads to an
increase in Vth during the course of an IGBT’s lifetime [4]. IGBT-4A (40–200 °C) 2,059 Loss of gate control, no
Consequently, a variation in Vth during the device’s lifetime G-E or C-E resistance
IGBT-8A (30–200 °C) 2,440
can be used to determine gate-oxide aging issues.
IGBT-11A (30–205 °C) 2,250
As a summary of previously published results, Vth is
highly useful as aging precursors when T j,max exceeds the
SOA [4]. However, below 100 °C its variation reduces dras-
tically because the gate-oxide failure mechanisms remain Table 2. The IGBT thermal aging
relatively inactive. On the other hand, the Vce,on shifts are results at low thermal swing [14].
highly dependent on the applied thermal stress and can only ΔT Cycle Number Switch Condition
provide a consistent increase for aging tests below thermal Name Range of Cycles at Failure
SOA [14]. Single-failure precursors may give incomplete IGBT-14A (30–180 °C) 3,592 Always off; low resistance
information. Therefore, to accurately detect and monitor between the G-E terminals
IGBT-15A (30–170 °C) 4,212
the state of health of IGBTs, a measurement circuit for both and very high resistance
Vth and Vce,on is proposed to determine the degradation of IGBT-16A (30–150 °C) 8,450 between the C-E terminals
IGBTs in start/stop system checkups. IGBT-17A 7,435
IGBT-18A (40–140 °C) 12,955
Issues in Measurements of Vth and Vce,on IGBT-19A 13,095
By definition, Vth is the gate-emitter voltage at which the
IGBT-20A (28–100 °C) >32,000 No failure observed
channel inversion occurs and current starts to flow from

September 2018 z IEEE Power Electronics Magazine 49

 4.5 6.2

Gate Threshold Voltage (Vth) (V)

At Tamb = 28 °C
Collector-to-Emitter Voltage

Ice = 5 A
ΔTj = 160 °C Vge>12 V
4 6
Drop (Vce,on) (V)

Tj,max = 200 °C

3.5 IGBT-3A 5.8 Compliance: Ice = 0.25 mA

IGBT-4A
IGBT-5A
IGBT-3A
3 5.6
IGBT-4A
IGBT-5A
2.5 5.4
0 500 1,000 1,500 2,000 2,500 0 500 1,000 1,500 2,000 2,500 3,000
Number of Cycles Number of Cycles
(a) (b)

3.6 5.5

Gate Threshold Voltage (Vth) (V)

Collector-to-Emitter Voltage

At Tamb = 30 °C Ice = 5 A
3.5 ΔTj = 120 °C Vge>12 V 5.4
Drop (Vce,on) (V)

Tj,max = 150 °C
5.3
3.4
5.2
3.3 Compliance: Ice = 0.25 mA
5.1
IGBT-16A IGBT-17A IGBT-16A IGBT-17A
3.2
5
0 2,000 4,000 6,000 8,000 10,000 0 2,000 4,000 6,000 8,000 10,000
Number of Cycles Number of Cycles
(c) (d)

FIG 6 The aging test results for induced thermoelectric stress, above and below the thermal SOA limit: (a) and (c) variations in
Vce,on drop at I ce = 5A and (b) and (d) variations in Vth drop, respectively.

Increase in Increase in the

Die Attach Equivalent
the Thermal
Degradation Contact Resistance
Resistance

Temperature Temperature
Increase at the Increase in the
PN Junction Drift Region

Gate Increase in the Minority

Threshold Intrinsic Carrier
Voltage Carrier Lifetime Voltage
Reduction Concentration Reduction Drop
Increases
Carrier Across the
Mobility Contacts
Voltage Drop Decreases
at the PN Junction

Vce,on Decrease Vce,on Increase

FIG 7 A simplified approach to explain the underlying physical phenomena responsible for the Vce,on variation in IGBTs under ther-
mally induced aging [14].

50 IEEE Power Electronics Magazine z September 2018

collector to emitter terminals. For in For the below-SOA case summa-
situ Vth measurements, a small cur- rized in Figure 8(b), the Vce,on curves
rent source (CS) is required to charge
The proposed circuit is at I ce = 10 mA show small dips com-
the gate-emitter capacitance until a intended to be used pared to the result at I ce = 5 A, as
small I ce starts to flow [18]. For the shown in Figure 6(c). In fact, in Fig-
for start-up diagnostic
Vth results shown in Figure 6, the mea- ure 6(c), Vce,on curves show a near-
surement has already been carried out tests in power convert- continuously increasing trend. It is
in a few microseconds at the same test ers before the actual evident that at a higher current with
current (I ce = 0.25 mA) and corre- minimal solder degradation, the con-
spondingly same T j; therefore, the switching operation is tact-resistance voltage drop is the
measurements are considered free activated and/or after dominant component of overall Vce,on
from the effects of variations in I c as but the same contact voltage drop
well as T j . it is halted. becomes negligible at a low- current
On the other hand, Vce,on is a function level. Thus, for a lower current with
of I c as well as T j . As discussed previ- minimal solder degradation, the cor-
ously, a complex load-current compensation is required for responding physical phenomena referred to in the “Identi-
trustworthy Vce,on measurements [6]. Measuring Vce,on at a fied Failure Precursors” section become dominant, which
fixed-test current level can avoid this compensation prob- cause dips in Vce,on curves.
lem at the cost of losing real-time measurement capability.
Since, a Vth measurement requires a fixed-test current through Proposed Circuit Description
device under test (DUT) and isolation of DUT from the main Based on the aging test results, an in situ Vth and Vce,on mea-
currents during measurement, observing Vce,on at lower cur- surement circuit is proposed to monitor IGBT aging. The pro-
rents alongside Vth is feasible. posed circuit is intended to be used for start-up diagnostic
Before utilizing this low-current Vce,on measurement, tests in power converters before the actual switching opera-
aging trends at a lower current must be verified. In this tion is activated and/or after it is halted. The schematic of the
connection, Figure 8(a) and (b) shows the Vce,on results proposed circuit is shown in Figure 9(a). Apart from the GD
at I ce = 10 mA for the same set of tested samples whose components, the circuit features a CS to provide a small test
results at I ce = 5 A have been shown in Figure 6(a) and current; two diodes are included to protect the GD circuit
(c), respectively. For the above-SOA results shown in from the applied high voltage between the C-E terminals dur-
Figure 8(a), significantly less voltage dips are seen as ing off-state and to provide isolation between the CS and GD.
compared to the Vce,on measurements at high current The diagnostic routine involves routing of current from
(5A) shown in Figure 6(a). The device’s self-heating at the CS through different paths to accurately measure Vth
I ce = 5 A causes increased intrinsic carrier concentra- and Vce,on . To achieve this, a set of control signals are gen-
tion, increased carrier lifetime, and decreased gate- erated through the digital signal processor (DSP), namely
threshold voltage, which results in dips in Vce,on curves S1 for IGBT gate signal, S2 to enable the GD output, S3 to
[14]. Conversely, the lower current measurement gener- enable the weak CS, and S4 to control the high-side IGBT.
ates much smaller self-heating; tiny dips in the Vce,on The required timing diagram for control signals is illus-
curves are therefore observed. trated in Figure 9(b).

0.78 0.765
IGBT-3A At Tamb = 28 °C
Collector-to-Emitter Voltage

Collector-to-Emitter Voltage

ΔTj = 120 °C Ice = 10 mA

IGBT-4A Tj,max = 150 °C Vge>12 V
Ice = 10 mA
0.763
Drop (Vce,on) (V)

Drop (Vce,on) (V)

IGBT-5A
0.77 Vge>12 V
At Tamb = 30 °C
ΔTj = 160 °C
0.761
Tj,max = 200 °C
0.76
0.759
IGBT-16A
IGBT-17A
0.75 0.757
0 500 1,500 2,500 0 2,000 4,000 6,000 8,000
Number of Cycles Number of Cycles
(a) (b)

FIG 8 Vce,on measurements at I ce = 10 mA (a) above and (b) below the SOA thermal limit.

September 2018 z IEEE Power Electronics Magazine 51

 Specifically, the circuit operates in three modes, i.e., the age Vth . Afterward, channel inversion takes place, which
Vth measurement, the Vce,on measurement, and the normal subsequently lowers the Vce , and the CS current is
operation modes, as illustrated in Figure 9(c)–(e). During diverted through the collector terminal. At this point,
each measurement mode, output- and emitter-node volt- the Vout reflects Vth of the device.
ages are fed back to a low-pass filter and then to the analog- 2) Vce,on measurement mode: Whereas during Vce,on mea-
to-digital converter pins of the DSP. surement mode, which is also illustrated in Figure 9(d),
1) Vth measurement mode: As illustrated by the red line in while S1 and S2 are high, the gate emitter is charged to
Figure 9(c), the CS is enabled using S3, and the current gate isolated supply voltage (+Vs) using the powerful CS
starts to charge the gate-emitter capacitance C ge raising within the GD integrated circuit. Thus, the CS current
the gate-emitter voltage (Vge) above the threshold volt- flows only through the collector terminal causing a

S1 +Vs CS +Vbus Timing Diagram

S2 S3
S3 S4 S1
S4 S4
S3

DSP
Output

Control Signals
Isolated + Vs S2
e
Output D2
S1
Vin c
D1
Gate S3
Driver g
S2 e
EN OUT
S4
e GND Vth Vce,on Normal
(a) (b)

S1 +Vcc CS +Vbus S1 +Vcc CS +Vbus

S2 S2
DSP S3 S4 DSP S3 S4
S3

S3

S4 +Vs S4 +Vs

Output D2 Output D2
S1 S1
Vin Vin
Gate D1 Gate D1
Driver Driver
S2 S2
EN OUT EN OUT

GND GND
(c) (d)

S1 +Vcc CS +Vbus

S2
DSP S3 S4
S3

S4 +Vs

S1 Output D2
Vin
Gate D1
Driver
S2
EN OUT

(e) GND

FIG 9 The proposed circuit (red = active and blue = inactive): (a) the schematic, (b) the timing diagram for control signals, (c) the
Vth measurement mode, (d) the Vce,on measurement mode, and (e) the normal GD operation. GND: ground.

52 IEEE Power Electronics Magazine z September 2018

 v­ oltage drop equivalent to the device’s Vce,on . Accord-
ingly, the Vout reflects Vce,on of the device. 16
3) Normal operation: Moreover, one of the circuit’s promi- Vge
nent features is that the same circuit can be used for 12 Output

Amplitude (V)
normal switching operations without any performance Vce,on
degradation. For normal operation, as illustrated in 8 CS Enable
Figure 9(e), the CS is disabled by keeping S3 at low while
the rest of the control signals are toggled to high with the 4
exception of S1, which now provides the required pulse-
width modulation signal to the IGBT gate. 0
90 110 130 150 170 190
Results from the Proposed Circuit Time (µs)
The P Spice simulation results for the proposed circuit are (a)
shown in Figure 10(a). Vout closely follows the Vge and Vce
waveforms during the Vth and Vce,on measurement modes,
respectively. To verify the simulated results, a prototype is
built. The actual photo of the prototype is shown in Figure 10(b).
Figure 10(c) illustrates the experiment’s waveforms from an
oscilloscope for a new DUT. The experiment’s waveforms
confirm the simulation results and validate the feasibility of
the proposed circuit.
Two aging tests, one above and one below the SOA
limit, have been performed to further corroborate the
simulation results. During the above-SOA test, T j has (b)
been kept variable between T j,max = 120-180 cC, with
T j,min = 30 cC and Ton /Toff = (12 s - 45 s) / (35 s -105 s). Sim­­ 80 µs
ilarly, for the below-SOA test, T j has been kept vari- 40 µs 40 µs
able between T j,max = 100-140 cC, with T j,min = 30 cC and CS 5 V/V
Enable
Ton /Toff = (12 s-23 s) / (35 s-55 s). The T j has been varied
Vth
to demonstrate the monitoring circuit’s efficacy under 5 V/V Measurement
Vout
variable-loading conditions. After a few hundred cycles, Vce,on
the aged samples are tested using both the proposed cir- Measurement
5 V/V
cuit and the curve tracer. The aged samples are still func- Vce,on
tional and show no sign of loss of gate control. Figure 11(a)
and (b) provides the Vth and Vce,on measurements compari- 10 V/V
Vge
son between the proposed circuit and curve tracer for the
20 µs
above-SOA test. Similarly, Figure 11(c) and (d) provides
the proposed circuit and curve tracer measurements com- (c)
parison for the below-SOA test. During all of these mea-
surements, I ce is maintained at approximately 1 mA.
FIG 10 The results of a prototype circuit: (a) the simulation,
The proposed circuit results therefore have offsets of a (b) the actual prototype snapshot containing both the GD and
few millivolts since the curve tracer and the proposed cir- the aging circuit, and (c) the oscilloscope waveforms for a new
cuit use slightly different current values. Other factors like IGBT sample.
the random thermal noise by the blocking diode (D2) and
trace parasitics or the random variations in the proposed
circuit’s measurement due to variable DUT placement, can to be used for RUL-estimation algorithms based on the Vth
also lead to this offset. In this application, the trend is criti- and Vce,on presented in [4] and [14].
cal for monitoring and it is similar between the proposed Another important aspect of the circuit is that it needs
circuit and curve tracer measurement. Thus, the efficacy of to be used as part of start and/or stop diagnostic test rou-
the circuit has been validated. tines. Since the device’s aging process spans a much longer
With the proposed circuit, a DSP can be used to continu- time, the information lost during normal operation can be
ously monitor the values of the aging precursors. Generally, safely neglected. It is also important to incorporate such
the DSP is capable of computing the relative parametric measurement circuits within the GD instead of the main
changes and the aging trends to estimate its state of health circuit to avoid noisy measurements due to trace para-
and RUL, however, this RUL estimation is outside the scope sitic inductances. In fact, the proposed circuit is ideally
of this article. Nevertheless, the circuit measurements are suited for intelligent power modules that generally house

September 2018 z IEEE Power Electronics Magazine 53

 6 0.84
Gate Threshold Voltage (Vth) (V)

Tj,min = 30 °C

On-State Collector-Emitter
5.8
0.82

Voltage (Vce,on) (V)

5.6 Tj,max = 120–180 °C
0.8
5.4
0.78
5.2

5 0.76

4.8 0.74
0 2,000 4,000 6,000 8,000 0 2,000 4,000 6,000 8,000
Number of Cycles Number of Cycles
(a) (b)

5.75 0.78
Gate Threshold Voltage (Vth) (V)

Tj,min = 30 °C

On-State Collector-Emitter
5.7 0.77

Voltage (Vce,on) (V)

Tj,max = 100–140 °C 0.76
5.65
0.75
5.6
0.74
5.55
0.73
5.5 0.72

5.45 0.71
0 2,000 4,000 6,000 8,000 10,000 0 2,000 4,000 6,000 8,000 10,000
Number of Cycles Number of Cycles
(c) (d)

Circuit Measurement Curve Tracer Measurement

FIG 11 The comparative results between the proposed circuit and a curve tracer: (a) the Vth comparison for an above-SOA test,
(b) the Vce,on comparison for an above SOA test, (c) the Vth comparison for a below-SOA test, and (d) the Vce,on comparison for a
below-SOA test.

six IGBTs and their respective GDs next to each other in a information can be used to give further information about
single, plastic-encapsulated package [19]. So, the proposed the actual die condition and verify the previously estimated
circuit can be integrated next to respective GD circuits RUL using Vce,on .
within the IPM conveniently. The implementation of the circuit has been validated by
comparing the Vth and Vce,on measurements with the test
Conclusions results from the highly sensitive and accurate curve tracer.
To advance the state-of-the-art converter design, a cost- The results show good agreement between the curve tracer
effective in situ Vth and Vce,on measurement circuit has been and proposed circuit measurements. The measurement
proposed that can easily be incorporated into conventional procedure takes less than 100 ns, which is feasible for most
GD circuits. The proposed circuit can be used as part of a real-world applications.
regular start and/or stop diagnostic routine in the power
converter without any significant RUL estimation error About the Authors
because aging is a much longer process and information lost Syed Huzaif Ali (syedhuzaifali@utdallas.edu) received his
during normal operation may become trivial. B.E. degree in electronics engineering from Nadirshaw
Compared with the state-of-the-art aging detection Eduljee Dinshaw University, Karachi, Pakistan, in 2010. He
methods, the proposed circuit provides a simple, accurate, is currently pursuing his Ph.D. degree with the University of
and easy-to-implement design at the GD side for state-of- Texas at Dallas, Richardson. Since 2015, he has worked at
health and condition monitoring of IGBTs. With the pro- the Power Electronics and Drives Laboratory in the Engi-
posed circuit, no complex compensation and/or constant neering and Computer Science Department at the Universi-
correction is required since the Vce,on can be directly ty of Texas at Dallas. His research interests include real-time
used for estimating the RUL of the IGBT. Additionally, Vth fault diagnosis of power converters and remaining useful

54 IEEE Power Electronics Magazine z September 2018

lifetime estimation of power devices. He is a Student Mem- [4] S. Dusmez, S. H. Ali, M. Heydarzadeh, A. S. Kamath, H. Duran, and B.
ber of the IEEE. Akin, “Aging precursor identification and lifetime estimation for thermally
Xiong Li (xiong.li@ti.com) received his B.E. degree in aged discrete package silicon power switches,” IEEE Trans. Ind. Appl., vol.
electrical engineering from the Central South University, 53, no. 1, pp. 251–260, Jan.-Feb. 2017.
Changsha, China, in 2011. He is currently working toward [5] Y. Avenas, L. Dupont, and Z. Khatir, “Temperature measurement of
his Ph.D. degree at the University of Texas at Dallas, Rich- power semiconductor devices by thermo-sensitive electrical parameters—A
ardson. He worked at the Power Electronics and Drives review,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 3081–3092, June
Laboratory in the Engineering and Computer Science 2012.
Department at the University of Texas at Dallas for four [6] S. Dusmez, H. Duran, and B. Akin, “Remaining useful lifetime estimation
years. He is currently working as a systems engineer at for thermally stressed power MOSFETs based on on-state resistance varia-
Texas Instruments, Dallas. His research interests include tion,” IEEE Trans. Ind. Appl., vol. 52, no. 3, pp. 2554–2563, May-June 2016.
design and control of multilevel converters for renewable [7] S. Be˛czkowski, P. Ghimre, A. R. de Vega, S. Munk-Nielsen, B. Rannestad,
energy systems, and integrated power electronic converters. and P. Thøgersen, “Online Vce measurement method for wear-out monitoring
He is a Student Member of the IEEE. of high power IGBT modules,” in Proc. 15th European Conf. Power Elec-
Anant S. Kamath (anantkamath@ti.com) received his tronics and Applications (EPE ’13 ECCE-Europe), 2013, pp. 1–7.
B. Tech. degree in electrical engineering from the Indian Insti- [8] Y. Avenas, L. Dupont, N. Baker, H. Zara, and F. Barruel, “Condition moni-
tute of Technology, Madras. Since 2002, he has been a toring: A decade of proposed techniques,” IEEE Ind. Electron. Mag., vol. 9,
­systems engineer with Texas Instruments, Dallas. He is no. 4, pp. 22–36, Dec. 2015.
responsible for definition and application support for indus- [9] M. A. Eleffendi and C. M. Johnson, “Evaluation of on-state voltage
trial and automotive high-voltage isolation products. He is VCE(ON) and threshold voltage Vth for real-time health monitoring of IGBT
also responsible for product compliance to component and power modules,” in Proc. 17th European Conf. Power Electronics and
end-equipment standards that deal with isolation, electrical Applications (EPE ‘15 ECCE-Europe), 2015, pp. 1–10.
safety, and electromagnetic compatibility. His was previously a [10] P. O’Connor, R. W. Cox, and J. M. Anderson, “Near real-time incipient
designer and architect of phase-locked loops and clock sys- fault detection in IGBT switches,” in Proc. 40th Annu. Conf. IEEE Indus-
tems, high-speed serializers/deserializers and high-voltage trial Electronics Society (IECON), 2014, pp. 4484–4491.
digital isolation devices. He is a Senior Member of the IEEE. [11] D. Astigarraga, F. M. Ibanez, A. Galarza, J. M. Echeverria, I. Unanue, P.
Bilal Akin (bilal.akin@utdallas.edu) received his Ph.D. Baraldi, and E. Zio, “Analysis of the results of accelerated aging tests in insu-
degree in electrical engineering from the Texas A&M Uni- lated gate bipolar transistors,” IEEE Trans. Power Electron., vol. 31, no. 11,
versity, College Station, in 2007. He was a research and pp. 7953–7962, Nov. 2016.
development (R&D) engineer with Toshiba Industrial Divi- [12] M. Bouarroudj, Z. Khatir, J. P. Ousten, F. Badel, L. Dupont, and S. Lefe-
sion, Houston, Texas, from 2005 to 2008. From 2008 to 2012, bvre, “Degradation behavior of 600V–200A IGBT modules under power
he worked as an R&D engineer at C2000 Embedded Control cycling and high temperature environment conditions,” Microelectron.
Group, Texas Instruments, Dallas. Since 2012, he has been Reliab., vol. 47, no. 9–11, pp. 1719–1724, Sept. 2007.
with the University of Texas at Dallas, Richardson, as an [13] S. H. Ali, S. Dusmez, and B. Akin, “A comprehensive study on variations
assistant professor. He is the recipient of the National Sci- of discrete IGBT characteristics due to package degradation triggered by
ence Foundation CAREER 2015 Award, the Jonsson School thermal stress,” in Proc. IEEE Energy Conversion Congr. Expo. (ECCE),
Faculty Research Award, and the Top Editors Recognition 2016, pp. 1–6.
Award from IEEE Transactions on Vehicular Technology [14] S. H. Ali, M. Heydarzadeh, S. Dusmez, X. Li, A. Kamath, and B. Akin,
Society. He is an associate editor of IEEE Transactions on “Lifetime estimation of discrete IGBT devices based on Gaussian process,”
Industry Applications and IEEE Transactions on Vehicu- IEEE Trans. Ind. Appl., vol. 54, no. 1, pp. 395–403, Jan.-Feb. 2018.
lar Technology. His research interests include the design, [15] W. Lai, M. Chen, L. Ran, O. Alatise, S. Xu, and P. Mawby, “Low ΔTj stress
control, and diagnosis of electric motors and drives, digital cycle effect in IGBT power module die-attach lifetime modeling,” IEEE
power control and management, fault diagnosis, and condi- Trans. Power Electron., vol. 31, no. 9, pp. 6575–6585, Sept. 2016.
tion monitoring of power electronics components and ac [16] U. M. Choi, F. Blaabjerg, S. Jørgensen, F. Iannuzzo, H. Wang, C. Uhren-
motors. He is a Senior Member of the IEEE. feldt, and S. Munk-Nielsen, “Power cycling test and failure analysis of
molded intelligent power IGBT module under different temperature swing
References durations,” Microelectron. Reliab., vol. 64, pp. 403–408, Sept. 2016.
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September 2018 z IEEE Power Electronics Magazine 55