HA13614FH

Combo (Spindle & VCM) Driver

ADE-207-246D (Z)
Preliminary
5th Edition
October 1998

Description

This COMBO driver for HDD application consists of sensorless spindle driver and BTL type VCM driver.

“PWM soft switching function” for low power dissipation and less commutation acoustic noise at the same
time is implemented by using the IPIC* process.

Note: Intelligent P ower IC

Features

• PWM soft switching drive

• Small surface mount package: FP-48T
• Low thermal resistance: 30°C/W with 4 layer multi glass-epoxy board
• Low output on resistance
 Spindle 1.2 Ω Typ
 VCM 1.4 Ω Typ
• TTL compatible input level (with 3.3 V logic interface)
• High precision reference voltage output (for 3.3 V power supply)

Functions

• 16 bit serial port

• 2.0 A Max/3-phase spindle motor driver with PWM soft switch function
• 1.5 A Max BTL VCM driver with low crossover distortion
• PWMDAC for VCM drive current control
• Power off brake function for spindle motor
• Auto retract with constant output voltage
• Booster
• Internal Protector (OTSD, LVI)
• Precision power monitor
• OP amplifier
HA13614FH
Pin Arrangement

12VGOOD
DACOUT

VIPWMH

SEENAB
VIPWML
DELAY

VREF

DATA

SCLK
POR
LVI1

CLK
TABGND
48 47 46 45 44 43 42 41 40 39 38 37

OP1OUT 1 36 COMM
OP1IN(−) 2 35 PHASE
OP2IN(+) 3 34 SPNCTL
Vss 4 33 UFLT
OP2OUT 5 32 NFLT
PC 6 31 VpsIN

TABGND TABGND

VCMPS 7 30 VpsOUT
VCMN 8 29 FLTOUT
Rs 9 28 Vpss
VCMIN 10 27 W
VCMP 11 26 ISENSE
VCMSLC 12 25 CT

13 14 15 16 17 18 19 20 21 22 23 24
LVI2
RETPOW
RETSET
BC1
BC2
Vpsv
VBST

BRKDLY
U
V
RNF
BRK

TABGND

(Top View)

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 HA13614FH

Pin Description
Pin No. Pin Name Function
1 OP1OUT Output of OP amp. 1
2 OP1IN(–) Inverted input of OP amp. 1
3 OP2IN(+) Non-inverted input of OP amp. 2
4 Vss Power supply for +5 V
5 OP2OUT Output of OP amp. 2
6 PC External time costant connection terminal for phase compensation of VCM
driver
7 VCMPS Current sensing terminal for VCM driver
8 VCMN Output of VCM driver (Inverted output of VCMP)
9 Rs Current sensing terminal for VCM driver (differential input for VCMPS)
10 VCMIN Input of VCM driver (differential input for VREF)
11 VCMP Output of VCM driver (inverted output of VCMN)
12 VCMSLC External capacitor connection terminal for stabilizing internal reference
voltage of VCM driver
13 RETPOW Power supply terminal of retract driver
14 RETSET Output voltage set up terminal of retract driver
15 BC1 External capacitor connection terminal for pumping of booster
16 BC2
17 Vpsv +12 V power supply for VCM driver
18 VBST Output of booster circuit
19 BRKDLY Time constance set up terminal of delayed brake
20 U U-phase output of spindle motor driver
21 V V-phase output of spindle motor driver
22 RNF Current sensing terminal for spindle motor driver
23 BRK External capacitor connection terminal for power off brake
24 LVI2 Resistor connection terminal for set up the threshold of +3.3 V power monitor
25 CT Center tap connection terminal for spindle motor
26 ISENSE Input of PWM comparator
27 W W-phase output of spindle motor driver
28 Vpss +12 V power supply for spindle motor driver
29 FLTOUT PWMDAC output for current control of spindle motor driver
30 VpsOUT Output of power supply switch
31 VpsIN Input of power supply switch (+12 V)
32 NFLT Output of pre-filter for B-EMF sensing (capacitor connection terminal)
33 UFLT

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HA13614FH

Pin Description (cont)

Pin No. Pin Name Function
34 SPNCTL PWMDAC input for current control of spindle motor driver
35 PHASE Toggle signal output for zero-crossing timing of B-EMF
36 COMM Commutation signal input for spindle motor driver during synchronous driving
37 CLK Master clock input of commutation logic circuit
38 SCLK Clock input of serial port for data strobe
39 SEENAB Enable signal input of serial port
40 DATA Data signal input of serial port
41 12VGOOD Output of power monitor for +12 V power supply (open drain)
42 VIPWML PWMDAC input for current control of VCM driver
43 VIPWMH
44 VREF Output of internal reference voltage
45 DACOUT PWMDAC output for current control of VCM driver
46 DELAY Capacitor connection terminal for set up the power on reset time
47 LVI1 Resistor connection terminal for set up the threshold of +12 V power monitor
48 POR Output of power on reset signal
TAB GND Ground of this IC

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 HA13614FH
Block Diagram

Vps (+12V)
Vss (+5V) C111
R109
C112 C116
C113 C114
Vss VpsIN VpsOUT Vpss
4 23 19 31 30 28
BRK BRKDLY
1
CLK 37 CLK CT
128
25
C101 UFLT VBST
33 BRAKE
B-EMF Brake
NFLT POR
32 Amps OTSD control U
U 20
C102 CLK Spindle
EXTCOM Commutation driver V
logic V 21
COMM 36
PHASE 35 W
W 27
SPN RNF
RNF
GAIN Current 22
Input
SPNCTL 34 control
PWMOUT

ISENSE
B-EMF

filter (PWM) 26
(TESTOUT)
C103 29 Vpsv
17
FLTOUT C110
1.4V ref. Selector
VBST RETPOW
+ OP Amp.1 MASK 13
− TEST R106
OP1IN(−) 2 RETSET
14
Retract C115
OP1OUT 1
driver
OP2IN(+) 3 + OP Amp.2
R105
− VCMSLC
12
VBST C109
OP2OUT 5 RS
VCMP
P 11
VCMIN 10 +
VCM PC
C104 6 RL
VREF − driver
44 VCMN R104 C108
N 8
VIPWMH VCMPS
43 7
PWM
C1 VIPWML decoder VCMENAB
42 Rs
9
DACOUT Vref(=5.3V) Vss (+5V)
45 41
POW DWN 12VGOOD
OTSD (Open Drain) R110
STANDBY
Serial BIAS
SCLK 38 SPNENAB Vps Vss
input EXTCOM Vss (+5V)
DATA 40 BRAKE
VCMENAB Power
monitor2 POR R103
SOFTSW (L: RESET)
SEENAB 39 TEST 48
Vss
SPNGAIN POR
RESET
delay
Power VBST
monitor1 CLK VBST C107
Booster 18
LVI1 LVI2 DELAY
TAB 47 24 46 15 16
Vps R101 R107 Vdd BC1 BC2
(+12V) (+3.3V) C105
R102 R108 C106
C117

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Serial Port

Construction

SEENAB
D0 to D15
Serial
SCLK port
to each block
DATA

RESET *
Note: When POR = Low, internal RESET signal becomes High and when RESET = High,
all bit of serial port are set up default value as shown in table 2.

Figure 1 Construction of Serial Port

Table 1 Truth Table of Internal RESET Signal

Input Ou tput Note

POR RESET
Low High 1
Open Low 1
Note: 1. When +5 V or +3.3 V power supply goes to Low, then POR = Low.
POR output is able to construct the wired logic with external signal.

Input Data

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 2 Input Data

The serial port is required the 16 bits data (D0 to D15). When the data length is less than 16 bits, the
internal register will not be up dated. And when the data length is more than 16 bits, this register will take
later 16 bits and ignore the faster bit.

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Bit Assingnment

Table 2 Bit Assingnment of Serial Port

Bit Symbol 1 (= High) 0 (= Low) Default Note

D0 STANDBY Active Stand by 0 1
D1 VCMENAB VCM enable VCM disable 0 1
D2 SPNENAB Spindle enable Spindle disable 0 1
D3 BRAKE Brake enable Brake disable 0 1
D4 SENSEN B-EMF sense enable B-EMF sense disable 0 2
D5 VARCNT Variable count Normal count 0 2
D6 EXTCOM External commutation Internal commutation 0 2
D7 SRCTL1 High slew rate Low slew rate 0 3
D8 SRCTL2 Commutation time select (See table 4) 0 4
D9 SRCTL3 0 4
D10 OFFTIME1 Off time select of PWM drive (See table 5) 0 5
D11 OFFTIME2 0 5
D12 SPNGAIN High gain Low gain 0 6
D13 RETRACT Retract Not retract 0 1
D14 TEST1 For testing 0 7
D15 TEST2 0 7
Note: 1. The priority of operation for each bit is as shown in table 3.
2. This bit is using for start up of spindle motor. Please refer to the application note explained
about start up of spindle motor.
3. The slew rate during every commutation of spindle motor is selectable by using this bit. Please
select the suitable value of this bit for your motor.
4. This bit is used for setting up the commutation time (refer to figure 9) of spindle motor as shown
in table 4.
5. This bit is used for setting up the off time at PWM driving of spindle motor as shown in table 5.
6. The gain of current control for spindle motor is selectable by using this bit. Please select the
suitable value of this bit for your motor.
7. This bit will be used in fabrication test. Please set up D15 = “0” normally.
SPNCTL terminal (pin 35) is using for output terminal in the case of “1” for testing. Then please
do not input signal into pin 35 from outside.

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Table 3 Truth Table

Input Driver Output

OTSD 12VGOOD STAND BY SPNENAB BRAKE RETRACT VCMENAB Spindle VCM Retract Power
*1 Driver Driver Driver Switch

Enable Low ×*2 × × × × Braking Cut off On Cut off

Disable Low × × × × × Braking Cut off On Cut off

Disable High Low × × × × Braking Cut off Cut off Cut off

Disable High High 0 0 0 0 Cut off Cut off Cut off On

Disable High High 0 1 0 0 Braking Cut off Cut off On

Disable High High 1 × 0 0 On Cut off Cut off On

Disable High High 0 0 0 1 Cut off On Cut off On

Disable High High 0 1 0 1 Braking On Cut off On

Disable High High 1 × 0 1 On On Cut off On

Disable High High 0 0 1 × Cut off Cut off On On

Disable High High 0 1 1 × Braking Cut off On On

Disable High High 1 × 1 × On Cut off On On

Note: 1. The 12VGOOD terminal is open drain output type. The 12VGOOD signal output is determined by
the power monitor output for 12 V power supply, POR output and OTSD signal as shown in the
table below.

12 V Supply POR OTSD 12VGOOD

Cut off × × Low
× Low × Low
× × Enable Low
Normal High Disable High

2. The symbol “×” means “Don’t care”.

Table 4 Commutation Time

SRCTL2 SRCTL3 Commutation Time (s)

0 0 24 × (128 / fclk)
0 1 16 × (128 / fclk)
1 0 12 × (128 / fclk)
1 1 No slew rate control
Note: The “fclk” is the frequency on pin “CLK”. (Recommendation: 20 MHz)

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 HA13614FH
Table 5 OFF Time at PWM Drive

OFFTIME1 OFFTIME2 OFF Time (s)

0 0 1 × (32 / fclk) + (4 / fclk)
0 1 2 × (32 / fclk) + (4 / fclk)
1 0 3 × (32 / fclk) + (4 / fclk)
1 1 4 × (32 / fclk) + (4 / fclk)

Data Input Timing

SEENAB Vth (= 2.4V Typ)

t1
t0 t2
SCLK Vth

t3 t4
DATA Vth D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK
Up date point
Note: Data input timing (Latch point, Up date point) is t0: ≥ 20ns Latch point
determined by CLK as shown above, and t1 t2: ≥ 40ns
requires two or more clock pulse. t3: ≥ 40ns
t4: ≥ 40ns

Figure 3 Input Timing of Serial Port

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HA13614FH

Timing Chart

Power on Reset (1)

Vhys
Vsd

Vpss, Vss
and Vdd

POR
tpor
12VGOOD

1.0V *2 *2
Max
0
t
Note: 1. Please refer to external components table about how to determine the threshold voltage
Vsd and delay time tpor.
2. Operation for Vss.

Figure 4 Operation of the Power Monitor (1)

Power on Reset (2)

Vpss, Vss
or Vdd tpor
tpor

POR <1µs <1µs

,, ,,
12VGOOD

,,,,
Spindle ON
Driver OFF
VCM ON
Driver OFF
Retract Retract
Driver
Note: This retract driver requires the electrical power from B-EMF of spindle motor.

Figure 5 Operation of the Power Monitor (2)

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 HA13614FH

Power on Reset (3)

Vss

Vps

tpor tpor
POR

12VGOOD

Spindle ON
Driver OFF
VCM ON
Driver OFF
Retract ON
Driver OFF

Figure 6 Operation of the Power Monitor (3)

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HA13614FH

Power Off Retract & Brake

Vps

GND

Vpss

GND

POR
GND
ON
Power
SW
OFF

Normal
U operation
Braking
GND
tBRKDLY*

Normal
V, W operation
Cut off
GND

Retract off
VCMP VCM on Vretout
GND

Retract off
VCMN VCM on
Vretsat
GND
t
Note: Please see the External Component table about setting delay time tBRKDLY.

Figure 7 Operation of Power Off Retract & Brake

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 HA13614FH

Start-up of the Spindle motor

• Not using external commutation mode

SPNENAB

EXTCOM Low

COMM

PHASE

IU 0

IV 0

IW 0

Synchronous driving* B-EMF sensing driving

• Using external commutation mode

SPNENAB

EXTCOM

COMM

PHASE

IU 0

IV 0

IW 0

Synchronous driving* B-EMF sensing driving

Note: “Synchronous driving” is defined as the period after changing SPNENAB = L to H until
the first positive edge of the PHASE signal.

Figure 8 Start-up of the Spindle Motor

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HA13614FH

Commutation Timing of the Spindle motor

U V W

B-EMF CT

PHASE
(EXTCOM=0)
*1

PHASE
(EXTCOM=1)

Vpss
B-EMF
PWM PWM
OUTPUT Vpss/2

PWM

GND

tspndly
*2 *3
IU 0

tsrctl
commutation
time

Note: 1. In the case of external commutation mode (EXTCOM=1), the signal PHASE will toggle at every B-
EMF zero-crossing, and selected the internal commutation mode (EXTCOM=0), the PHASE will
have the same period as B-EMF of the spindle motor.
2. This is delay time by pre-LPF of the B-EMF amplifier. This delay time can be adjust by the value
of external filter capacitor C101, C102. To get the maximum driving efficiency of the spindle
motor, these capacitor value should be chosen as equation (17) in the “External components”
section.
3. The slew rate of every commutation timing is controllable by changing the SRCTL1, SRCTL2 and
SRCTL3 in the serial port.

Figure 9 Commutation Timing of the Spindle motor

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 HA13614FH

Application

Vps
(+12V)
C111

31
C116 VpsIN
19 BRKDLY
R109
C112
23 BRK
C101 VpsOUT 30
33 UFLT
C102 Vpss 28
32 NFLT C114
C103
29 FLTOUT
Vss CT 25
R110 U 20
41 12VGOOD
35 PHASE
34 SPNCTL V 21
W 27
36 COMM RNF 22
RNF
MPU 37 CLK ISENSE 26
38 SCLK
HA13614FH

RETPOW 13
40 DATA
C110
Vpsv 17
39 SEENAB
C109 R101
43 VIPWMH VCMSLC 12
C115 R106 R102
42 VIPWML RETSET 14
R105
3 OP2IN(+)
R3 VCMP 11
5 OP2OUT RS
VCMPS 7
10 VCMIN R104 C108 RL
C2 PC 6
R2 C3
45 DACOUT VCMN 8
C1 C104
44 VREF Rs 9 Vdd
(+3.3V)
LVI1 47
R107
2 OP1IN(−)
LVI2 24
1 OP1OUT R108 C117
Vss R103 C113 BC1 15
(+5V) 4 Vss
C106
BC2 16
to MPU 48 POR
C107
46 DELAY VBST 18
C105 TAB

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HA13614FH

External Components
Recommendation
Parts No. Value Purpose Note
R101 — Set up threshold of power monitor for Vps 1
R102 —
R103 ≥ 5.6 kΩ Pull up for POR terminal
R104 — Gain dumping for VCM driver 5
R105 — Set up output voltage of retract driver for pin VCMP 6
R106 —
R107 — Set up threshold of power monitor for Vdd 1
R108 —
R109 — Set up time constance of delayed brake 12
R110 ≥ 5.6 kΩ Pull up for 12VGOOD terminal
R2 — Filter constant of LPF 3
R3 —
Rnf 0.33 Ω Current sensing for spindle motor 7
RS 0.47 Ω Current sensing for VCM 4
C101, C102 — Pre-filter of B-EMF amplifier 10
C103 — Filter of PWMDAC for current control of spindle motor 9
C104 0.1 µF Filter of internal reference output
C105 0.1 µF Set up delay time of POR signal 8
C106 0.22 µF Boost up of power supply
C107 2.2 µF Stabilizing boost up voltage
C108 — Gain dumping for VCM driver 5
C109 0. 1 µF Stabilizing reference voltage of VCM driver
C110 0.1 µF By passing of power supply
C111 0.1 µF
C112 — Keeping brake function 12
C113 0.1 µF By passing of power supply
C114 0.1 µF
C115 — Stabilizing output voltage of retract driver for pin VCMP 11
C116 — Set up time constance of delayed brake 12
C117 0.1 µF Stabilizing LVI2 terminal
C1 — Filter constant of LPF 3
C2 —
C3 —

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 HA13614FH
Notes: 1. The operation threshold voltage of Vps or Vdd is determined by resistor R101, R102 or R107,
R108 as follows.

POR
(for Vdd)
12VGOOD
(for Vps)
Vdwn Vup Vps

• for Vps
Recovery R101
voltage Vup(Vps) = (Vsd1 + Vhys3) ⋅ 1 + [V]
R102 (1)

Cut off R101

voltage Vdwn(Vps) = Vsd1 ⋅ 1 + [V]
R102 (2)

where, Vsd1 : Operating voltage of the power monitor [V] (refer to Electrical Charasteristics)
Vhys3 : Hysteresis voltage of the power monitor [V] (refer to Electrical Charasteristics)
• for Vdd
Recovery R107
voltage Vup(Vdd) = (Vsd1 + Vhys4) ⋅ 1 + [V]
R108 (1)’

Cut off R107

voltage Vdwn(Vdd) = Vsd1 ⋅ 1 + [V]
R108 (2)’

where, Vhys4 : Hysteresis voltage of the power monitor [V] (refer to Electrical Charasteristics)
2. The relation between PWMDAC input VIPWMH, VIPWML for VCM driver current control and VCM
driver input (VCMIN – VREF) is determined by following equation. (refer to below figure)
6.4
VCMIN − VREF = ⋅ (64 ⋅ DPWMH + DPWML) − 3.2
6500 (3)

where, VREF : Internal reference voltage [V] (refer to Electrical Charasteristics)

DPWMH : Duty of input signal on terminal VIPWMH [%]
DPWML : Duty of input signal on terminal VIPWML [%]

VREF VREF
5.3V
VIPWMH R1L R0
5.3V
R1H DACOUT R2 R3 OP2IN(+)OPAmp.2 VREF
+ to VCM driver
VIPWML C1 C2 C3 GND R4 −
R1=R1L//R1H//R0 R5 VCMIN
=740Ω 5.3±3.2V
OP2OUT R5/R4=0.604
VCMIN

3. The 3rd order LPF at next stage of PWMDAC is characterized by internal OP amp. and capacitor
C1, C2, C3 and resistor R2, R3. These components value are determined by following equations.
1
C1 = [F]
2 ⋅ π ⋅ fc ⋅ R1 (4)

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HA13614FH
C3 = 220 ⋅ 10−12 [F] (5)

1 4⋅k+1− 8⋅k+1
C2 = ⋅ ⋅ C3 [F]
2 k2 (6)

k 2
R2 = ⋅ [Ω]
4⋅k+1− 8⋅k+1 2 ⋅ π ⋅ fc ⋅ C3
(7)

R3 = R2 [Ω] (8)

R5
k= = 0.604
R4 (9)

where, f c : Cut off frequency of 3rd order LPF [Hz]

R1 : Output resistance of PWMDAC [Ω] (refer to Electrical Characteristics)
4. The driving current of VCM Ivcm is determined by following equation.
Vvcmin − VREF
Ivcm = ⋅ Gvcm [A]
RS
(10)

where, Vvcmin : Input voltage on terminal VCMIN (pin 10) [V]

Gvcm : Transfer function of VCM driver [dB] (refer to Electrical Characteristics)
5. Capacitor C108 and resistor R104 are useful to dump the gain peaking of VCM driver. These
components also determine the gain band width of VCM driver BW1 which should be chosen less
than 10 kHz, as follows.
12π ⋅ BW1 ⋅ Lvcm
R104 = [kΩ]
RS
(11)

Lvcm 1
C108 = ⋅ [F]
RS + RL R104
(12)

where, RL : Coil resistance of VCM [Ω]

Lvcm : Coil inductance of VCM [H]
6. Retract current Iret is determined by following equation.
R105
0.7 × 1 + − Vretsat
R106
Iret = [A]
RS + RL
(13)

Vretsat : Output saturation voltage of retract driver [V]

(refer to Electrical Characteristics)
7. The relation between duty of input signal on terminal SPCNTL (pin 34) and output current of
spindle motor driver Ispn is as follows.
Vref − Voff1
Ispn = ⋅ duty [A]
Rnf (14)

Vref : Reference voltage of current control amplifier [V]

Vref = Vref2 (@SPNGAIN = 1)
Vref = Vref3 (@SPNGAIN = 0)
Voff1 : Offset voltage of current control amplifier [V]
(refer to Electrical Characteristics)

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 HA13614FH
8. The delay time of the power monitor for start up is as follows.
tpor = 140 ⋅ C105 [ms] (15)

9. The cut off frequency fcpwm of the filter for current control input of the spindle motor is as
follows.
1
fcpwm = [Hz]
2π × 20k ⋅ C103 (16)

10. To get the maximum driving efficiency for spindle motor, the capacitor C101, C102 should be
chosen as following equation.
C101 = 0.8 ⋅ C102 (17-1)

tan(π/6) 1
C102 = ⋅ [F]
2π ⋅ 13k fbemf (17-2)

fbemf : Back EMF frequency at standard rotation speed of the spindle motor [Hz]
where, please set the value of C101, C102 so that C101 < C102 can be kept including the
accuracy of the absolute value to assure the stability of motor starting and speed lock state.
11. To stabilize output voltage od retract driver, the capacitor C115 should be chosen as following
equation. Please chose same values for C115.
3 ⋅ 10−6
C115 = [F]
2π ⋅ (R105 // R106) (18)

12. Time tBRKDLY of the delayed brake of V, W phase for retract is determined by resistor R109 and
capacitor C112, C116 as following equation.

tBRKDLY = − C116 ⋅ R109 ⋅ ln 1 −

Vthb C116
⋅ 1+ [s]
C116 VBRK0 C112
1+
C112 (19)

where, Vthb : Threshold voltage that output MOS transistor of spindle motor driver is
operated.
VBRK0 = Vpss – 0.7 [V]
Vpss : +12 V power supply for spindle motor driver
and, please select capacitor C112 and C116 that the ratio of C112/C116 is more than 3 times,
because the last voltage of BRK and BRKDLY terminals falls if the value of C116 is big for C112,
and effect of brake goes down.

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Absolute Maximum Ratings

Item Symbol Rating Unit Note
Power supply Vss 6.0 V 1
Vpss 15 V 2
Vpsv 15 V 2
Spindle current Ispn 2.0 A 3
VCM current Ivcm 1.5 A 3
Input voltage Vin –0.33 to Vss +1.0 V 4
Power dissipation PT 5.0 W 5
Junction temperature Tj 150 °C 6
Storage temperature Tstg –55 to +125 °C
Notes: 1. Operating voltage range is 4.25 V to 5.5 V. If power supply voltage exceed this operating range
in actual application, the reliability of this IC can not be guaranteed.
2. Operating voltage range is 10.2 V to 13.8 V.
3. ASO (Area of Safety Operation) of each output transistor is shown in figure 10.
Operating locus must be within the ASO.
4. Applied to CLK, COMM, SPNCTL, VIPWMH, VIPWML, SCLK, DATA and SEENAB.
5. Thermal resistance θj-a ≤ 30°C/W (Using 4 layer glass epoxy board)
6. Operating junction temperature range is 0°C to +125°C.

for Spindle motor driver for VCM driver

10 10

t = 1 ms
t = 10 ms t = 1 ms
2.0 t = 100 ms t = 10 ms
IDS (A)

IDS (A)

1.5 t = 100 ms
1.0 1.0

0.10 0.10
1 10 15 100 1 10 15 100
VDS (V) VDS (V)

Figure 10 ASO of Output Transistor

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Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vpss = Vpsv = 12 V)

Applicable
Item Symbol Min Typ Max Unit Test Conditions Pins Note

Supply current Iss0 — 2.0 3.4 mA Stand by, Vss

fclk=20MHz

Iss1 — 3.2 4.2 mA fclk=20MHz

Ips0 — 1.6 2.4 mA Stand by Vpss & Vpsv 1

Ips1 — 42 56 mA

Power Output on Ron0 — 0.2 0.3 Ω VpsIN

switch resistance VpsOUT

Output Icer0 — — ±10 µA VpsOUT=15V,

leacage VpsIN=0V,
current Vss=0V,
Vpss=Vpsv=0V

Logic Input low Iil1 — — ±10 µA Vil=0V CLK,

input current COMM,

Input high Iih1 — — ±10 µA Vih1=5V SCLK ,

current DATA,

Input low Vil1 — — 0.8 V SEENAB,

voltage VIPWMH,

Input high Vih1 2.0 — — V VIPWML,

voltage SPNCTL

Clock fclk 19 — 21 MHz

frequency

Logic Output high Voh1 4.6 — — V Ioh=1mA PHASE

output1 voltage

Output low Vol1 — — 0.4 V Iol=2mA

voltage

Logic Output Icer1 — — ±10 µA Vo=5.5V POR, 5

output2 leakage 12VGOOD
current

Output low Vol2 — — 0.4 V Iol=2mA

voltage

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Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vpss = Vpsv = 12 V) (cont)

Applicable
Item Symbol Min Typ Max Unit Test Conditions Pins Note

Spindle Output on Ron1 — 1.2 1.5 Ω Io≤1.5A U, V, W 2

motor resistance
driver

On resistance Ron2 — — 3.0 Ω Io=0.4A,

during braking BRK=3V

Output Icer3 — — ±2 mA Vo=15V

leakage
current

Output clamp Vf — 0.9 1.2 V If=0.5A

diode forward
voltage

Output MOS Vthb — 2 — V Ron=(Ron/2)×10

operating
threshold
voltage

Leakage Icer4 — — 0.6 µA Vpsv=GND, BRK,

current on Vo=8V BRKDLY
brake terminal

Input filter & Vref2 — 490 ±10% mV SPNGAIN=1, ISENSE,

current control SPNCTL=Vss FLTOUT
amp.

Vref3 — 250 ±10% mV SPNGAIN=0,

SPNCTL=Vss

Current Voff1 — –10 ±20 mV SPNCTL=GND

control amp.
offset voltage

B-EMF Input offset Voff2 — — ±20 mV Synchronous drive U, V, W,

amp. voltage UFLT,
NFLT

Voff3 — — ±20 mV B-EMF sens drive

Input Vhys1 70 90 110 mVp-p Synchronous drive

hysteresis
voltage

Vhys2 35 45 55 mVp-p B-EMF sens drive

22
 HA13614FH

Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vpss = Vpsv = 12 V) (cont)

Applicable
Item Symbol Min Typ Max Unit Test Conditions Pins Note

VCM Output on Ron2 — 1.4 1.8 Ω Io≤1.0A VCMP, 2

driver resistance VCMN

Output Icer5 — — ±2 mA Vo=15V

leakage
current

Output Vq — Vpsv/2 ±5% V RS=0.47Ω, RL=10Ω,

quiescent L=2mH,
voltage R104=1.6MΩ,
C108=120pF

Transfer gain Gvcm — –18 — dB VCMPS, Rs 4

Gain band BW1 — 10 — kHz

width

Input Rin — 60 ±30% kΩ VCMIN

resistance

PWM Input Tpwm 50 — — ns VIPWMH,

DAC minimum VIPWML
pulse width

Output R1 — 740 ±30% Ω FLTOUT

resistance

Output voltage Vo1 — 0.4 ±10% V VIPWMH=High, VCMPS, Rs 3

VIPWML=High

Vo2 — 0.4 ±10% V VIPWMH=Low,

VIPWML=Low

Output offset Voff4 — — ±10 mV

voltage

Gain ratio Rat — 64 ±2% — Rat=VIPWMH/

VIPWML

Reference Vref — 5.3 ±5% V Io=±1mA VREF

voltage

Retract Retract driver Vretout — 1.0 ±8% V Vpss=6.0V, VCMP

driver output voltage R105=13k Ω,
R106=33k Ω,
RL=10 Ω, RS=0.47 Ω

VCMN output Vretsat 0.1 0.2 0.4 V VCMN

saturation
voltage

23
HA13614FH

Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vpss = Vpsv = 12 V) (cont)

Applicable
Item Symbol Min Typ Max Unit Test Conditions Pins Note

Power Operating Vsd1 — 1.415 ±3% V LVI1, LVI2

monitor voltage

Hysteresis Vhys3 — 60 — mV LVI1

Vhys4 — 30 — mV LVI2

Cut off voltage Vsd2 4.1 — — V Vss

Recovery Vrec — — 4.4 V

voltage

POR delay tpor 10 14 20 ms C105=0.1µF POR

time

OP Output Rout2 — — 10 Ω Shorted between OP1OUT

amp.1 resistance OP1OUT and
OP1IN(–)

Output Iomax1 — — ±1 mA
maximum
current

Output voltage Vdev — 1.415 ±3% V

deviation

Input bias IB1 — — ±10 nA OP1IN(–)

current

Gain band BW2 — 1.0 — MHz OP1OUT

width

OTSD Operating Tsd 125 150 — °C 4

temperature

Hysteresis Thys — 25 — °C
Note: 1. Specified by sum of supply current to Vpss and Vpsv terminal.
2. Specified by sum of saturation voltage and lower saturation voltage.
3. Specified by differential voltage on both side of RS at shorting between DACOUT and OP2IN(+),
and between OP2OUT and VCMIN, respectively.
4. Guaranteed by design.
5. The 12VGOOD terminal is open drain output type.

24
 HA13614FH

Package Dimensions

Unit: mm

17.2 ± 0.2
14
36 25

0.65
37 24
17.2 ± 0.2

4.85
2.425

48 13
1 12
2.425
4.85
0.30 ± 0.08
0.27 ± 0.06 0.13 M
0.17 ± 0.05
0.15 ± 0.04

1.6
0.825 0.825
2.7

2.925 0° − 8°
2.925 2.925 2.925
0.10 ±0.07

3.05 Max

0.8 ± 0.3
0.10

Hitachi Code FP-48T

JEDEC 
Dimension including the plating thickness EIAJ 
Base material dimension Weight (reference value) 1.2 g

25
Cautions

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Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

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