The TLM-2.
0 Standard
John Aynsley, Doulos
The TLM-2.0 Standard
CONTENTS
• Review of SystemC and TLM
• Review of TLM-2.0
• Frequently Asked Questions
What is SystemC?
• System-level modeling language
• Network of communicating processes (c.f. HDL)
• Modeling hardware and software together
• New: SystemC-AMS (mixed signal)
• C++ class library Communicating
processes
• Industry standard IEEE 1666™
• Owned and driven by OSCI (Open SystemC Initiative)
• Open source implementation
• Mature, robust, easy-to-integrate and “free”
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Transaction Level Modeling
Behavioral
RTL
Model
Pin Accurate Function Call
write(address,data)
RTL Behavioral
Model
Simulate every event! 100-10,000 X faster simulation!
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Reasons for using TLM
Accelerates product release schedule
Firmware / Software development
software
Fast
TLM Architectural exploration
Ready before RTL
RTL
Hardware verification
Test bench TLM = golden model
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TLM is Communication-Oriented
Concurrent simulation environment
Transaction
+ timing
Simple functional models, e.g. C programs
Could be synthesized by an ESL synthesis tool ?
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TLM and Synthesis
ESL Synthesis ESL Synthesis Pin-level
Compare
Compare
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The TLM-2.0 Standard
CONTENTS
• Review of SystemC and TLM
• Review of TLM-2.0
• Frequently Asked Questions
OSCI TLM Timeline
Apr 2005 Jun 2008 July 2009
• TLM-1.0 • TLM-2.0
• put, get and • Pass-by-reference • TLM-2.0.1
transport
• Unified interfaces • LRM
• Request-response
model • Generic payload
• TLM-2.0 focusses on memory-mapped bus modeling
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Typical Use Case: Virtual Platform
Multiple software stacks
Software Software
CPU ROM RAM DMA DSP ROM RAM
Bridge
Interrupt Timer I/O Bridge Interrupt Timer A/D
Multiple buses and bridges
TLM-2.0
Memory Custom
I/O RAM DMA D/A
interface peripheral
Digital and analog hardware IP blocks
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Virtual Platform Characteristics
Instruction Set Transaction-Level Model RTL
Simulator or software
stubs
Available early Available early Much later
Fast enough to run Fast enough to run Too slow to run
applications applications applications
Little or no hardware Register-accurate Register-accurate and
detail
pin-accurate
No timing information Some timing information Cycle-accurate timing
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Coding Styles and Mechanisms
Use cases
Software Software Architectural Hardware
development performance analysis verification
TLM-2 Coding styles (just guidelines)
Loosely-timed
Approximately-timed
Mechanisms (definitive API for TLM-2.0 enabling interoperability)
Blocking Generic Non-blocking
DMI Quantum Sockets Phases
transport payload transport
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Interoperability Layer
1. Core interfaces and
sockets
The first function call
Initiator Target
2. Generic payload 3. Base protocol
Command
BEGIN_REQ
Address Either write bytes
Data
END_REQ
Byte enables
Streaming
BEGIN_RESP
Response status or read bytes
Extensions END_RESP
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Utilities
Interoperability
layer
Initiator Target
Coding Style
Loosely- or Approximately-timed
Core interfaces Utilities
Sockets Convenience sockets
Generic payload Quantum keeper (LT)
Payload event queues (AT)
Base protocol
Instance-specific extensions (GP)
• Productivity
• Shortened learning curve
• Consistent coding style
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The TLM-2.0 Standard
CONTENTS
• Review of SystemC and TLM
• Review of TLM-2.0
• Frequently Asked Questions
FAQ #1
"Do I want LT or AT or CA?"
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Loosely-Timed
Executing software
Initiator
The End!
Resources:
Bus
Initiator
Memory
Peripherals
Initiator
• Goal: execute software at full speed of host processor
• Target models do not consume any time, initiators run ahead
• Need the initiators to take turns
• Either have explicit synchronization points (can be untimed)
• or initiators must use a time quantum
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Loosely-Timed
Executing software
Initiator
Sync Resources:
Bus
Initiator
Memory
Peripherals
Initiator
• Goal: execute software at full speed of host processor
• Target models do not consume any time, initiators run ahead
• Need the initiators to take turns
• Either have explicit synchronization points (can be untimed)
• or initiators must use a time quantum
Copyright © 2010 by Doulos. All rights reserved. 18
Loosely-Timed
Executing software
Initiator
Resources:
Bus
Initiator
Memory
Peripherals
Initiator
Quantum
• Goal: execute software at full speed of host processor
• Target models do not consume any time, initiators run ahead
• Need the initiators to take turns
• Either have explicit synchronization points (can be untimed)
• or initiators must use a time quantum
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AT and CA
• No running ahead of simulation time; everything stays in sync
AT CA
BEGIN_REQ
END_REQ
BEGIN_RESP
END_RESP
Wake up at significant Wake up every cycle
timing points
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FAQ #2
"How do I model such-and-such a feature using TLM-2?"
"What does it take to make a model TLM-2-compliant?"
"How much of this 194-page LRM do I really need to understand?"
"How can TLM-2 make models of different protocols interoperable?"
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First Kind of Interoperability
• Use the full interoperability layer
• Use the generic payload + ignorable extensions
• Obey all the rules of the base protocol. The LRM is your rule book
tlm_initiator_socket<32, tlm_base_protocol_types> my_socket;
Initiator Interconnect Target
• Functional incompatibilities are still possible (e.g. writing to a ROM)
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Second Kind of Interoperability
• Create a new protocol traits class
• Create user-defined generic payload extensions and phases as needed
• Make your own rules!
tlm_initiator_socket<32, my_protocol> my_socket;
Initiator Adapter Target
• One rule enforced: cannot bind sockets of differing protocol types
• Recommendation: keep close to the base protocol. The LRM is your guidebook
• The clever stuff in TLM-2.0 makes the adapter fast
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FAQ #2
Q. "How do I model such-and-such a feature using TLM-2?"
A. Either make do with the generic payload, or create extensions
Q. "What does it take to make a model TLM-2-compliant?"
A. Either obey the base protocol or make your own rules
Q. "How much of this 194-page LRM do I really need to understand?"
A. For the base protocol, everything except Utilities and TLM-1
Q. "How can TLM-2 make models of different protocols interoperable?"
A. Either map onto the base protocol, or write adapters
Copyright © 2010 by Doulos. All rights reserved. 24
FAQ #3
Q. "How do I model my algorithm using TLM-2.0"
A1. Not applicable. TLM is communication-centric
A2. Use the LT/AT coding styles as guidelines
A3. Use the utilities at least as examples
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FAQ #4
Q. "How do I use extensions? It's not really explained anywhere."
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Create an Extension Class
struct my_extension: tlm::tlm_extension<my_extension>
{
my_extension() { m_attribute1 = ...; }
virtual tlm_extension_base* clone() const
{
my_extension* ext = new my_extension;
ext->m_attribute1 = this->m_attribute1;
ext->m_attribute2 = this->m_attribute2; Standard code to clone/copy
return ext;
}
virtual void copy_from( tlm_extension_base const& ext )
{
m_attribute1 = static_cast<my_extension const &>(ext).m_attribute1;
m_attribute2 = static_cast<my_extension const &>(ext).m_attribute2;
}
int m_attribute1;
Any number of attributes
string m_attribute2;
};
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Setting and Getting Extensions
Initiator Target
tlm_generic_payload* trans; virtual void b_transport( ... )
... {
my_extension* ext;
my_extension* ext = new my_extension; trans.get_extension(ext);
ext->m_attribute1 = 1; if (ext) {
ext->m_attribute2 = "foo"; ... = ext->m_attribute1;
trans->set_auto_extension( ext ); ... = ext->m_attribute2;
...
socket->b_transport( *trans, delay ); }
Have the initiator add the extension Target can test for an extension
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FAQ #5
Q. "Okay, but you've not shown me how to create ignorable extensions.
How do I do that?"
A. Being ignorable is not an explicit property of an extension,
but about how you use it
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Ignorable Extensions
An ignorable extension is able to be ignored
• Timestamp when the transaction was created
• An initiator ID or transaction ID
Extensions that might not be ignorable
• An extended address (initiator might rely on extended address space)
• A priority (initiator might rely on high priority transaction executing first)
• A flag to lock the interconnect (initiator might rely on have exclusive access)
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FAQ #6
Q. "How do I dispose of the extension object? Can I re-use it?"
A. Use a memory manager
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Using a Memory Manager
Initiator Interconnect Target
# refs
Allocate transaction object 3
2
1
0
acquire()
Call nb_transport_fw
acquire() nb_transport_fw
acquire()
Return nb_transport_fw Return
nb_transport_fw
nb_transport_bw Call nb_transport_bw Call
release()
Return nb_transport_bw release()
Return nb_transport_bw release()
free()
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Memory Management Methods
class tlm_generic_payload {
public:
tlm_generic_payload () ;
tlm_generic_payload(tlm_mm_interface* mm) ;
virtual ~tlm_generic_payload ();
void set_mm(tlm_mm_interface* mm);
bool has_mm();
void acquire();
void release();
int get_ref_count();
void deep_copy_from( const tlm_generic_payload& ) ;
void update_original_from( const tlm_generic_payload& );
void free_all_extensions();
void reset();
... Frees all auto-extensions
};
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A User-Defined Memory Manager
#include "tlm.h"
class gp_mm: public tlm::tlm_mm_interface
{
typedef tlm::tlm_generic_payload gp_t;
public:
gp_mm();
virtual ~gp_mm();
gp_t* allocate() {
...
ptr = new gp_t( this ); Pass mm as constructor arg
...
}
void free(gp_t* trans) {
Called when ref count == 0
trans->reset(); Free auto-extensions
...
}
...
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Typical Coding Idiom
my_module(sc_module_name _n, gp_mm* mm)
: m_mm(mm) {...} Pass mm as constructor arg
tlm_generic_payload* trans;
trans = m_mm.allocate(); Get transaction object from mm
trans->acquire(); Increment reference count
my_extension* ext = new my_extension; Allocate extension on heap
ext->m_attribute1 = 1;
ext->m_attribute2 = "foo";
trans->set_auto_extension( ext ); Set for auto-deletion
socket->b_transport( *trans, delay ); Not just for nb_transport
trans->release(); Decrement reference count
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FAQ #7
Q. "How do I connect multiple components together?"
Q. "How do I model a bus with multiple masters/slaves?"
Q. "How many sockets do I need for two-way communication?"
Q. "How many transactions do I use?"
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Example Topology
Control
Memory Target
manager Initiator
Data
Target
Initiator
Multi-sockets
Target
Bus
Initiator Interconnect
Target
Thread
Target
Initiator Controller
Thread Target
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Bridges
tlm_*_socket< 32, protocol_A > tlm_*_socket< 32, protocol_B >
Initiator Bridge Target
deep_copy_from()
update_original_from()
Generic Generic Generic Generic
Payload Payload Payload Payload
Extension Extension Extension Extension
Extension Extension Extension Extension
Extension Extension
Extension Extension
Could pass the same transaction if their lifetimes allow
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Copying the Data Array
• Deep-copy the data array in the bridge
new_trans->set_data_ptr( &data_buffer );
new_trans->deep_copy_from ( original_trans );
new_trans->b_transport(...);
original_trans->update_original_from( new_trans ); Copies back data array on read
• Shallow-copy the data array in the bridge
new_trans->set_data_ptr( 0 );
new_trans->deep_copy_from ( original_trans );
new_trans->set_data_ptr( original_trans->get_data_ptr() );
new_trans->b_transport(...);
original_trans->update_original_from( new_trans ); Does not touch data array
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FAQ #7
Q. "How do I connect multiple components together?"
A. By having one or more components act as a hub
Q. "How do I model a bus with multiple masters/slaves?"
A. The "hub" can do arbitration and routing. Use multi-sockets for convenience
Q. "How many sockets do I need for two-way communication?"
A. Each initiator needs an initiator socket, each target a target socket
Q. "How many transactions do I use?"
A. As few as possible
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FAQ #8
Q. "How do I model something like a SPI port?"
A. If you can abstract the functionality, use the base protocol
Q. "How do I model something like a SPI port with accurate timing?"
A. You can model precise timing with the AT coding style, but why not use RTL?
Q. "How do I model something like AMBA, PCI, or USB?"
A. Buy a model (or get one through a university/research program)
Copyright © 2010 by Doulos. All rights reserved. 41
For More FREE Information
• IEEE 1666
standards.ieee.org/getieee/1666/index.html
• OSCI SystemC 2.2 and TLM-2.0
and examples
www.systemc.org and videos
• Tutorial introduction to TLM-2.0 and Free TLM-2.0 Protocol Checker
www.doulos.com/knowhow/systemc/tlm2
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Copyright © 2010 by Doulos. All rights reserved.
