Digital

Fundamentals
Tenth Edition

Floyd

Chapter 3

© 2008 Pearson Education

 A X
The Inverter

The inverter performs the Boolean NOT operation. When the

input is LOW, the output is HIGH; when the input is HIGH,
the output is LOW.

Input Output
A X
LOW (0) HIGH (1)
HIGH (1) LOW(0)

The NOT operation (complement) is shown with an overbar.

Thus, the Boolean expression for an inverter is X = A.
 A X
The Inverter

Example waveforms:
A
X
A group of inverters can be used to form the 1’s complement
of a binary number: Binary number
1 0 0 0 1 1 0 1

0 1 1 1 0 0 1 0
1’s complement
 Specific shape Rectangular outline
symbol with polarity symbol with polarity
indicator indicator
A A
X & X
The AND Gate B
B
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

The AND operation is usually shown with a dot between the

variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.
 A A
X & X
The AND Gate B
B
Example waveforms:
A
B

X
The AND operation is used in computer programming as a
selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask with
1’s in the position of the retained bits.
If the binary number 10100011 is ANDed with
the mask 00001111, what is the result? 00000011
 Summary
The AND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count down mode. XLA1 is a logic analyzer with the
output of the AND gate connected to first (upper) line of the
analyzer. What signal do you expect to on this line?

The output (line 1) will be

HIGH only when all of the
inputs are HIGH.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 A X A ≥1 X
The OR Gate
B B
The OR gate produces a HIGH output if any input is HIGH;
if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1

The OR operation is shown with a plus sign (+) between the

variables. Thus, the OR operation is written as X = A + B.
 A X A ≥1 X
The OR Gate
B B
Example waveforms:
A
B

X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.

What will be the result if you OR an 00000001(01=Hex) with

the 8-bit 01110000 (70=Hex)?

01110001 (71 = Hex), which is equal to ASCII letter q.

 The OR Gate
A Multisim circuit is shown. XWG1 is a word generator set
to count down. XLA1 is a logic analyzer with the output
connected to first (top) line of the analyzer. The three 2-input OR gates act
as a single 4-input gate. What signal do you expect on the output line?
The output (line 1) will be
HIGH if any input is HIGH;
otherwise it will be LOW.
 A X A & X
The NAND Gate
B B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0

The NAND operation is shown with a dot between the

variables and an over bar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)
 A X A & X
The NAND Gate
B B
Example waveforms:
A
B

X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates
How would you connect a 2-input NAND gate
to form a basic inverter?
 Summary
The NAND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count up mode. A four-channel oscilloscope monitors the
inputs and output. What output signal do you expect to see?

The output (channel D) will be

LOW only when all of the
inputs are HIGH.

Inputs

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 A X A ≥1 X
The NOR Gate
B B
The NOR gate produces a LOW output if any input is
HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
The NOR operation is shown with a plus sign (+) between
the variables and an over bar covering them. Thus, the NOR
operation is written as X = A + B.
 A X A ≥1 X
The NOR Gate
B B
Example waveforms:
A
B

X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V
When the LED is ON for the circuit shown? 330 W

The LED will be on when any of A

B X
the four inputs are HIGH. C
D
 A X A =1 X
The XOR Gate
B B
The XOR gate produces a HIGH output only when both
inputs are at opposite logic levels. The truth table is
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 0

The XOR operation is written as X = AB + AB.

Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.
 A X A =1 X
The XOR Gate
B B
Example waveforms:
A
B

X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?

There is no change in the output.

 A X A =1 X
The XNOR Gate
B B
The XNOR gate produces a HIGH output only when both
inputs are at the same logic level. The truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1
The XNOR operation shown as X = AB + AB. Alternatively,
the XNOR operation can be shown with a circled dot
between the variables. Thus, it can be shown as X = A . B.
 A X A =1 X
The XNOR Gate
B B
Example waveforms:
A
B

X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?

The output will be inverted.

 Construction of NOT Gate by using NAND gate (A.B)

=A.AA

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of AND Gate by using NAND gate (A.B)

A .B A .B
 A .B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of OR Gate by using NAND gate (A.B)

A
A .B
=A+ BA+B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of NOT Gate by using NOR gate (A + B)

=A+AA

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of OR Gate by using NOR gate (A + B)

=A+BA+B
A+B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of AND Gate by using NOR gate (A + B)

A
A+B
=A.B A.B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of NAND Gate by using NOR gate (A + B)

Do it yourself

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Construction of NOR Gate by using NAND gate (A . B)

Do it yourself

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Fixed Function Logic

Two major fixed function logic families are TTL (Transistor

Transistor Logic) and CMOS (complementary metal oxide
semiconductor). A third technology is BiCMOS, which
combines the first two. Packaging for fixed function logic is
shown.
0.335 – 0.334 in.
0.740 – 0.770 in. 14 13 12 11 10 9 8

14 13 12 11 10 9 8

0.250 ± 0.010 in. 0.228 – 0.244 in.

1 2 3 4 5 6 7

1 2 3 4 5 6 7
Pin no.1 Lead no.1
identifiers identifier
14
1 14
1

DIP package SOIC package

Dual in-line package Small Outline IC

Fixed Function Logic
Some common gate configurations are shown.
VCC VCC VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'00 ' 02 '04 '08

VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'10 '11 '20 '21

VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'27 '30 '32 '86
Fixed Function Logic
Logic symbols show the gates and associated pin numbers.
VCC
(14)
(1)
(3)
(2) (1) & (3)
(4) (2)
(6) (4)
(5) (6)
(5)
(9) (9)
(8) (8)
(10) (10)
(12) (12)
(11) (13) (11)
(13)

(7)
GND
Fixed Function Logic
Data sheets include limits and conditions set by the
manufacturer as well as DC and AC characteristics. For
example, some maximum ratings for a 74HC00A are:
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V V
V in DC InputVoltage (Referenced to GND) – 0.5 to VCC +0.5 V V
V out DC Output Voltage (Referenced to GND) – 0.5 to VCC +0.5 V V
I in DC Input Current, per pin ± 20 mA
Iout DC Output Current, per pin ± 25 mA
ICC DC Supply Current, VCC and GND pins ± 50 mA
PD Power Dissipation in Still Air, Plastic or Ceramic DIP † 750 mW
SOIC Package † 500
TSSOP Package † 450
Tstg Storage Temperature –65 to + 150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds °C
Plastic DIP, SOIC, or TSSOP Package 260
Ceramic DIP 300

TSSOP (thin-shrink small outline package

 Selected Key Terms
Inverter A logic circuit that inverts or complements its
inputs.
Truth table A table showing the inputs and corresponding
output(s) of a logic circuit.
Timing A diagram of waveforms showing the proper time
diagram relationship of all of the waveforms.

Boolean The mathematics of logic circuits.

algebra
AND gate A logic gate that produces a HIGH output only
when all of its inputs are HIGH.
 Selected Key Terms
OR gate A logic gate that produces a HIGH output when
one or more inputs are HIGH.
NAND gate A logic gate that produces a LOW output only
when all of its inputs are HIGH.
NOR gate A logic gate that produces a LOW output when one
or more inputs are HIGH.

Exclusive-OR A logic gate that produces a HIGH output only

gate when its two inputs are at opposite levels.
Exclusive-NOR A logic gate that produces a LOW output only
gate when its two inputs are at opposite levels.