ET3 301 Embedded Systems Page 1
Final Test Example
1. (10 p) Build a 2x2 AND-OR-INVERT gate using a minimum number of CMOS transistors.
Use this structure to compute x ⊕ y. You may assume that the signals x and y are available in
both direct and inverted form.
2. (10 p) The 4-bit Johnson counter advances through the sequence 0000, 1000, 1100, 1110,
1111, 0111, 0011, 0001, 0000, … Design such a counter. Use the sequential design
technique described in Chapter 2. Start from a state diagram, draw the state table, and
minimize the logic. Do not draw the circuit! Logic equations resulting from minimization are
enough to describe the logic.
3. (10 p) Design a single-purpose processor that outputs Fibonacci numbers up to n places. The
processor has the following interface:
a. go_i – start signal, when 1 the processors should start generating the numbers;
b. n_i - the number of places to be generated;
c. fib_o - gives the value of the current Fibonacci number.
Start with a function computing the desired result, translate it into a state diagram, and sketch
a probable controller and datapath.
4. (5 p) Detail the stages of executing the MOV instructions in Figure 3.7, assuming an 8-bit
processor and a 16-bit IR and program memory following the model in Figure 3.1. For
example, the stages for the ADD instruction are (1) fetch M[PC] into IR, (2) read Rn and Rm
from register file through ALU configured for ADD, storing results back in Rn.
5. (5 p) Add one instruction to the instruction set in Figure 3.7 that would reduce the size of the
summing assembly program in Figure 3.8 (b) by 1 instruction. Write down the reduced
program.
6. (5 p) Write a C function (pseudocode is OK too) that initializes the LCD described in Figure
4.7. After initialization, the display should be clear with a blinking cursor. The initialization
should set the following data to shift to the left, have a data length of 8-bits and a font of
5×10 dots, and be displayed on one line.
7. (5 p) Determine the values for smod and TH1 to generate a baud rate of 9,600 for the 8051
baud rate equation in Chapter 4, assuming an 11.981 MHz oscillator. Remember that smod is
2 bits and TH1 is 8 bits.
8. (5 p) Given an analog input signal whose voltage ranges from –5 to 5 V, and an 8-bit digital
encoding, calculate the correct encoding of 1.2 V, and then trace the successive
approximation approach to find the correct encoding.
9. (10 p) Design the logic required for building a 16 M × 8-bit PROM memory module out of 1
M × 32-bit PROM chip memories. You have to propose a design that allows the utilization of
the entire capacity of the PROM chips in the module. No memory location can be wasted!
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10. (10 p) Draw a block diagram of a processor, memory, peripheral, and DMA controller
connected with a system bus, in which the peripheral transfers 100 bytes of data to the
memory using DMA. Show all relevant control and data lines of the bus, and label
component inputs/outputs clearly. Draw a timing diagram showing what happens during the
transfer; skip the 2nd through 99th bytes.
11. (5 p) Show the correspondence of the three types of cores with Gajski’s Y-Chart.
12. (10 p) Assume the following Huffman code:
Character Code
A 1
B 01
C 0000
D 0001
E 0010
F 0011
Write the C-code for the associated decoder.
Assumptions:
• A pointer to the to be decoded bitstream in the memory is available:
int *bitstream;
• In order to decrease the number of memory accesses, utilize a buffer to store
4 bytes of the bitstream at a time: unsigned int decode_buffer;.
• An infinite bitstream, therefore no tests are required to detect the end of the
bitstream.
13. (10p) Consider the following multiple bus platform:
Arbiter Device 1
BUS1
CPU1 CPU2
Bridge Device 3 Device 4
Device 2
BUS3
BUS2 CPU3
Assume that during the execution of a program on “CPU 2” some “Device 4” data are required.
To get this data, the program issues a “Device 4” read data request. Consequently, a number of
transactions will take place on the system busses. Assuming that all buses are ISA alike parallel
buses provide a timing diagram illustrating how this read data request is solved. It must be clear
what actions are taken, which signals are asserted, etc.
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Question 3
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Question 4
Question 5
Question 6
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Question 7
Question 8
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Question 10
Question 11
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Question 12
int *bitstream;
unsigned int decode_buffer;
int counter = 0;
int get_one_bit() {
int first_bit = decode_buffer & 0x80000000;
decode_buffer <<= 1;
counter++;
if (counter > 31) {
decode_buffer = bitstream++;
counter = 0;
}
return first_bit;
}
char Huffman_decode() {
if (get_one_bit())
return ‘A’; // 1
else
if (get_one_bit())
return ‘B’; // 01
else
if (get_one_bit())
if (get_one_bit())
return ‘F’; // 0011
else
return ‘E’; // 0010
else
if (get_one_bit())
return ‘D’; // 0001
else
return ‘C’; // 0000
}
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