OPA602

OPA
602

OPA
602

SBOS155A – AUGUST 1987 – REVISED OCTOBER 2002

High-Speed Precision
Difet ® OPERATIONAL AMPLIFIER

FEATURES APPLICATIONS
● WIDE BANDWIDTH: 6.5MHz ● PRECISION INSTRUMENTATION
● HIGH SLEW RATE: 35V/µs ● OPTOELECTRONICS
● LOW OFFSET: ±250µV max ● SONAR, ULTRASOUND
● LOW BIAS CURRENT: ±1pA max ● PROFESSIONAL AUDIO EQUIPMENT
● FAST SETTLING TIME: 1µs to 0.01% ● MEDICAL EQUIPMENT
● UNITY-GAIN STABLE ● DATA CONVERSION

DESCRIPTION +VS
The OPA602 is a precision, wide bandwidth FET operational (7)
amplifier. Monolithic Difet (dielectrically isolated FET) con-
struction provides an unusual combination of high-speed and
accuracy. –In
(2)
Its wide-bandwidth design minimizes dynamic errors. High
slew rate and fast settling time allow accurate signal process-
ing in pulse and data conversion applications. Wide band- +In
Cascode
width and low distortion minimize AC errors. All specifications (3)
are rated with a 1kΩ resistor in parallel with 500pF load. The
OPA602 is unity-gain stable and easily drives capacitive
Output
loads up to 1500pF. (6)
Laser-trimmed input circuitry provides offset voltage and drift
performance normally associated with precision bipolar op
amps. Difet construction achieves extremely low input bias
currents (1pA max) without compromising input voltage noise.
The OPA602’s unique input cascode circuitry maintains low
input bias current and precise input characteristics over its
–VS
full input common-mode voltage range.
(4)
Difet® Burr-Brown Corp. (1) (5)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 1987, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Supply Voltage ............................................................................... ±18VDC
Internal Power Dissipation (TJ ≤ +175°C) .................................... 1000mW DISCHARGE SENSITIVITY
Differential Input Voltage .............................................................. Total VS
Input Voltage Range ............................................................................ ±VS This integrated circuit can be damaged by ESD. Texas Instru-
Storage Temperature Range ments recommends that all integrated circuits be handled with
P and U Packages ....................................................... –40°C to +125°C
appropriate precautions. Failure to observe proper handling
Operating Temperature Range
P and U Packages ........................................................ –25°C to + 85°C and installation procedures can cause damage.
Lead Temperature
ESD damage can range from subtle performance degrada-
U Package, SO (3s) .................................................................... +260°C
Output Short-Circuit to Ground (+25°C) ................................... Continuous tion to complete device failure. Precision integrated circuits
Junction Temperature .................................................................... +175°C may be more susceptible to damage because very small
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” parametric changes could cause the device not to meet its
may cause permanent damage to the device. Exposure to absolute maximum published specifications.
conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION
OFFSET SPECIFIED
VOLTAGE MAX PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT (µV) AT 25°C PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
OPA602AP ±2000 DIP-8 P –25°C to +85°C 602AP 602AP Tubes, 50
OPA602BP ±1000 " " " 602BP 602BP Tubes, 50
OPA602AU ±3000 SO-8 D –25°C to +85°C 602AU 602AU Tubes, 100

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PIN CONFIGURATIONS
Top View DIP, SO

Offset Trim 1 8 NC
Offset Trim 1 8 NC

–In 2 7 +VS –In 2 7 +VS

+In 3 6 Output
+In 3 6 Output
–VS 4 5 Offset Trim
–VS 4 5 Offset Trim
SO-8
DIP-8
NC = No Connection

2
OPA602
www.ti.com SBOS155A
ELECTRICAL CHARACTERISTICS
At VS = ±15VDC and TA = +25°C, unless otherwise noted.
OPA602BP OPA602AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT NOISE
Voltage:
fO = 10Hz 23 ✻ nV/ √Hz
fO = 100Hz 19 ✻ nV/ √Hz
fO = 1kHz 13 ✻ nV/ √Hz
fO = 10kHz 12 ✻ nV/ √Hz
fB = 10Hz to 10kHz 1.4 ✻ µVrms
fB = 0.1Hz to 10Hz 0.95 ✻ µVp-p
Current:
fB = 0.1Hz to 10Hz 12 ✻ fAp-p
fO = 0.1Hz to 20kHz 0.6 ✻ fA/ √Hz
OFFSET VOLTAGE
Input Offset Voltage:
P Package 0.5 1 1 2 mV
U Package 1 3 mV
Over Specified Temperature
P, U Packages ±0.75 ±1.5 ±1.5 mV
Average Drift(1) TA = TMIN to TMAX ±3 ±5 ✻ ±15 µV/°C
Supply Rejection ±VS = 12V to 18V 80 100 70 ✻ dB
BIAS CURRENT
Input Bias Current VCM = 0VDC ±1 ±2 ±2 ±10 pA
Over Specified Temperature ±20 ±200 ±20 ±500 pA
OFFSET CURRENT
Input Offset Current VCM = 0VDC 0.5 2 1 10 pA
Over Specified Temperature 20 200 20 500 pA
INPUT IMPEDANCE
Differential 1013 || 1 ✻ Ω || pF
Common-Mode 1014 || 3 ✻ Ω || pF
INPUT VOLTAGE RANGE
Common-Mode Input Range ±10.2 +13, –11 ✻ ✻ V
Common-Mode Rejection VIN = ±10VDC 88 100 75 ✻ dB
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain RL ≥ 1kΩ 88 100 75 ✻ dB
FREQUENCY RESPONSE
Gain Bandwidth Gain = 100 4 6.5 3.5 ✻ MHz
Full-Power Response 20Vp-p, RL = 1kΩ 570 ✻ kHz
Slew Rate VO = ±10V, RL = 1kΩ 24 35 20 ✻ V/µs
Settling Time:
0.1% Gain = –1, RL = 1kΩ 0.6 ✻ µs
0.01% CL = 500pF, 10V Step 1.0 µs
RATED OUTPUT
Voltage Output RL = 1kΩ ±11.5 +12.9, ±11 ✻ V
–13.8
Current Output VO = ±10VDC ±15 ±20 ✻ ✻ mA
Output Resistance 1MHz, Open Loop 80 ✻ Ω
Load Capacitance Stability Gain = +1 1500 ✻ pF
Short-Circuit Current ±30 ±50 ±25 ✻ mA
POWER SUPPLY
Rated Voltage ±15 ✻ VDC
Voltage Range, Derated Performance ±5 ±18 ✻ ✻ VDC
Current, Quiescent IO = 0mADC 3 4 ✻ ✻ mA
Over Specified Temperature 3.5 4.5 ✻ ✻ mA
TEMPERATURE RANGE
Specification Ambient Temperature –25 +85 ✻ ✻ °C
Operating:
P, U Packages –25 +85 ✻ ✻ °C
Storage:
P, U Packages –40 +125 ✻ ✻ °C
θJA 200 ✻ °C/W

✻ Same specifications as OPA602BP.

NOTE: (1) OPA602AP, AU ensured by design with a 99% confidence level.

OPA602 3
SBOS155A www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C and VS = ±15VDC, unless otherwise noted.

INPUT CURRENT NOISE SPECTRAL DENSITY INPUT VOLTAGE NOISE SPECTRAL DENSITY
100 1k

Voltage Noise (nV/√Hz)

Current Noise (fA/√Hz)

10 100

1 10

0.1 1
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

POWER-SUPPLY REJECTION AND COMMON-MODE TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
REJECTION vs TEMPERATURE AT 1kHz vs SOURCE RESISTANCE
110 1k

EO
Voltage Noise, EO (nV/√Hz)

105
CMR and PSR (dB)

RS
100

CMR
100 OPA602 + Resistor

PSR
10
95

Resistor Noise Only

90 1
–75 –50 –25 0 25 50 75 100 125 100 1k 10k 100k 1M 10M 100M
Temperature (°C) Source Resistance (Ω)

COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE OPEN-LOOP FREQUENCY RESPONSE
120 140
RL = 1kΩ
120 –45
CL = 100pF
Common-Mode Rejection (dB)

110
Phase Shift (degrees)

100
Voltage Gain (dB)

100 80 –90
φ
60
90
40 –135
AOL
80
20

70 0 –180
–15 –10 –5 0 +5 +10 +15 1 10 100 1k 10k 100k 1M 10M
Common-Mode Voltage (V) Frequency (Hz)

4
OPA602
www.ti.com SBOS155A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C and VS = ±15VDC, unless otherwise noted.

GAIN BANDWIDTH AND SLEW RATE GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE vs SUPPLY VOLTAGE
10 37 8 38
AV = –1

8 35
Gain Bandwidth (MHz)

Gain Bandwidth (MHz)

GBW

Slew Rate (V/µs)

7 36

Slew Rate (V/µs)

GBW
6 33

Slew Rate
6 34
4 31

Slew Rate
2 29 5 32
–75 –50 –25 0 25 50 75 100 125 0 5 10 15 20
Ambient Temperature (°C) Supply Voltage (±VCC)

MAXIMUM OUTPUT VOLTAGE SWING

OPEN-LOOP GAIN vs TEMPERATURE vs FREQUENCY
120 30

110 Output Voltage (Vp-p)

Voltage Gain (dB)

20

100

10
90

RL = 1kΩ
80 0
–75 –50 –25 0 25 50 75 100 125 10k 100k 1M 10M
Ambient Temperature (°C) Frequency (Hz)

LARGE-SIGNAL TRANSIENT RESPONSE SMALL-SIGNAL TRANSIENT RESPONSE

150

10 100
Output Voltage (mV)
Output Voltage (V)

50

0 0

–50

–10 –100

–150

0 1 2 3 4 5 0 2 5
Time (µs) Time (µs)

OPA602 5
SBOS155A www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C and VS = ±15VDC, unless otherwise noted.

SETTLING TIME vs CLOSED-LOOP GAIN SUPPLY CURRENT vs TEMPERATURE

5 3.5

4
3.25

Supply Current (mA)

Settling Time (µs)

3
3.0
0.01% 0.1%
2

2.75
1
RL = 1kΩ
CL = 100pF
0 2.5
–1 –10 –100 –1k –75 –50 –25 0 25 50 75 100 125
Closed-Loop Gain (V/V) Ambient Temperature (°C)

TOTAL HARMONIC DISTORTION

OPEN-LOOP GAIN vs SUPPLY VOLTAGE vs FREQUENCY
104 1
40.2kΩ
402Ω
6.5Vrms
THD + Noise (%rms)

100 0.1 1kΩ

Voltage Gain

AV = +101V/V

AV = +101V/V
96 0.01

AV = +1V/V

92 0.001
0 5 10 15 20 0.1 1 10 100 1k 10k 100k
Supply Voltage (±VCC) Frequency (Hz)

BIAS AND OFFSET CURRENT

BIAS AND OFFSET CURRENT vs TEMPERATURE vs INPUT COMMON MODE VOLTAGE
10nA 10nA 10 10

1nA 1nA
Offset Current (pA)
Offset Current (pA)

Bias Current
Bias Current (pA)
Bias Current (pA)

1 1
100 100

Offset Current
10 10
0.1 0.1

1 1

0.1 0.1 0.01 0.01

–50 –25 0 25 50 75 100 125 –15 –10 –5 0 5 10 15
Ambient Temperature (°C) Common-Mode Voltage (V)

6
OPA602
www.ti.com SBOS155A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C and VS = ±15VDC, unless otherwise noted.

POWER-SUPPLY REJECTION vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY

140 140

120 120

Common-Mode Rejection (dB)

Power-Supply Rejection (dB)

100 100

80 80
– +
60 60

40 40

20 20

0 0
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

INPUT BIAS CURRENT GUARDING

APPLICATIONS INFORMATION
Leakage currents across printed circuit boards can easily
Unity-gain stability with good phase margin and excellent
exceed the input bias current of the OPA602. A circuit board
output drive characteristics bring freedom from the subtle
“guard” pattern, as shown in Figure 1, is an effective solution
problems associated with other high-speed amplifiers. How-
to difficult leakage problems. This guard pattern must be
ever, as with any high-speed, wide bandwidth circuitry, care-
repeated on all layers of a multilayer board. By surrounding
ful circuit layout will ensure best performance. Make short,
critical high impedance input circuitry with a low impedance
direct interconnections and avoid stray wiring capacitance—
circuit connection at the same potential, leakage currents will
especially at the inverting input pin.
flow harmlessly to the low-impedance node.
Power supplies should be bypassed with good high-frequency
Input bias current may also be degraded by improper han-
capacitors positioned close to the op amp pins. In most cases
dling or cleaning. Contamination from handling parts and
0.1µF ceramic capacitors are adequate. Applications with
circuit boards may be cleaned with appropriate solvents and
heavier loads and fast transient waveforms may benefit from
deionized water. Each rinsing operation should be followed
use of additional 1.0µF tantalum bypass capacitors.
by a 30-minute bake at +85°C.

Noninverting
Buffer

2 2
6 6
OPA602 Out OPA602 Out
In 3 In 3

Inverting
In

2
6
Board Layout for Input Guarding: OPA602 Out
3
Guard top and bottom of board.
Alternate—use Teflon® standoff for sensitive input pins.

Teflon® E.I. Du Pont de Nemours & Co.

FIGURE 1. Connection of Input Guard.

OPA602 7
SBOS155A www.ti.com
APPLICATION CIRCUITS
MSB
B1 • • • • • • • • • • B12

4 5 6 7 8 9 10 11 12 13 14 15
16 18 C1 15pF
+15V RF
+VS 1
DAC7541A Out 1 VOUT
17
7 VREFERENCE Out 2 OPA602
2
2 3
6
OPA602 100kΩ
3 1
±10mV Typical
5 Single-Point Ground
Trim Range
4
(1)
–VCC

B B B B 
–VS V OUT = − VREF  1 + 2 + 3 + L + 12 
 2 4 8 4096 
−10V ≤ VREF ≤ +10V
4095
0 ≤ V OUT ≤ − VREF
NOTE: (1) 10kΩ to 1MΩ trim potentiometer (100kΩ recommended). 4096
Where: BN = 1 if the BN digital input is high.
BN = 0 if the BN digital input is low.

FIGURE 2. Offset Voltage Trim. FIGURE 3. Voltage Output Digital-to-Analog Converter.

(2)
HP 5082-2835

2kΩ 2kΩ 50Ω

+15V
47pF
1µF
High-Quality
Pulse Generator 2kΩ +

510Ω
+15V 1µF
Pulse In 1µF Tantalum
±5V 2kΩ +
+
1/2 2N5564
OPA602 Output
51Ω 1µF Tantalum Error Out
±0.5mV
+ (0.01%)
CL
500pF
–15V

1/2 2N5564
1µF
+

510Ω
1µF
+

–15V

FIGURE 4. Settling Time and Slew Rate Test Circuit.

8
OPA602
www.ti.com SBOS155A
PACKAGE DRAWINGS

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)
0.355 (9,02)
8 5

0.260 (6,60)
0.240 (6,10)

1 4
0.070 (1,78) MAX

0.325 (8,26)
0.020 (0,51) MIN
0.300 (7,62)

0.015 (0,38)

Gage Plane
0.200 (5,08) MAX
Seating Plane

0.125 (3,18) MIN 0.010 (0,25) NOM

0.100 (2,54) 0.430 (10,92)

MAX
0.021 (0,53)
0.010 (0,25) M
0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001

OPA602 9
SBOS155A www.ti.com
PACKAGE DRAWINGS (Cont)

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
8 5

0.244 (6,20) 0.008 (0,20) NOM

0.228 (5,80)
0.157 (4,00)
0.150 (3,81)

Gage Plane

1 4 0.010 (0,25)

A 0°– 8°
0.044 (1,12)
0.016 (0,40)

Seating Plane

0.010 (0,25)
0.069 (1,75) MAX 0.004 (0,10)
0.004 (0,10)

PINS **
8 14 16
DIM

0.197 0.344 0.394

A MAX
(5,00) (8,75) (10,00)
0.189 0.337 0.386
A MIN
(4,80) (8,55) (9,80)

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

10
OPA602
www.ti.com SBOS155A
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Oct-2009

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
OPA602AM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA602AM2 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA602AP ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA602APG4 ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA602AU ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA602AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA602AU/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA602AUE4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA602AUG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA602BM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA602BM1 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA602BP ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA602BPG4 ACTIVE PDIP P 8 50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA602CM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
OPA602SM OBSOLETE TO-99 LMC 8 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Oct-2009

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
OPA602AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA602AU/2K5 SOIC D 8 2500 346.0 346.0 29.0

Pack Materials-Page 2
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