Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-1

LECTURE 23 – DESIGN OF TWO-STAGE OP AMPS

LECTURE OUTLINE
Outline
• Steps in Designing an Op Amp
• Design Procedure for a Two-Stage Op Amp
• Design Example of a Two-Stage Op Amp
• Right Half Plane Zero
• PSRR of the Two-Stage Op Amp
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 286-309

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-2

STEPS IN DESIGNING A CMOS OP AMP

Design Inputs
Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain 8. Output-voltage swing
2. Gain bandwidth 9. Output resistance
3. Settling time 10. Offset
4. Slew rate 11. Noise
5. Common-mode input range, ICMR 12. Layout area
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-3

Outputs of Op Amp Electrical Design

The basic outputs are:
1.) The topology
2.) The dc currents
3.) The W and L values of transistors
4.) The values of components
Op amp circuit VDD

or systems M3 M4 Cc
M6

Topology
specifications
vout

-
vin
M1 M2 CL L
+
+ M7
VBias
-
M5 W
VSS
DC Currents
Design of 50µA

CMOS
Op Amps
W/L ratios

Component C R
values
060625-06

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-4

Some Practical Thoughts on Op Amp Design

1.) Decide upon a suitable topology.
• Experience is a great help
• The topology should be the one capable of meeting most of the specifications
• Try to avoid “inventing” a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.
• Consider the load and stability requirements
• Use some form of Miller compensation or a self-compensated approach
3.) Design dc currents and device sizes for proper dc, ac, and transient performance.
• This begins with hand calculations based upon approximate design equations.
• Compensation components are also sized in this step of the procedure.
• After each device is sized by hand, a circuit simulator is used to fine tune the
design
Two basic steps of design:
1.) “First-cut” - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this
step.
2.) Optimization - this step uses the computer to refine and optimize the design.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-5

A DESIGN PROCEDURE FOR THE TWO-STAGE CMOS OP AMP

Unbuffered, Two-Stage CMOS Op Amp
VDD

M6
M3 M4 Cc
vout

- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig. 6.3-1
Notation:
Wi
Si = L = W/L of the ith transistor
i

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-6

DC Balance Conditions for the Two-Stage Op Amp

For best performance, keep all transistors in VDD
VSG4 + VSG6 +
saturation. - -
M6
M4 is the only transistor that cannot be forced into M3 M4 I4 Cc I6
vout
saturation by internal connections or external voltages.
- M1 M2 CL
Therefore, we develop conditions to force M4 to be in vin I7
saturation. +
I5
M7
1.) First assume that VSG4 = VSG6. This will cause +
VBias M5
“proper mirroring” in the M3-M4 mirror. Also, the -
VSS
Fig. 6.3-1A
gate and drain of M4 are at the same potential so that
M4 is “guaranteed” to be in saturation.
S6
2.) If VSG4 = VSG6, then I6 = S I4
 4
S7 S7
3.) However, I7 = S I5 = S  (2I4)
 5  5
S6 2S7
4.) For balance, I6 must equal I7  called the “balance conditions”
S4 = S5
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-7

Summary of the Design Relationships for the Two-Stage Op Amp

I5
Slew rate SR = C (Assuming I7 >>I5 and CL > Cc)
c
gm1 2gm1
First-stage gain Av1 = g + g = I (l + l )
ds2 ds4 5 2 4
gm6 gm6
Second-stage gain Av2 = g + g = I (l + l )
ds6 ds7 6 6 7
gm1
Gain-bandwidth GB = C
c
-gm6
Output pole p2 = C
L
gm6
RHP zero z1 = C
c
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are  10GB.
I5
Positive ICMR Vin(max) = VDD - b3 - VT03(max) + VT1(min))
I5
Negative ICMR Vin(min) = VSS + b1 + VT1(max) + VDS5(sat)
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-8

Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, Av(0)
2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, CL
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, Pdiss

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-9

Unbuffered Op Amp Design Procedure

This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input
common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),
settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation
(Pdiss) are given. Choose the smallest device length which will keep the channel
modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase
margin we use the following relationship. This assumes that z  10GB.
Cc  0.22CL
2. Determine the minimum value for the “tail current” (I5) from
I5 = SR .Cc
3. Design for S3 from the maximum input voltage specification.
I5
S3 = K' [V − V (max) − V (max) + V (min)]2
3 DD in T03 T1
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant
by assuming it to be greater than 10 GB
gm3
2Cgs3 > 10GB.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-10

Unbuffered Op Amp Design Procedure - Continued

5. Design for S1 (S2) to achieve the desired GB.
gm12
gm1 = GB . Cc → S2 = K' I
1 5
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
I5 2I5
VDS5(sat) = Vin(min) - VSS- -V (max) ≥ 100 mV → S5 =
1 T1 K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that
VSG4 = VSG6.
gm6 2KP'S6I6 S6I6 S6 gm6
gm6 = 2.2gm2(CL/Cc) and →
gm4 = = S4I4 = S4 S6 = g S4
2KP'S4I4 m4
8. Calculate I6 from
gm62
I6 =
2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-11

Unbuffered Op Amp Design Procedure - Continued

10. Check gain and power dissipation specifications.
2gm2gm6
Av = I ( +  )I ( +  ) Pdiss = (I5 + I6)(VDD + VSS)
5 2 4 6 6 7
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased or
the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked
to insure that they are satisfied. If the power dissipation is too high, then one can only
reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of
some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-12

Unbuffered Op Amp Design Summary

Step Design Equations Comments

1 Let Cc ≥ 0.2CL PM = 60° and RHP Z=10GB
2 Let I5 ≥ SR·CcCCL Assumes SR limited by Cc 0° and RB
W3 W4 I5
3 = = ' Maximum input common mode range
L3 L4 K3 [VDD -Vin (max)- | VT 3 | +VT1 ] 2
W1 W2 gm1
2

4 gm1 = GB ×Cc ® = = GB defines the W/L of M1 and M2

L1 L2 K1'I 5
W5 2I 5
5 = ' Minimum input common mode range
L5 K 5VDS 5 (sat)2
W6 gm6 W4
6 = DC balance conditions
L6 gm 4 L4
gm6
2

7 I6 = PM = 60° and p2 = 2.2GB give gm6 ≈ 10gm1

2K 6' (W6 / L6 )
W7 é I 6 W5 2I 7 ù
8 = max ê , ' 2ú Determines the current in M7
L7 ë I 5 L5 K 7VDS 7 (sat) û
Check gain and power
2gm1gm6
9 dissipation and iterate Av = and Pdiss = (I 5 + I 6 )(VDD + | VSS |)
if necessary I 5 (l2 + l4 )I 6 (l6 + l7 )

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-13

DESIGN EXAMPLE OF A TWO-STAGE OP AMP

Example 23-1 - Design of a Two-Stage Op Amp
If KN’=120µA/V2, KP’= 25µA/V2, VTN = |VTP| = 0.5±0.15V, N = 0.06V-1, and P =
0.08V-1, design a two-stage, CMOS op amp that meets the following specifications.
Assume the channel length is to be 0.5µm and the load capacitor is CL = 10pF.
Av > 3000V/V VDD =2.5V GB = 5MHz SR > 10V/µs
60° phase margin 0.5V<Vout range < 2V ICMR = 1.25V to 2V Pdiss  2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc  (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 µA
3.) Next calculate (W/L)3 using ICMR requirements (use worst case thresholds ±0.15V).
30x10-6
(W/L)3 = = 30 → (W/L)3 = (W/L)4 = 30
(25x10-6)[2.5 - 2 - .65 + 0.35]2

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-14

Example 23-1 - Continued

4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact
greater than 10GB. Assume the Cox = 6fF/µm2. The mirror pole can be found as
-gm3 - 2K’pS3I3
p3 ≈ 2C = 2(0.667)W L C = -1.25x109(rads/sec)
gs3 3 3 ox
or 199 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
gm12 (94.25)2
(W/L)1 = (W/L)2 = 2K’ I = 2·120·15 = 2.47  3.0  (W/L)1 = (W/L)2 = 3
N 1
6.) Next calculate VDS5,
30x10-6
VDS5 = 1.25 - - .65 = 0.31V
120x10-6·3
Using VDS5 calculate (W/L)5 from the saturation relationship.
2(30x10-6)
(W/L)5 = (120x10-6)(0.31)2 = 5.16  6 → (W/L)5 = 6

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-15

Example 23-1 - Continued

7.) For 60° phase margin, we know that
gm6  10gm1  942.5µS
Assuming that gm6 = 942.5µS and knowing that gm4 = 150µS, we calculate (W/L)6 as
942.5x10-6
(W/L)6 = 30 = 188.5  190 (W/L)6 = 190
(150x10-6)
8.) Calculate I6 using the small-signal gm expression:
(942.5x10-6)2
I6 = (2)(25x10-6)(188.5) = 94.2µA  95µA
Calculating (W/L)6 based on Vout(max), gives a value of 15. Since 190 exceeds the
specification and gives better phase margin, we choose (W/L)6 = 190 and I6 = 95µA.
With I6 = 95µA the power dissipation is Pdiss = 2.5V·(30µA+95µA) = 0.3125mW
9.) Finally, calculate (W/L)7
95x10-6
(W/L)7 = 6 30x10-6 = 19  20 → (W/L)7 = 20
 
Let us check the Vout(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of Vout(min) is
Vout(min) = VDS7(sat) = (2·95)/(120·20) = 0.281V
which is less than required. At this point, the first-cut design is complete.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-16

Example 23-1 - Continued

10.) Now check to see that the gain specification has been met
(94.25x10-6)(942.5x10-6)
Av = 15x10-6(.06 + .08)95x10-6(.06 + .08) = 3,180V/V
which barely exceeds the specifications. Since we are at 2xLmin, it won’t do any good to
increase the channel lengths. Decreasing the currents or increasing W6/L6 will help.
The figure below shows the results of the first-cut design. The W/L ratios shown do
not account for the lateral diffusion discussed above. The next phase requires simulation.

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-17

RIGHT-HALF PLANE ZERO

Controlling the Right-Half Plane Zero
Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for
stability.
jw
jw3 Loop
Gain RHP Zero Boost

jw2 0dB log10w

180 > q1 > q2 > q3
180°
q3 Loop
jw1 q2
q1 Phase
s Shift
z1 0° log10w
150129-013 RHP Zero Lag

Solution of the problem:

The compensation comes from the feedback path through Cc, but the RHP zero
comes from the feedforward path through Cc so eliminate the feedforward path!

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-18

Elimination of the Feedforward Path through the Miller Capacitor

Feedback Only
1.) Removing the feedforward path.
Cc
Roots: Dominant pole and output pole. +1

Inverting vOUT
High-Gain
Stage
120523-01

2.) Controlling the RHP zero location using a Rz Cc

nulling resistor†.
Roots: Inverting vOUT
High-Gain
a.) Dominant pole (Miller pole) Stage
120523-02

b.) Output pole

-1
c.) Pole due to Rz and first stage output capacitance, p4 ≈ R C
z I
1
d.) Controllable zero, z1 = C (1/g - R )
c mII z
Note that z1 can be placed anywhere on the real axis.

† W.J. Parrish, “An Ion Implanted CMOS Amplifier for High Performance Active Filters”, Ph.D. Dissertation, 1976, Univ. of CA, Santa Barbara.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-19

A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1 -gmII
Cc(1/gmII - Rz) = CII
The value of Rz can be found as
Cc + CII
Rz =  C  (1/gmII)
 c 
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain
stability, all that is required is that
Av(0) gmI
p4  Av(0)p1 = g R R C = C and (1/RzCI)  (gmI/Cc) = GB
mII II I c c
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc  gmII CICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-20

Using the Nulling Resistor in the Miller Compensated Two-Stage Op Amp

VDD
Circuit:
M11 M3 M4 V
B
VA M6
M10 CM Cc vout
M8
VC vin- vin+
M1 M2
CL
IBias

M9 M5
M12 M7

VSS Fig. 160-03

We saw earlier that the roots were:
gm2 gm1 gm6
p1 = - A C = - A C p2 = - C
v c v c L
1 -1
p4 = - z1 =
RzCI RzCc - Cc/gm6
where Av = gm1gm6RIRII.
(Note that p4 is the pole resulting from the nulling resistor compensation technique.)
Design of the Nulling Resistor (M8)
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-21

For the zero to be on top of the second pole (p2), the following relationship must hold
1 CL + Cc Cc+CL  1
Rz = g  C  =  C 
m6  c   c  2K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active region
because the dc current through it is zero. Therefore, Rz, can be written as
vDS8 1
Rz =  =
iD8 V =0 K’PS8(VSG8-|VTP|)
DS8
The bias circuit is designed so that voltage VA is equal to VB.
W11 I10 W6
 VGS10 − VT = VGS8 − VT  VSG11 = VSG6   =  
 L11   I6   L6 
In the saturation region
2(I10)
VGS10 − VT =
K'P(W10/L10) = VGS8 − VT
1 K’PS10 1 S10
 Rz =
K’PS8 2I10 = S8 2K’PI10
W8  Cc  S10S6I6
Equating the two expressions for Rz gives   =  
 L8  CL + Cc I10

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-22

Example 23-2 - RHP Zero Compensation

Use results of Ex. 23-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p2. Use device
data given in Ex. 23-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current
I10. The first step in this design is to establish the bias components. In order to set VA
equal to VB, then VSG11 must equal VSG6. Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 15µA which gives S11 = (15µA/95µA)190 = 30.
VDD
The aspect ratio of M10 is essentially a free parameter,
and will be set equal to 1. There must be sufficient supply M11 M4
VB
VA M6
voltage to support the sum of VSG11, VSG10, and VDS9. The M10 M8
Cc

ratio of I10/I5 determines the (W/L) of M9. This ratio is VC

I9

(W/L)9 = (I10/I5)(W/L)5 = (15/30)(6) = 3 IBias I5

Now (W/L)8 is determined to be M12

M9 M5


3pF  1·190·95µA 100327-03
 VSS
(W/L)8 = 3pF+10pF
 =8
  15µA
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-23

Example 23-2 - Continued

It is worthwhile to check that the RHP zero has been moved on top of p2. To do this, first
calculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
2I10 2·15
VSG10 = + |V | =
K’PS10 TP 25·1 + 0.5 = 1.595V
Next determine Rz.
1 106
Rz = = = 4.564k
K’PS8(VSG10-|VTP|) 25·8(1.595-.7)
The location of z1 is calculated as
-1
z1 = -12 = -94.91x106 rads/sec
3x10
(4.564 x 103)(3x10-12) -
950x10-6
The output pole, p2, is
950x10-6
p2 = - = -95x106 rads/sec
10x10-12
Thus, we see that for all practical purposes, the output pole is canceled by the zero
that has been moved from the RHP to the LHP.
The results of this design are summarized below where L = 0.5µm.
W8 = 4µm W9 = 1.5µm W10 = 0.5µm and W11 = 15 µm
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-24

An Alternate Form of Nulling Resistor

To cancel p2, VDD
Cc+CL 1
z1 = p2 → Rz = g C = g M11 M10
m6A C m6B M3 M4
Which gives M6
vout
 Cc  - M1 M2 M6B
gm6B = gm6AC +C  vin Cc CL
 c L
+
In the previous example, + M8 M9
M7
VBias M5
gm6A = 950µS, Cc = 3pF -
VSS Fig. 6.3-4A
and CL = 10pF.
Choose I6B = 10µA to get
gm6ACc 2KPW6BI6B  Cc  2KPW6AID6
gm6B = → = 
Cc + CL L6B  Cc+CL L6A
or
W6B  3 2 I6A W6A  3 2 95
= = (190) = 96.12 → W6B = 48µm
L6B 13 I6B L6A 13 10

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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-25

Increasing the Magnitude of the Output Pole†

The magnitude of the output pole, VDD VDD
M11 M12 M11 M12
p2, can be increased by introducing Cc
M7
Cc
M7
vOUT vOUT
gain in the Miller capacitor feedback
A
path as shown where, M8 VBias
A ≈ gm8(rds8||rds9||rds2||rds4). M6 M6

M10 M9 M10 M9
The roots become, VSS VSS
120523-03
1.) The dominant pole increased slightly because RI (output of first stage) is decreased.
VDD VDD
2.) The output pole is increased by a rds7 rds7
Cc
-Agm6 vout A vout
factor of A to get new p2 ≈ C 1
II M8 GB·Cc » 0 M6
CII
M6 CII
3.) The pole at the source of M8 (-gm8/Cc)
becomes a zero on the negative real axis. 120523-04

Roots: jw
s
-Agm6 -gm8 -1 gm6
C2 Cc gm6rds2Cc Cgd6 120523-05
† B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
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Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-26

Issues with the Previous Method†

The previous technique assumed that the gate-source capacitance of M8 could be
neglected. Unfortunately, this assumption ignores a pair of complex poles near the unity
gain frequency. Below is the small signal model with the capacitance that causes this
that includes Cgs8. Cgd6 Cc
+ + +
1 Cgs8
Iin R1 V1 Vs8 R2 C2 Vout
gm8 gm6V1
- gm8Vs8 - -
160311-01

The solution proposed in the reference below is to decrease the impedance at the source
of M8 by using a negative feedback loop. Below is a possible solution that will have
better phase margin. VDD
M11 M12 M16 M7
M13
vOUT

M8 Cc
M6

M10 M9 M14 M15

160311-02
VSS

† Uday Dasgupta, “Issues with ‘Ahuja’ Frequency Compensation Technique,” Proc. of IEEE Inter. Symposium on Radio Frequency Integration
Technology, Jan. 9, 2009, pp. 326-329.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-27

POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMP

What is PSRR?
Av(Vdd=0)
PSRR = A (V =0)
dd in

How do you calculate PSRR?

You could calculate Av and Add and divide, however

Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout → Vout(1+Av) = AddVdd

Vout Add Add 1
 =  = (Good for frequencies up to GB)
Vdd 1+Av Av PSRR+

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-28

Approximate Model for PSRR+

1.) The M7 current sink causes VSG6 to act like a battery.

2.) Therefore, Vdd couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-29

Approximate Model for PSRR-

M6 VDD
Cc Vout
M3 M4
rds7
vout
M1 M2 CI CII
Vss Zout

M5 rds7
Vss Path through Cgd7
VBias M7
is negligible
VBias connected to VSS VSS
Fig. 180-11

What is Zout?
Vt  gmIVt 
Zout = I  It = gmIIV1 = gmIIG +sC +sC  Cc CII+Cgd7 It
t  I I c
+ rds6||rds7 +
GI+s(CI+Cc) CI RI V1 gmIIV1 Vout Vt
Thus, Zout = g g gmIVin
- -
mI MII
150131-01
rds7
1+ Z
Vout out s(Cc+CI) + GI+gmIgmIIrds7 -GI
 = =  Pole at
Vss 1 s(Cc+CI) + GI Cc+CI
The negative PSRR is much better than the positive PSRR.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-30

SUMMARY
• The output of the design of an op amp is
- Schematic
- DC currents
- W/L ratios
- Component values
• Design procedures provide an organized approach to creating the dc currents, W/L
ratios, and the component values
• The right-half plane zero causes the Miller compensation to deteriorate
• Methods for eliminating the influence of the RHP zero are:
- Nulling resistor
- Increasing the magnitude of the output pole
• The PSRR of the two-stage op amp is poor because of the Miller capacitance, however,
methods exist to eliminate this problem
• The two-stage op amp is a very general and flexible op amp

CMOS Analog Circuit Design © P.E. Allen - 2016