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Compre A

The document is a comprehensive examination for an Analog and Digital VLSI Design course. It contains 7 questions assessing the student's knowledge of CMOS and transmission gate logic design, including implementing logic functions using different styles, calculating delays, drawing circuit diagrams, and analyzing feedback amplifiers. The questions cover topics such as implementing logic functions using CMOS gates, calculating delays, drawing transmission gate logic, analyzing pseudo-NMOS logic gates, implementing an XOR gate with 6 transistors, and analyzing feedback amplifiers including calculating gains and noise.

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94 views3 pages

Compre A

The document is a comprehensive examination for an Analog and Digital VLSI Design course. It contains 7 questions assessing the student's knowledge of CMOS and transmission gate logic design, including implementing logic functions using different styles, calculating delays, drawing circuit diagrams, and analyzing feedback amplifiers. The questions cover topics such as implementing logic functions using CMOS gates, calculating delays, drawing transmission gate logic, analyzing pseudo-NMOS logic gates, implementing an XOR gate with 6 transistors, and analyzing feedback amplifiers including calculating gains and noise.

Uploaded by

k.b.aditya reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS


FIRST SEMESTER, 2018-2019
COMPREHENSIVE EXAMINATION, ANALOG & DIGITAL VLSI DESIGN (EEE F313/INSTR F313)

Closed Book PART A Duration : 2 Hours Maximum Marks: 70 Date 03.12.2018

Instructions: Write answers in the space provided. Overwritten/pencil-written answers will not be rechecked. Answer
without proper suffix and without sign will be considered wrong.

1. Implement the following function using (a) What is Rout if circuit is disconnected at P?
(a) complex CMOS gate and inverter (b) What is VP /VX ?
(b) 2-levels of CMOS NOR gates (c) What is overall Rout of the circuit?
If load capacitor is 100 units and input capacitor is Neglect body effect.
20 units what is minimum normalized delay in both
cases? What is the size of individual transistors (write
size of each MOSFET in diagram, you can write size in
fractions)?

Y = (A + B +C)(D + E + F)
2. Draw the circuit diagram of following functions using
transmission gates
(a) 2-input NAND gate
(b) 2-input OR gate
(c) 3-input XOR gate (use minimum number of
transmission gates)

3. In pseudo-NMOS inverter, the driving strength of


PMOS is chosen to be 1/6 times that of NMOS.

(a) Draw the inverter with sizes of NMOS and PMOS.


Calculate the logical efforts and parasitic delays
for both transition.
(b) Draw 3-input NAND gate with pseudo-NMOS
style showing transistor sizes. Calculate its 7. Calculate the input-referred 1/f and thermal noise
logical efforts and parasitic delays for both the voltage for the circuit shown in the figure below.
transitions.

4. Draw the XOR gate with transmission gates and


inverters. Total number of transistors should be 6.
Complemented inputs are not available directly.

5. For the circuit shown in figure, calculate the following


including loading effect and assuming λ = γ = 0.
(a) Open loop gain
(b) Loop gain
(c) Feedback factor
(d) Closed-loop gain

6. For the circuit given below


Name: ID No.:

Q1a - Complex CMOS gate and inverter (3 Marks)

G = __________________(2 Marks)

B = __________________(1 Mark)

H = __________________(1 Mark)

f = __________________(2 Marks)

P = __________________(2 Marks)

Min. Delay = ___________(2 Marks)

Q1b - 2 Levels of CMOS NOR gate (3 Marks)

G = __________________(2 Marks)

B = __________________(1 Mark)

H = __________________(1 Mark)

f = __________________(2 Marks)

P = __________________(2 Marks)

Min. Delay = ___________(2 Marks)

Q2a(2 Marks) Q2c(4 Marks)

Q2b(2 Marks)
Q3a - Pseudo-NMOS Inverter(2 Marks)
gu = __________________(1 Marks)

gd = __________________(1 Marks)

pu = __________________(1 Marks)

pd = __________________(1 Marks)

Q3b - 3 Input Pseudo-NMOS NAND Gate(2 Marks)


gu = __________________(1 Marks)

gd = __________________(1 Marks)

pu = __________________(1 Marks)

pd = __________________(1 Marks)

Q4(4 Marks) Q5a(2 Marks)

Q5b(2 Marks)

Q5c(2 Marks)

Q5d(2 Marks)

Q6a(2 Marks)

Q6b(2 Marks)

Q6c(2 Marks)

Q7(6 Marks)

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