LiteX: SoC builder and library

OSDA Workshop (2019), Florence, March 29

Florent Kermarrec, florent@enjoy-digital.fr

1
 Enjoy-Digital
Founded in 2011.
FPGA consulting / Full FPGA based systems design.
Reuse and create open-source tools/cores to be more efficient.

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OSDA Workshop (2019), Florence, March 29
Presentation:
1) Let’s design an FPGA SoC the traditional way...
2) LiteX : Build your hardware, easily!
3) Systems using Migen/LiteX and Future!

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OSDA Workshop (2019), Florence, March 29
Let’s design an FPGA SoC the traditional way...

LiteX: SoC builder and library 4

OSDA Workshop (2019), Florence, March 29
Create a simple SoC:

- Choose a CPU.
- Add cores around it.
- Connect all that.
- Write low-level software.

[...] LiteX: SoC builder and library

OSDA Workshop (2019), Florence, March 29
5
Create a simple SoC:

[One day later...]

Great we got it working by only

using open-source cores!

~ 500 LOC for the wrapper.

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OSDA Workshop (2019), Florence, March 29
Let’s add our own core:

Let’s create the new core, simulate it with an open-source

simulator.

Everything is working fine, let’s integrate it!

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OSDA Workshop (2019), Florence, March 29
Let’s add our own core:

It’s… almost working, but not behaving as expected, is it a

bug in the core or something we miss-understood in the
datasheet of the chip we are interfacing with??

We need to see what is going on…*

(*signal is not observable with an external logic analyzer)
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OSDA Workshop (2019), Florence, March 29
Let’s add our own core:
No standard way to debug FPGA designs:

1) Create our own debug tools: ~a few days, limited

functionalities/capabilities.

2) Use vendor’s free embedded logic analyzer...

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OSDA Workshop (2019), Florence, March 29
 Let’s add our own core:
No standard way to debug FPGA designs:

1) Create our own debug tools: ~a few days, limited

functionalities/capabilities.

2) Use vendor’s free embedded logic analyzer…*

* Just this time...
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OSDA Workshop (2019), Florence, March 29
Let’s add our own core:

OK, issue is understood (was a bad interpretation of the

spec), core is adapted and now working fine…

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OSDA Workshop (2019), Florence, March 29
 Let’s add some RAM:
We need RAM to run an OS, our board has DDR3.

Let’s look at open-source solutions… Nothing seems to exist

except something called LiteDRAM written in ...Python, how
can it be serious? :)

Let’s generate a controller with vendor’s tools…*

* Just this time… (again)
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OSDA Workshop (2019), Florence, March 29
We could continue with several similar examples…:
- How to support different vendors and reuse the same
methodology/cores?
- How to build high performance systems at a
reasonable cost.
- How to create complex SoCs and limit LOC
- ....
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OSDA Workshop (2019), Florence, March 29
In addition to open-source FPGA toolchains, there is a
need to high level tools and high performance cores...

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OSDA Workshop (2019), Florence, March 29
LiteX: Build your hardware easily!

LiteX: SoC builder and library 15

OSDA Workshop (2019), Florence, March 29
Migen : A python HDL toolbox.

LiteX: SoC builder and library 16

OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.

What is Migen?

An alternative HDL
based on Python

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OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.

FHDL is a Python DSL (Domain Specific Language)

defined by Migen and allow generating Verilog or
instanciating Verilog/VHDL from Python code.

Principle: Use Python to create a list of combinatorial

and synchronous assignments.
self.comb += [“...”]
self.sync += [“...”]
Led blinker

And generate a verilog file from these assignments. LiteX: SoC builder and library 18
OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.

Migen.FHDL DSL: Python used for

elaboration by
manipulating these objects
to create the logic.

Switch from hardware

paradigm to software Led blinker
paradigm!
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OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.

Migen.Genlib, a library with most of the base elements required to digital logic:
- Record. (Group signals together with direction)
- FSM. (Finite State Machine).
- Clock Domain Crossing.
- Memory.
- Instance. (reuse Verilog/VHDL)
- FIFO. (Synchronous, Asynchronous)
- ...

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OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.

Migen.Sim, a simulator in native Python:

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OSDA Workshop (2019), Florence, March 29
 Migen : A python HDL toolbox.
Could be seen as the
lowest layer of an
HLS.
Migen != HLS
(High Level Synthesis) Could be reused in the
future to create an
but...
HLS but still full
control on the
generated logic.

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
Provide the infrastructure to create complex SoCs with Python/Migen:

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
Originated from a collaboration on MiSoC with :

MiSoC still used successfully by M-Labs for physics equipment in

LiteX since 2015 focuses on embedded-systems and provides a wider collection

of tools/cores.
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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!

LiteX’s key features to simplify

development / integration / debug:

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!

Simple SoC target

Reduce the amount of code to create a SoC.

Execution on hardware or with litex_sim LiteX: SoC builder and library 26

OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
With vendor toolchains… for now :) Ultrascale
Cyclone V
Scaling and portability
Stratix 10
7-Series

Spartan6
With open-source toolchain:
Yosys/Trellis/Icestorm/Nextpnr
(Even DDR3 / 1Gbps Ethernet!) 2 Mluts / 40k $
ECP5
w ell…
re tty
le p
iCE40 Sca
Used on very various FPGAs

1 Kluts / ~few $ LiteX: SoC builder and library 27

OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
CPUs integration/support:
- LM32
- OpenRisc (Mor1kx)
- RISC-V (PicoRV32, Vexriscv, Minerva)
- ARM (*through AXI on ZYNQ)
- X86 (*through PCIe)
Switch CPU and in command line:
./arty.py --cpu_type=vexriscv --cpu_variant=lite

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!

Ecosystem of highly configurable and high performance cores:

SDR/DDR/DDR2/DDR3/DDR4 SATA I/II/III: 1.5/3.0/6.0Gbps
(Up to > 80 Gbps with DDR4 - 64 bit) (400MB/s writes / 500MB/s reads)

Ethernet MAC/IP/UDP up to 1Gbps SDCard up to 55MB/s

PCIe / DMA / Scatter-Gather

Embedded Logic Analyzer
(Up to Gen2 X4)

Cores are designed to be used on various FPGAs, adding support for a new
devices = just adding a new PHY.
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[...] and more at http://github.com/enjoy-digital
OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!

Constraint propagation / reduced duplication:

User defined constraints (specific to application) Board specific constraints (automatically derived from DRAM config)
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 LiteX : Build your hardware, easily!

Interactive simulation (emulation) with litex_sim/Verilator:

litex_sim --cpu-type=lm32 litex_sim --cpu-type=vexriscv litex_sim --cpu-type=or1k

<5s build time / ~1MHz execution speed, very useful for software dev.
Easy to add additional C++ plugins (JTAG, VGA, Ethernet, etc…) LiteX: SoC builder and library 31
OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
Various OS support:

Micropython Zephyr Linux

From bare-metal to Linux OS, collaboration with others open-source enthusiasts.

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
Automatic CSR registers collection / software header generation:

C header or CSV file that can be use by scripts/software

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OSDA Workshop (2019), Florence, March 29
 LiteX : Build your hardware, easily!
Debug infrastructure with LiteX Server / LiteScope and the bridges:

Speed up development, use

Python scripts to control/debug
the same tools for all devices!
the hardware.

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OSDA Workshop (2019), Florence, March 29
Systems using Migen/LiteX and Future!

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OSDA Workshop (2019), Florence, March 29
 Systems using Migen/LiteX and Future!

Used for our commercial projects:

- Custom FPGA systems/designs for clients.
- Customizations of cores for clients to replace commercial/vendor’s
cores: LiteSATA on a 100Mpix camera, LiteDRAM on Ultrascale/DDR4
boards, etc...

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OSDA Workshop (2019), Florence, March 29
 Systems using Migen/LiteX and Future!
- Custom ASIC characterization equipment

- ...
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OSDA Workshop (2019), Florence, March 29
 Systems using Migen/LiteX and Future!

But also by others to create FPGA based systems:

Opsis NeTV2 Fomu

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OSDA Workshop (2019), Florence, March 29
 Systems using Migen/LiteX and Future!

But also by others to create FPGA based systems:

DRAM

SPI Flash

Ethernet

HDMI In /Out

SDCard

NeTV2
PCIe (X4)
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OSDA Workshop (2019), Florence, March 29
 Systems using Migen/LiteX and Future!

Future: continue collaboration with others open-source enthusiasts to:

- Improve tools/cores/documentation/verification.
- Ease cores generation and reuse as standalone cores. (FuseSoC?).
- Add nMigen support (or switch to it) (almost 100% compatible, better
doc/tests, adds formal verification).
- Improve current OS support/drivers and add drivers for others cores lite
LiteSATA, LiteSDCard, LiteScope, LiteICLink, etc…
- Add others cores :)
- ...

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OSDA Workshop (2019), Florence, March 29
You are a student and would like to work on this? (or know one)
Applications are now open and TimVideos/Symbiflow organizations can accept
LiteX related projects.

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OSDA Workshop (2019), Florence, March 29
Migen/LiteX is not magic… but very powerful and could help you to be more
efficient/productive.
Can be used to create full designs in Python or just as a tool for integration, core
generation, simulation…
Want to try it or to help :) ? : http://github.com/enjoy-digital/litex (BSD License)

Get in touch on IRC (Freenode):

Migen: #m-labs Questions ?
LiteX: #litex
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OSDA Workshop (2019), Florence, March 29