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Digital Clock

This document summarizes a digital clock design that uses a 5-bit hour output, 6-bit minute and second outputs, and active-low reset and clock signals. It can be configured for 12-hour or 24-hour display format using the clk_format signal. Upon reset, all outputs are cleared to 0. Five test cases are described to test functionality like setting the time from a command line, reset behavior, and switching between time formats.

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159 views2 pages

Digital Clock

This document summarizes a digital clock design that uses a 5-bit hour output, 6-bit minute and second outputs, and active-low reset and clock signals. It can be configured for 12-hour or 24-hour display format using the clk_format signal. Upon reset, all outputs are cleared to 0. Five test cases are described to test functionality like setting the time from a command line, reset behavior, and switching between time formats.

Uploaded by

prasad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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DIGITAL CLOCK :

Introduction :
This digital clock is active low reset and positive edge sensitive clk device. By
default the device is in 12 hour format. Using clk_format signal we can able to
switch between 24 hours and 12 hours mode. Upon reset all the device outputs
will be set to 0. We can able to set the the time using command line.

Block diagram :

Signal description :

s.no Signal name Description


1 Hour[4:0] It is 5 bit output signal for hour in digital
clock. We need 5 bits for representing 24
hours per day
2 Min[5:0] It is 6 bit output signal for minutes in
digital clock. We need 6 bits for
representing60 minutes in a hour.
3 Sec[5:0] It is a 6 bit output signal for seconds in
digital clock. We need 6 bits for
representing 60 seconds ina minute.
4 clk It is a single bit signal for synchronizing
digital clock to the standard frequency
5 reset This is a active low reset signal.upon reset
the clock will set to zero and it stays in
zero until reset set to high.
6 clk_format This is a single bit signal for setting time
format to 24hour(clk_format=1) or 12
hour (clk_format=0) in the clk

Test cases :

s.n Condition Description Expected output


o
1 Settung This will ensures The clock should start from the
time whether the device given time.
through starting from the
command time which we
line given through
command line
2 Checking This will check the The clock should start from
without functionality of the 00:00:00 (hh:mm:ss)time.
command clock if time given
line input through command
time line initially.
3 Reset = 0 This will check the All outputs(hour,minute,and sec )
operation of clock should set to 0.
upon reset.
4 Reset =1 This will check the The clock should start counting
functionality of the from 0 as no input time is given.
clk, if reset is
removed.
5 Changing This will check the After turning on clock should
clk_format operation of a clock operate in 12 hours mode as
format changing clk_format is 0 initially.after
during operation. changing clk_format it should
operate in 24 hours mode. Vice
versa should be checked.

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