24/07/2018 VLSI Design Verification and test - - Unit 7 - Physical Design

reviewer1@nptel.iitm.ac.in ▼

Courses » VLSI Design Verification and test

Announcements Course Ask a Question Progress Mentor

Unit 7 - Physical
Design

Course
outline WEEK 4 ASSIGNMENT
The due date for submitting this assignment has passed. Due on 2016-08-22, 23:58 IST.
How to access
the portal ? Submitted assignment

Introduction and 1) Which of the following statement(s) is (are) true about moore style FSM? 1 point
Overview of VLSI
Design the output is a function of the present state.
the output is a function of the present state and inputs.
Scheduling in the output is a function of the next state.
High-Level
Synthesis the output is a function of the next state and inputs.

No, the answer is incorrect.

Resource Score: 0
Sharing and
Binding in HLS Accepted Answers:
the output is a function of the present state.
Logic Synthesis
2) Which of the following statement(s) is(are) incorrect about Boolean expressions? 1 point

Physical Design All Boolean expressions can be implemented as a two-level logic function.
Physical Design All Boolean expressions can be implemented as a three-level logic function.
(Part-1) All Boolean expressions can be implemented as a four-level logic function.
Physical Design None of the above
(Part-2)
No, the answer is incorrect.
Physical Design Score: 0
(Part-3)
Accepted Answers:
Quiz : WEEK 4 None of the above
ASSIGNMENT
3) The ON-set of a Boolean function is composed of the following min-terms: 1, 2, 5, 6, 7, 9, 2 points
Introduction to 10. The don't cares are: 0, 3, 11, 13. The cardinality of the exhaustive set of prime implicants is:
Verification
Techniques 5
6
Syntax and
semantics of 4
CTL, 7
Equivalences
between CTL No, the answer is incorrect.
formulas and Score: 0
Introduction to
Model Checking Accepted Answers:
6
CTL Model 4) The minimum number of essential prime implicants for the Boolean function in Q3 are: 2 points
checking
Algorithms and
4
Introduction to
Binary Decision 3
Diagrams

https://onlinecourses.nptel.ac.in/noc16_ec08/unit?unit=20&assessment=73 1/3
24/07/2018 VLSI Design Verification and test - - Unit 7 - Physical Design

5
Binary Decision
Diagram and 2
Symbolic model
No, the answer is incorrect.
checking
Score: 0
Introduction to Accepted Answers:
Digital Testing 3

Fault Simulation 5) For the ESPRESSO algorithm, which of the following statement(s) is(are) true: 1 point
and Testability
Measures The expand step produces a cover over prime implicants.
The irredundant step produces a cover over essential prime implicants.
Combinational The reduce step retains a cover over all prime implicants.
Circuit Test
Pattern None of the above.
Generation
No, the answer is incorrect.
Score: 0
Sequential
Circuit Testing Accepted Answers:
and Scan Chains The expand step produces a cover over prime implicants.
The irredundant step produces a cover over essential prime implicants.
Built In Self Test The reduce step retains a cover over all prime implicants.
(BIST)
6) 2 points

For the given circuit diagram with the initial partition as shown through the cut line, obtain a netlist. With
this netlist as an input, a correct enumeration of the vertices on each side of the partition after the
second iteration of the inner repeat loop in the Kernighan-Lin (KL) algorithm is:

Partition-1: a, e, f, g. Partition-2: b, c, d, h
Partition-1: a, c, e, g. Partition-2: b, d, f, h
Partition-1: a, c, g, h. Partition-2: b, d, e, f
Partition-1: c, d, f, g. Partition-2: a, b, e, h

No, the answer is incorrect.

Score: 0
Accepted Answers:
Partition-1: a, c, e, g. Partition-2: b, d, f, h

7) For Q6, the absolute gain (g) at the end of the third iteration is: 2 points

-2
2
-1
1

No, the answer is incorrect.

Score: 0
Accepted Answers:

https://onlinecourses.nptel.ac.in/noc16_ec08/unit?unit=20&assessment=73 2/3
24/07/2018 VLSI Design Verification and test - - Unit 7 - Physical Design
-2

8) For Q6, the final partition and cut-size is: 2 points

Partition-1: a, b, c, h. Partition-2: d, f, g, e and cut-size: 2

Partition-1: a, f, c, e. Partition-2: d, b, g, h and cut-size: 1
Partition-1: a, b, c, e. Partition-2: d, f, g, h and cut-size: 3
Partition-1: a, b, g, h. Partition-2: d, f, c, e and cut-size: 4

No, the answer is incorrect.

Score: 0
Accepted Answers:
Partition-1: a, b, c, e. Partition-2: d, f, g, h and cut-size: 3

Previous Page End

© 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -

A project of In association with

Funded by

Powered by

https://onlinecourses.nptel.ac.in/noc16_ec08/unit?unit=20&assessment=73 3/3