Novel Glitch Reduction Techniques for Ultra-Low Power Digital Design

Weidong Sun, Ken Choi

Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL USA
E-mail: wsun26@hawk.iit.edu, kchoi@ece.iit.edu

Abstract approach and its benefits in comparison to the traditional

This paper presents some proposed and new techniques one. Section 5 illustrates and compares the results in several
in comparison to a traditional one for register-transfer level RTL circuits in terms of power consumption and area
(RTL) circuits. The traditional technique focuses on killing between the proposed and traditional techniques.
glitches in both the control and data path parts of the circuit 2. Glitch Generation
to reduce power consumption. By analyzing and simulating
In this section, we analyze and illustrate how glitches
the generation and propagation of glitches in some
generate in a circuit in terms of controller and data paths by
benchmark circuits, we found out some issues when killing
Fig. 1. This circuit Fig. 1 is consist of two full adders FA1,
glitches in both control and data paths using traditional
FA2 and one 2:1 multiplexer MUX, and control signal ‘SEL’
approach. In some cases, the traditional approach selects the results from either FA1 or FA2 as an output
minimizing glitches, at the same time, still consume a huge ‘OUT’ of MUX.
amount of power though glitches are killed because a great
many extra transistors are brought as a trade-off. And much
more extra transistors have a deep impact on area and delay,
which is neglected in the traditional technique. Besides, it
could not kill glitches in control path when two selected data
are not correlated. Therefore, our key point of this paper is Figure 1: Glitch generation in both controller and data paths
to solve these issues that the traditional technique leaves,
and propose more techniques to kill glitches in other cases. 2.1 Glitch Generation in Data Path
Keywords As Fig. 1 shows, both two full adders FA1 and FA2
Controller/data path, multiplexer gating, XOR/XNOR generate and propagate glitches in data path. We analyze
reconstruction, glitch generation and analysis, power one full adder FA1 and suppose that FA1 is a 2-bit carry
consumption, area, register-transfer level, glitch delay block ripple adder shown in Fig. 2.
As Fig. 2 shows, the value of a and b change from ‘11’
1. Introduction and ‘01’ to ‘10’ and ‘10’ at the same time. When connecting
As we know, at least eighty percent of the power in ASIC cin to the ground, the carry signal c0 depends on the sum of
design is fixed when the circuit is finished. In order to save a[0] and b[0]. So when a[0] and b[0] change from both ‘1’
more power, there is a systematic method that detects to both ‘0’, the value of c0 changes from ‘1’ to ‘0’. As there
opportunities either directly from RTL or from the mapping are transistor delays in the full adder, the
results. It cannot fix a broken design - it cannot close your
critical path if architecture is wrong. backend flow cannot
fix micro-architecture. Design architecture and RTL coding
style have a deep impact on dynamic and static power
dissipation. In this case, more power issues should be solved
before synthesis during RTL itself [1].
In register-transfer level, there are lots of techniques in
saving power consumption including glitch reduction,
operand isolation, pre-computation logic, clock gating etc Figure 2: Glitch generation from a 2-bit carry ripple adder
[2-4], where glitches in combinational circuits is the most
common and unexpected case. This issue has been realized falling transition of c0 occurs later than the transitions of a[0]
and solved by a traditional technique[4]. It reduces glitching and b[0]. And then a falling transition of c0 leads to a
power consumption in RTL circuits by minimizing falling transition of sum[1] with a transistors delay. As a
propagation of glitches from control as well as data signals result, a glitch is generated on sum[1]. Furthermore, with the
through the RTL circuit. But, there are still some drawbacks increasing number of bits of the full adder, there will be
in the traditional technique. Hence, this paper presents some much more glitches generated at the output sum of higher
proposed techniques to gain more benefits in comparison to bits. Not only full adders, but also all the circuits with
the traditional one. unbalanced paths inside could generate glitches due to the
The rest of this paper is organized as follows. Section 2 transistors delay.
analyzes and illustrates how describes the experimental Among these circuits with unbalanced paths, glitches can
glitches generate in controller/data path. Section 3 be generated and propagated much more easily and
summarizes how glitches are killed using the traditional frequently in a combinational logic circuit including
technique and its issues. Section 4 presents a proposed
XOR/XNOR gates. Fig. 3 is a partial combinational circuit a delay element on the select signal SEL in order to delay the
in benchmark s298 which is designed using 45nm CMOS falling transition so that it can avoid the glitch shown in Fig.
5. Delay element can be achieved by inserting some
inverters or buffers in series.
Suppose that control signal SEL is glitchy shown in Fig. 6,
if both data input signals A and B are ‘1’, the output g3 will
be glitchy a lot due to the interaction of glitchy g1 and g2.
The traditional technique is to insert a consensus term, a
NAND gate G0, into the circuit shown in Fig. 6. In this case,
Figure 3: Glitch generation from an XOR gate glitches are killed at the output of G3.

predictive technology model. It is obvious when transitions

do not occur on G2 and G22 simultaneously, a glitch is
generated by the XOR gate and propagated to the following
circuit. Since two inputs of an XOR or XNOR gate almost
cannot transit at the same time, so a combinational logic
circuit including XOR or XNOR gates has an important
Figure 6: Consensus term to minimize glitches propagate
influence on glitch generation in a circuit.
2.2 Glitch Generation in Controller Path 3.3 Issues using Traditional Technique
We analyze the 2:1 multiplexer MUX at gate level shown The traditional technique can kill glitches from both data
in Fig. 4. and controller path in most cases indeed. However, it
minimizes glitches propagation with negligible area as a
trade-off in data path. For example in Fig. 1, if A is the
output of the highest bit slice sum[31] of a 32-bit full adder,
and a worst case can be happened that there are a huge
amount of glitches at the signal A shown in Fig. 7. In order
to delay the falling transition of SEL, lots of buffers or
inverters have to be inserted.
Figure 4: Glitch generation in controller path

In Fig. 4, suppose that the both input data signals A and B

are glitch-free and those value are set to ‘1’. And control
signal SEL transits from ‘1’ to ‘0’. Since the path from SEL
to g1 is longer than the path from SEL to g2 due to one more
inverter connecting to the input of G1, so the falling
transition of g1 arrives later than the rising transition of g2. Figure 7: Delay element costs lots of transistors to avoid glitchy
In this case, there is a glitch generated at the output signal data signal
g3 of G3.
For one thing, area must be increased a lot. For another
3. Glitch Reduction with Traditional Technique thing, inserted transistors still dissipate power.
In section 2, we have analyzed how glitches generate in Besides, inserting a consensus term in controller path
both data/controller paths. This section summarizes how to cannot solve the issue if two inputs data are not correlated.
kill glitches with traditional technique also from two aspects These issues are not concerned in the traditional technique.
including data/controller paths. And when two inputs data are correlated, much more
In Fig. 2, we illustrate a glitch generated at the output of glitches can be killed from the previous level instead of
a 2-bit full adder. In this case, suppose that A is glitchy inserting a consensus term in controller path.
because it is a output of FA1 according to Fig. 1. Now we
split and discuss the half of Fig. 4 just including an inverter 4. Glitch Reduction with Proposed Technique
and a NAND gate G1 shown in Fig. 5. In this section, we propose some new techniques to kill
glitches from both controller and data paths, and solve a
problem that XOR or XNOR gate can always generate
glitches.
4.1 Glitch Delay Block
In Fig. 7, it shows lots of delay elements such as inverters
or buffers have to be inserted to delay the falling transition
Figure 5: Delay control signal to avoid glitchy data signal of control signal SEL because the delay time between the
first glitch and the last glitch is quite long. However, since
Since there is a glitch on signal A, if the falling transition
the width of one glitch is considerably negligible comparing
of select signal SEL arrives earlier than the glitch of A, this
to the width between two adjacent glitches, so we can delay
glitch will propagate to the output of G1. The traditional put
glitchy signal itself and then make an AND or OR logic path B is selected when SEL is 0. In this case, lots of power
operation with delayed glitchy signal. This technique is are wasted due to glitches in the combinational logic parts
implemented shown in Fig. 8 called glitch delay block(same and the following level circuit of the mux.
as rising or falling delay block).

Figure 8: Glitch delay block to kill glitches Figure 10: (a) Glitches propagate in data path (b) Implement mux
gating in data path
In this case, the delay element in glitch delay block just
needs a few transistors to delay the width of the widest As we know, when select signal SEL is 1, data path B is
glitch in glitchy signal. In contrast, delaying control signal blocked. At the same time, when select signal SEL is 0, data
with the traditional technique wastes a great many path A is block. In this case, making an AND(OR) operation
transistors. As a consequence, power consumption and area to the source of generating glitches with select signal SEL
are reduced a lot. so that the data path will be blocked if it is not selected by
4.2 Mux Gating select signal SEL shown in Fig. 10 (b).
In this section, we try to find out the sources of those Note that with mux gating in data path, glitches will not
glitches that propagate to the multiplexer, and then reduce propagate from sources to the following level circuit if this
glitches implemented by the multiplexer. We define this implemented data path is not selected by select signal of the
technique as mux gating. mux, else glitches will propagate to the mux outputs. And
there should not be any fan-out branches in the
4.2.1 Mux Gating in Controller Path combinational logic part shown in Fig. 10. Next we show a
As Fig. 9 (a) shows, assume that data signal n3 is glitchy procedure how to implement mux gating into a common
generated by the OR gate where two inputs are n1 and n2. circuit:
Then glitchy signal n3 is propagated to the select signal of 1. Find out all the multiplexers in a circuit, and then
the mux SEL. In this case, glitches consume a huge amount analyze whether two input data signals and one select signal
of power in combinational logic between n3 and SEL as well are glitchy.
as the following level circuit of the mux. 2. If any of them are glitchy, then follow every path of
glitchy signals to the previous level circuit until the sources
are found out that generate glitches. During searching the
sources, make sure that there should not be any fan-out
branches in the searched data path, else stop searching and
consider current point as the source. Finally, mark these
sources.
3. For glitches in data path, make an AND(OR)
operation to the marked sources in step 2 with select signal
Figure 9: (a) Glitches propagate throughout SEL to the following
circuit (b) Implement mux gating in controller path SEL of the mux if this data path is selected when select
signal SEL=1(SEL=0); For glitches in controller path,
In order to kill glitches from the source instead of from making an AND operation to the source with an XOR
the mux along the controller path, making an AND operation of two inputs data signal A and B of the mux.
operation to the output of the source(OR gate in Fig. 9 (a)) 4.3 XOR/XNOR Gate Reconstruction
with an XOR operation of two inputs data signal A and B In section 2, we have shown that a combinational logic
shown in Fig. 9 (b). circuit containing XOR/XNOR gates can generate glitches
Note that there should not be any fan-out branches in the much more frequently in comparison to other unbalanced
combinational logic part shown in Fig. 9, else disordered paths inside of a circuit. Some common methods like
logic function will be occurred. Besides, with the mux delaying the input signals cannot avoid glitch generation.
gating in controller path, glitches will be prevented from the Our technique is to reconstruct XOR/XNOR gates as well as
output of sources if two inputs data values of the mux are surrounding logic.
correlated (<0, 0> or <1, 1>), else this technique will not In Fig. 3, an XOR gate generates a glitch propagating to
make a contribution. signal G119. In this case, if we consider signal G22, G2,
4.2.2 Mux Gating in Data Path and G0 as logic inputs, and signal G119 as a logic output.
As Fig. 10 (a) shows, assume that data signals n1 and n2 Firstly, we obtain a logic expression:
are sources that generate and propagate glitches to two data G 119  G 2  G 0
G 22  G 22  G 0
G 2 (1)
paths of the mux. And path A is selected when SEL is 1, and
 TABLE I
EXPERIMENTAL RESULTS

Circuit Traditional Optimized % Power % Area Red.

Power Area Slack Power Area Slack Red.
[mW] [ m 2 ] [ns] [mW] [ m 2 ] [ns]
S298 1.340 401.72 3.44 1.253 319.59 3.26 6.49 20.44
S344 1.622 359.01 3.34 1.507 278.48 3.27 7.09 22.43
S349 1.639 344.47 3.33 1.485 275.68 3.30 9.40 19.97
S382 1.691 445.37 3.44 1.456 384.84 3.43 8.22 13.59
S386 0.800 256.71 3.44 0.694 224.13 3.43 13.26 12.69
S400 1.697 437.86 3.46 1.590 392.23 3.44 6.33 10.42
S420 1.250 376.85 3.23 1.188 279.96 3.20 4.93 25.71
S444 1.684 437.39 3.42 1.592 370.16 3.39 5.45 15.37
S510 1.184 415.80 3.34 0.950 291.85 3.31 19.80 29.81
S526 1.644 484.79 3.39 1.585 365.39 3.30 3.56 24.63
S526n 1.648 491.83 3.39 1.597 378.17 3.30 3.12 23.11
S641 1.506 406.88 3.00 1.331 369.32 3.03 11.64 9.23
S820 0.966 481.03 3.30 0.799 394.16 3.28 17.28 18.06
S832 0.973 481.03 3.29 0.833 395.89 3.27 14.41 17.70
S838 2.232 762.14 2.72 2.122 531.82 2.61 4.93 30.22
S953 2.759 895.89 3.22 2.297 803.17 3.25 16.76 10.35
S1196 3.228 970.98 2.98 2.521 696.39 2.91 21.89 28.28
S1238 3.220 979.90 3.05 2.567 770.69 2.99 20.27 21.35
S1423 6.761 1610.64 1.70 5.723 1078.00 1.61 15.35 33.07

6. Conclusions
This paper presents some proposed techniques to reduce
power consumption as well as concerning area issue by
minimizing glitches in the circuit. A traditional technique
has applied to kill glitches previously. The issue of
traditional technique is when it minimizes glitches, at the
same time, extra power consumption is brought because of
lots of additional transistors inserted in the circuit. Besides,
further more area increases as a trade-off. Proposed
Figure 11: Combinational logic containing XOR gate technique can deal with both power consumption and area
reconstruction issue applying to kill glitches in the circuit. And another
case that XOR/XNOR gates generate plenty of glitches is
And then, we reconstruct logic gates according to expression
solved in this paper as well. Although proposed technique
(1) shown in Fig. 11. This is a small part circuit in
may be not better than traditional one in a few cases when a
benchmark s298 using 45nm CMOS library. In Fig. 11, we
small group of glitches are generated in the circuit, proposed
found that the falling transition of G22 happened later than
approaches will be more efficient in most cases of plenty of
G2’s falling transition approximately. And in 45nm CMOS
glitches produced.
library, two NOR gates delay lead to the rising transitions of
n1 and n2 happened later than falling transitions of G22 and 7. References
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not unique. Several other types of reconstruction are also
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synthesis techniques: a tutorial, Computers and Digital
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are reduced more or less after an optimization to the Optimization, Design Automation Conference
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