Spintronic Logic Gates for Spintronic Data Using

Magnetic Tunnel Junctions

Shruti Patil, Andrew Lyle, Jonathan Harms, David J. Lilja and Jian-Ping Wang
Department of Electrical and Computer Engineering
University of Minnesota Twin Cities
{pati0036,lylex031,harms047,lilja,jpwang}@umn.edu

Abstract— The emerging field of spintronics is undergoing are programmability, noise-resistance and radiation-hardness
exciting developments with the advances recently seen in spin- ([3], [5]). The combination of these desirable properties in a
tronic devices, such as magnetic tunnel junctions (MTJs). While single device makes them promising devices for applications
they make excellent memory devices, recently they have also
been used to accomplish logic functions. The properties of MTJs in many areas of digital computing.
are greatly different from those of electronic devices like CMOS As technology nodes shrink in size, the current state-of-
semiconductors. This makes it challenging to design circuits that the-art CMOS technology is facing challenges such as scal-
can efficiently leverage the spintronic capabilities. The current ability limits, power dissipation, device variability, etc. By
approaches to achieving logic functionality with MTJs include exploiting the spintronic effects in devices, it may be possible
designing an integrated CMOS and MTJ circuit, where CMOS
devices are used for implementing the required intermediate to overcome some of these challenges. For example, the
read and write circuitry. The problem with this approach is that properties of non-volatility and low-power consumption of
such intermediate circuitry adds overheads of area, delay and spintronic devices can bring power enhancements to CMOS-
power consumption to the logic circuit. In this paper, we present based designs. Therefore, it is necessary to investigate tech-
a circuit to accomplish logic operations using MTJs on data that niques and means to utilize the spintronics properties in
is stored in other MTJs, without an intermediate electronic
circuitry. This thus reduces the performance overheads of the computing circuits and evaluate their potential for improving
spintronic circuit while also simplifying fabrication. With this computer performance.
circuit, we discuss the notion of performing logic operations In previous works, MTJ-based memories have been fabri-
with a non-volatile memory device and compare it with the cated commercially as Magnetic Random Access Memories
traditional method of computation with separate logic and (MRAMs) [4]. In this type of memory, data is intrinsically
memory units. We find that the MTJ-based logic unit has the
potential to offer a higher energy-delay efficiency than that of stored as a spintronic state. Logic operations using MTJs
a CMOS-based logic operation on data stored in a separate have been demonstrated [5] and other components, such as
memory module. hybrid flip-flops [6], SRAMs [7] and adders [8] have been
designed, simulated and fabricated. These works have taken
I. I NTRODUCTION the critical first steps towards spintronic computation and
Traditionally, computing has been achieved through the demonstrated the capability of the MTJ devices for efficient
use of charge, a property of electrons that has single- logic operations. They have also established the advan-
handedly carried technology to unimaginable limits. So far, tages of including spintronic devices within logic modules.
little has been done to leverage the property of ‘spin’ of However, these designs include more electronic components
electrons. Currently substantial research efforts are being de- than spintronic components. This has been necessitated by
voted to develop our understanding and utilization of electron the requirement to read or sense the spintronic data as
spin for computing. The field of spin electronics, or ‘spin- an electronic signal and then to write it in MTJs using
tronics’, strives to exploit electron spins along with charges current signals. These intermediate circuits add integration
to increase the advantages obtained from electronic circuits. complexity, power consumption, area and delay overheads
In recent years, researchers have succeeded in developing to logic modules, and hence should be minimized to gain a
and using spintronic devices such as the magnetic tunnel full advantage of the spintronic technology.
junctions (MTJ). These devices operate on the principle To enable an efficient use of MTJs for logic functions,
of tunneling magnetoresistance (TMR), an effect seen at we examine the problem of performing logic operations
and below micro-scale dimensions ([1], [2]). This makes directly on data that is stored in an MTJ in the spintronic
them highly scalable, and hence high integration densities form, and investigate the possibility of avoiding the need for
are possible with MTJs [3]. Being ferromagnetic in nature, intermediate electronic circuitry to convert it into electronic
they are also capable of retaining their states in the absence signals. In this paper, we present a logic circuit to achieve
of power, which eliminates static power dissipation. These this objective. Without intermediate devices, the delay and
properties of MTJs have been leveraged to obtain dense, power consumption of the circuit is expected to reduce. A
low-power and non-volatile memory [4]. From the study significant feature of this circuit is its simplicity of operation
of MTJs so far, other properties that have been observed as well as fabrication.
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Fig. 1. Magnetic Tunnel Junction K& K!
input current (I) larger than or equal to threshold current (IC )
passing from the free layer to the fixed layer (top to bottom)
The proposed circuit demonstrates a spintronic logic cir-
magnetizes the free layer in a direction parallel to the fixed
cuit that can both store and process data. This dual capability
K&
provides for an opportunity to implement K! operations
logic
layer, and a reverse current magnetizes it in the opposite
direction. This method of controlling the magnetization of
inside a non-volatile memory & unit, thus reducing
! the com- 'the free layer is known as 34=8<>LMN
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munication overhead between logic and memory units. With
switching
J;F (CIMS). With this technique, the input to the MTJ
our circuit, we investigate the notion of accomplishing logic G
are currents +I or −I whichJ;F can be denoted as logic-1 and
using the MTJ devices within a single logic-and-memory
logic-0 respectively. The resistance of the device can be
unit, and compare it to the von Neumann approach of
measured by passing a small sense current (Isense ) through
computation with separate logic and memory units. We
the device.
! measure ' the delay and power consumption of a circuit that
The CIMS device operation has been leveraged for per-
accomplishes logic operations on data stored 34=8<>LMN
in a memory
forming logic operations and demonstrated in [5]. By con-
cell, implemented using CMOS-based circuits and the MTJ-
J;F
based proposed circuit. We show that a single GJ;Fbit operation
structing multiple current lines that act as inputs, the state of
an MTJ is controlled by the net current that passes through
using the MTJ-based logic setup shows an improved energy-
it. Fig. 2 shows an example of an MTJ accomplishing the
delay efficiency compared to a CMOS-based logic operation
NAND operation. The MTJ is preset to the logic-1 state.
configuration that reads data from a 180nm 256x3 memory
Inputs are currents of magnitude −I (logic-0) and +I (logic-
module and a 130nm 512x3 memory module.
1), with I = Ic /2. Logical inputs (0,0),(0,1) and (1,0) do
not affect the state of the MTJ. Only an input of (1,1)
II. T HE M AGNETIC T UNNEL J UNCTION (MTJ) D EVICE
generates a net current of +Ic through the MTJ that changes
The magnetic tunnel junction (Fig. 1(a)) is a sandwich the magnetization of the device to a logic-0 state, giving the
of two layers of ferromagnetic materials separated by a NAND truth table.
thin insulating barrier made of a metal oxide like AlO or Recent commercially developed Magnetic Random Access
MgO [9]. The two ferromagnetic layers, the free layer and Memories (MRAMs) utilize the CIMS technique to write
the fixed layer, are magnetized when the spins of their data to MTJ devices [17]. A CMOS-based write circuitry
electrons are all aligned in a single direction. With a parallel converts data voltage into appropriate signals that generate
relative orientation of the magnetization of the two layers, the directional currents through an MTJ. Reading of MTJ devices
resistance of the device (RP ) is lower than its resistance with is accomplished using CMOS-based sense amplifiers, in a
an anti-parallel relative orientation (RAP ). Thus, the device manner similar to reading any DRAM memory cell.
exhibits two distinct resistance values, low and high, which Sense amplifiers allow different bias requirements to be
are used to denote the digital states of logic-0 and logic-1. met easily, and hence using sense amplifiers for reading
Usually, the fixed layer is magnetized in one direction and spintronic memory is beneficial when MTJ-based storage
held constant by using additional layers. The magnetization devices are used within CMOS circuits that are performing
of the free layer is controlled externally to set the resistance computation. If the same concept is used for computation
of the device to a high or low value as desired. One way of of logic operations using MTJs themselves, the circuitry
controlling the free layer is by applying a magnetic field to would consist of intermediate electronic circuitry to convert
it. This technique is known as field-induced magnetization signals between the spintronic devices. A possible circuit
switching (FIMS). With the FIMS technique, programmable is shown in Fig. 3, where the sense amplifier senses the
logic has been demonstrated using MTJs [10]. This has resistance difference between the MTJ to be read (MTJ-A)
further led to the development of logic circuits such as a with a reference MTJ (MTJ-Ref) in a low state and outputs
full adder [11], 1-bit ALU [12] and 3-bit gray counter [13]. a voltage of 0V or +Vdd, which are then fed into a write
An improved technique of controlling the direction of the circuitry consisting of current mirror circuits that generate
free layer magnetization uses a recently discovered mech- the critical current for the logic-MTJ. Clearly, when it is
anism called spin torque transfer (STT)([14], [15], [16]). desired to perform simple logic operations on data stored in
With this effect, currents passing through an MTJ have been MTJs using MTJs themselves, this extra level of electronic
shown to magnetize the device. As shown in Fig. 1(b), an circuitry within the spintronic unit puts extra overheads on
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Logic Implementation Voltage requirement for
Operation (Set VMT J such that) delay of 1ns for
Fig. 3. Logic operation using an MTJ for data stored in two MTJs with MTJ fabricated in [18]
intermediate electronic circuitry for reading and writing data
NOR I > IC when both inputs are low 1.7V
NAND I > IC when either or both inputs are low 1.8V
OR I > IC when both inputs are low 2.5V
the circuit. This motivates the need for a simpler mechanism AND I > IC when either or both inputs are low 2.6V
that performs the function of a sense amplifier, but entirely
in the spintronics domain with as little extra circuitry as
possible. We address this requirement in this work. We operation, the current is greater than IC for the first three
present a logic circuit that senses or ‘reads’ the data in MTJs rows of the truth table, when either or both the inputs are
and computes the result of a logic operation in a third MTJ low. Thus, the same circuit performs both logic operations
with no intermediate electronic circuitry. We describe this at different bias voltages.
circuit in the next section. Fig. 4(b) shows a variation of the circuit where the current
passing through the logic-MTJ is in a direction from top to
III. C IRCUIT FOR L OGIC O PERATIONS USING MTJ S bottom. In essence, this can also be achieved by the circuit in
Noting that the inherent spintronic state of an MTJ is a Fig. 4(a) by simply interchanging the voltages on terminals
resistance, we propose a logic circuit that senses the net VMT J and Gnd. For the OR operation, the value of VMT J is
resistance of a circuit to generate a current through it. The adjusted such that the current flowing through the circuit is
circuit consists of three MTJs A, B and C connected as greater than IC only when MTJs A and B are low, while for
shown in Fig. 4(a) or Fig. 4(b). The inputs are stored as a the AND operation, bias voltage is such that the current is
spintronic state in MTJs A and B. The MTJ that performs the greater than IC for the first three rows. This is summarized
logic operation and stores its result within itself is MTJ-C. In in Table I.
Fig. 4(a) MTJ-C performs the NAND or NOR operation on
the data stored in input MTJs A and B. MTJ-C initially has a IV. V ERIFICATION AND FABRICATION
logic state of low, while input MTJs A and B have resistance- We simulated the circuit in Fig. 4(a) using a SPICE model
type data, i.e. a spintronic state corresponding to logic-0 or of the MTJ [19] for functional verification of the NOR
logic-1. Since the input devices are connected in parallel, the operation. MTJ device parameters reported for a fabricated
circuit current gets divided into the two branches without device [18] were used for the simulation: Rlow =3472 Ω,
subjecting any input device to critical current values. This Rhigh =5902 Ω, calculated IC =320uA for a device of size
ensures that the states of the ‘input’ MTJs remain unchanged 120nmx240nm. The bias voltage (VMT J ) calculated for the
through the operation. On applying bias voltage VMT J , the function of NOR, at a delay of 1ns, is 1.66V. Note that the
total current that flows through the circuit experiences the NOR operation can be obtained even for a lower voltage,
resistance of all three devices. If this happens to be above the albeit with a longer delay, while it can be obtained with a
critical value, it changes the state of the result MTJ (MTJ-C). smaller delay at a higher voltage.
The circuit current then experiences the new total resistance After applying a bias voltage of 1.7V to the circuit in
of the circuit and settles into a steady state. If the initial Fig. 4(a), Fig. 5 shows the resistance of the three devices
current is not above the critical current value, the result MTJ for four combinations of inputs. During NOR operation, the
retains its initial state. resistance of MTJ-C changes to a high state when MTJs
The value of VMT J controls the operation performed by A and B are in the low state. This occurs at about 300ps.
the circuit. For the NOR operation, this value is selected so Fig. 6(a) shows the circuit current for MTJ-A=MTJ-B=Rlow
that the current that flows through the circuit is greater than in the NOR circuit. The initial current is above the critical
IC only when MTJs A and B are low, while for the NAND value IC which changes the resistance of MTJ-C, and then
 !4 !4
[NOR opr] Resistance of MTJsA,B,C for A=0,B=0 [NOR opr] Resistance of MTJsA,B,C for A=0,B=1 x 10 x 10
3.5 3.4
6000 6000
MTJ!A MTJ!A 3.2
5500 MTJ!B 5500 MTJ!B

Resistance (ohms)
3
Resistance (ohms)

MTJ!C MTJ!C 3
5000 5000

Current (A)

Current (A)
2.8
4500 4500 2.5
2.6
4000 4000
2.4
3500 2
3500
2.2
3000 3000
0 0.5 1 1.5 2 0 0.5 1 1.5 2 1.5 2
Time (s) !9 Time (s) !9 0 0.5 1 1.5 2 0 0.5 1 1.5 2
x 10 x 10
Time (s) !9
x 10 Time (s) !9
x 10
[NOR opr] Resistance of MTJsA,B,C for A=1,B=1
[NOR opr] Resistance of MTJsA,B,C for A=1,B=0
6000
6000
MTJ!A
(a) Circuit Current for A=0, B=0 in (b) Circuit Current for A=0,B=1 in
MTJ!A
5500 MTJ!B
5500 MTJ!B NOR circuit (VMT J = 1.7V ) NAND circuit (VMT J = 1.8V )

Resistance (ohms)
Resistance (ohms)

MTJ!C MTJ!C
5000 5000

4500 4500

4000 4000 Fig. 6. Current in the MTJ-based logic circuit obtained from simulation
3500 3500

3000 3000
0 0.5 1 1.5 2 0 0.5 1 1.5 2
Time (s)
x 10
!9 Time (s) !9
x 10

Fig. 5. (Color online) SPICE simulation for functional verification for the
NOR operation with bias voltage=1.7V. Resistance (ohms) of MTJs A, B
and C shown vs Time (s).

settles into a steady state with a magnitude lesser than IC .

The waveforms also show that the current that flows through
individual branches of input MTJs does not change their
state.
The same circuit (Fig. 4(a)) can be used for NAND
operation when a bias voltage (VMT J ) of 1.8V is applied. Fig. 7. Optical Image of fabricated circuit
This bias voltage is large enough to generate a current more
than IC for the first three rows of the truth table. The circuit
current settles into a steady state after the NAND operation, power consumption of the circuit are influenced by the bias
as shown in Fig. 6(b). voltage requirement and the critical current density. As the
For the AND and OR operations, MTJ-C is initially preset critical current density decreases, the power requirements for
to a high resistance state. A bias voltage of 2.5V is required the logic operation decrease. A great amount of research
for accomplishing the OR function, while a bias voltage of aimed at reducing the critical current density of magnetic
2.6V is required for the AND operation. This can either be tunnel junctions is currently underway. In only three years of
accomplished by the circuit in Fig. 4(b) or by the circuit in prototyped devices (2005-2007), the critical current density
Fig. 4(a) by interchanging the terminals of VMT J and Gnd. has decreased from 16MA/cm2 to 1MA/cm2 , a factor of
Thus, in general, the circuit in Fig. 4(a) is programmable almost 16X ([21], [22], [23], [18]). The device reported in
for the four logic operations by applying suitable voltages to [18] with a critical current density of 1MA/cm2 is a dual
the two terminals. The differences in bias voltages depend on barrier structure specially designed to reduce the critical
the TMR ratio of the devices. This is the ratio (RH −RL )/RL . switching current, while behaving as a standard MTJ. With
The higher the ratio, the greater the difference between the the parameters of the devices fabricated and characterized in
voltages required for different logic operations, and hence the the three years, we calculated the bias voltage requirements
greater the noise or process variations that can be tolerated for the NOR, NAND, OR and AND operations for the
by the circuit. proposed circuit. These are shown in Fig. 8. With fabrication
To demonstrate the idea of the proposed circuit, we of smaller MTJs, these voltages decrease proportionally with
fabricated and verified this 3-MTj circuit. Fig. 7 shows the the area reduction. The bias voltage requirements for the
optical image of the fabricated circuit on a chip. More details MTJ device fabricated in [18] (120nm×240nm device with a
and characterization measurements are presented in [20]. critical current density of 1MA/cm2 ) are comparable to those
of the 180nm and 130nm CMOS technologies. Thus, the
V. E XPECTED TRENDS IN CRITICAL PARAMETERS
proposed MTJ circuit operates on practical voltage values.
An important consideration for a logic circuit in terms of
performance is its delay and power. The delay of the circuit is VI. I MPACT ON COMPUTING
primarily governed by the magnitude of the switching current The proposed circuit offers some interesting and novel
(I) flowing through the MTJ which is generated due to the possibilities for computation. Without the need for interme-
bias voltage (VMT J ), while the power consumption is based diate electronic circuitry, the circuit provides the potential to
on the bias voltage and the current through the circuit (I). perform logic operations within a non-volatile memory unit,
The bias voltage applied for the NOR and NAND operation using the memory devices themselves. This capability is a
is calculated as a direct function of the critical current density critical advantage over the conventional von Neumann ap-
Jc of the fabricated devices. Thus, both the delay and the proach to computing, where the logic units and memory units
 Ref NOR NAND OR AND
CMOS-180nm 1.8 1.8 1.8 1.8
CMOS-130nm 1.6 1.6 1.6 1.6
MTJ[18] 1.65 1.79 2.42 2.56 grandis 2007
MTJ[21] 1.30 1.45 2.22 2.37 aist 2005
MTJ[22] 1.67 1.84 2.67 2.85 ohno 2006
MTJ[23] 2.00 2.29 4.06 4.35 grandis 2006

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performing the four logic operations of NAND, NOR, AND
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operands and the result of the logic operation is functionally
equivalent to a 3-cell SRAM circuit performing a logic
Fig. 8. Bias voltage requirements for logic operations of NOR, NAND, operation using a logic gate, except that the spintronic im-
OR, AND in fabricated devices
plementation is also non-volatile. However, for CMOS-based
EDP SRAM circuits, the read and write delay also depends on the
2.93E-21
7.71E-21
are separated because the same circuits cannot achieve both number of cells connected to a single bit line. Performance
7.21E-22
functions simultaneously. Working around this constraint of
2.02E-21 of the SRAM configuration degrades as the number of cells
1.95E-21
CMOS-based devices, the concept of logic-in-memory with increases. The number of cells in the cell array depends on
von Neumann architectures has been researched extensively, the design of the memory unit and the requirements of the
A/cm^2
in which
Jc theohm
RLprocessor
ohm
RH is broughtIc closerNOR_R
to memory in order
NAND_R
overall system in which it resides. In order to incorporate this
2.20E+06
to reduce the 2.20E+03 5.61E+03
processor-memory 0.000605 3.30E+03
communication 3.78E+03
bottleneck. effect of CMOS circuits, we built an n-bit SRAM cell array
1.10E+06 3.47E+03 5.90E+03 0.0003168 5.21E+03 5.66E+03
Such 8.70E+06 1.00E+03
processor-in-memory 1.90E+03 0.0011136
architectures 1.50E+03
have shown 1.66E+03
signif- during evaluation. We scale the number of cells per bit line
1.60E+07 2.70E+02 5.60E+02 0.0032 4.05E+02 4.52E+02
icant performance benefits for data-centric applications like (or array size) to show the trade-off points of performance
image processing, signal processing, etc. ([24], [25]). With a between MTJ and SRAM circuits.
device capable of simultaneous storage and logic operations, We simulated this SRAM-based circuit in HSPICE using
the memory element itself becomes a processor, and the CMOS devices from 180nm and 130nm technologies, and
overhead of communication further decreases. measured the power and delay of a single-bit operation.
In a general-purpose computing system, data resides in The bias voltage (Vdd) used for the 180nm and 130nm
non-volatile memory elements like hard drives, flash memory simulations was 1.8V and 1.6V, respectively. We make the
cells, etc. Since these are relatively slow compared to the fast assumption that data is already present in the input SRAM
computing circuits, data is brought closer to the processor cells. Being volatile in nature, the SRAM cells consume
using an intermediate hierarchy of volatile memory elements power just for retention of the data before and after the logic
consisting of CMOS-based DRAM cells and SRAM cells operation. However, we ignore this power consumption.
in order to reduce the communication costs and increase The MTJ-based circuit in Fig. 4(a) is used to determine
performance. The complexity of such a setup could be the current through the circuit for the time of a clock cycle.
potentially alleviated by using a logic-and-memory circuit Since an MTJ circuit must be isolated from the rest of
for simple logic functions. To investigate the impact of this the circuitry in order to have a minimal connected path
idea, we compare the energy and delay measurements of for current to flow through so that the power consumption
a CMOS-based logic operation setup with the MTJ-based is minimized, we simulated a single 3-MTJ circuit. It is
logic circuit. We use device parameters related to the recent assumed that the result MTJ is already preset to logic-
technology status for both technologies. 0 before the operation commences. We will discuss this
The delay and power consumption of a single logic gate assumption further in Section VI-C.
using the CMOS technology is lower than the MTJ-based The CMOS-based circuit is simulated with minimal sized
logic circuit using devices fabricated in the laboratory so devices. Each SRAM cell is implemented as a 6T circuit. A
far. However, a complete data path for a logic operation with single logic-and-memory MTJ-based circuit clearly provides
the CMOS technology on stored data includes the memory area advantages over a separate logic and memory module
elements that contain input data and those that contain the using CMOS-based circuits. This area advantage is further
result of the operation. To compare against the non-volatile enhanced by the scalability possible with the spintronic tech-
MTJ memory cells performing a single logic operation on nology. We do not quantify the area advantages in this paper,
stored data, we choose the faster but volatile CMOS-based instead focus on the power and delay performance of the
SRAM cells as memory elements that contain the input data MTJ-based spintronic technology to get an insight into the
and will store the result of the operation. We next describe potential of the technology to improve circuit performance.
the experimental set up for the evaluation.
B. Results: Power-Delay Product (PDP) and Energy-Delay
A. Experimental Methodology Product (EDP)
A CMOS-based circuit performing the NAND function on The power consumption of the MTJ circuit is given by
data stored in SRAM devices is shown in Fig. 9. The 1-bit V.Iavg for the length of a high clock cycle. Since the bias
input operands are stored in two SRAM cells (shaded in the voltage for the spintronic device is computed for a delay of
figure), which feed into a simple ALU circuit capable of 1ns, we apply a clock high time of 2ns and compute the
 256cell 7.71E-21 256cell 7.7134
MTJ [10] 1.95E-21 MTJ [18] 1.9464
256cell 7.21E-22 256cell 0.7211
512cell 2.02E-21 512cell 2.0194
MTJ [10] 1.95E-21 MTJ [18] 1.9464

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Fig. 11. Comparison of the Energy-Delay Product of 180nm CMOS-based
EDP
SRAM circuit EDP EDP
and the MTJ devices reported EDP
in [18]
CMOS-180nm '# 19.2480 CMOS-180nm-128cell 2.9300
CMOS-130nm 2.0210 CMOS-130nm-512cell 2.0210
MTJ [2] &# 1.9464 MTJ [2] 1.9464
3-
8.9:;<=>?;1
C. Note &# additional supporting circuitry
on

!"#$%&'()%,*'++$
PDP 180nm CMOS 130nm CMOS 3, ("5
%(#
128cell 8.58E-13 3@A@<=13>B;CAD
256cell 1.77E-12 In order%# to develop into a complete logic-and-memory
MTJ [18] 9.73E-13 %#
256cell
Fig. 9. CMOS-based circuit 5.01E-13
for logic operations on data stored in volatile
module,
%!# there are three fundamental functions required of
512cell 1.08E-12
SRAM
MTJ [18]cells 9.73E-13
each MTJ$# in the unit: read, write and logic. When data is

!"#$%&$'()%,*'++$
$#
present
$(# in the devices, these three functions occur inherently
!#
&"!!#'(&% in the proposed circuit during
:2;<=$+!-.=$%+/011#
a logic operation
:2;<=$&!-.=($%/011# 789#
(the circuit
234#5%6#
(",!#'(&%
("+!#'(&%
current
$!# is established after ‘reading’ the inputs – this current

("*!#'(&% (&,3455% causes a ‘write’ in the result-MTJ). When data is not already
("&!#'(&% &6+3455% present in the devices, an external read and write is neces-
!"!#

("!!#'(&% 078%9(,:%
,"!!#'()% &6+3455%
sary. To add a read/write capability to the present circuit,
+"!!#'()% 6(&3455% simple switches would be required to establish a read/write
*"!!#'()% 078%9(,:% path. These switches would also allow the circuit to toggle
&"!!#'()%
!"!!#$!!% between the logic mode and the memory mode.
$, $- +,
(,!-.%/012%
("5
()!-.%/012% The proposed circuit also requires a ‘preset’ mode for the
result MTJ before applying inputs. In a CMOS analogy, this
Fig. 10. Comparison of the Power-Delay Product of 180nm CMOS-based is similar to the requirement of precharging the bit lines of a
SRAM circuit and the MTJ devices reported in [18] memory module before applying read or write signals. In the
proposed circuit, a preset may be achieved through external
write circuitry in a separate and necessary time step before a
power consumption for that period. This ensures that the logic step. Another way is by applying a suitable voltage to
operation is reliably completed. the present circuit that will set the state of the result MTJ to
The CMOS-based operation consists of read, write, trans- the desired value irrespective of the states of the input MTJs.
fer and the logic operation. We measure the power and delay However, to prevent the current due to this ‘preset’ voltage
of the entire operation including the reading of operands, the from affecting the states of the input MTJs, the circuit must
logic function and the writing of the result. We ignore the de- include an additional MTJ (‘preset’ MTJ) in parallel with the
lay and power consumed during the transfer of data through input MTJs. Since the proposed circuitry inherently writes to
communication lines between memory module and the ALU. the result-MTJ, the preset state will be written to the result
Fig. 10 shows the PDP comparisons between the CMOS MTJ while the preset-MTJ protects the input data.
and MTJ technologies with our simulation parameters. The Alternatively, techniques to amortize the overhead of the
data points show the trade-off points of performance of the preset may be used. Though beyond the scope of this paper, it
MTJ-based circuit with respect to 180nm and 130nm CMOS may be possible to preset an entire unit of MTJ-based logic-
technologies. The PDP of a logic operation using device and-memory cells by using separate magnetic or spintronic
parameters of 120nmx240nm MTJs falls between that of a means. For example, with a current plane above the array of
180nm CMOS-based logic setup with 128 cells and 256 cells result-MTJs, a current may be passed through the plane to
connected to a single bitline in a memory array. With 130nm magnetize the free layers of the entire row of result-MTJs at
technology, the PDP of the MTJ-based logic operation falls once.
between that of a CMOS-based memory array with 256
cells and 512 cells per bitline. The energy-delay product is VII. C ONCLUSION
an indicator of the energy-efficiency of the logic operation. In this work, we demonstrated an MTJ-based spintronic
The EDP for the CMOS and MTJ circuit configurations circuit that enables a magnetic tunnel junction to perform a
is shown in Fig. 11. For the 180nm technology, though logical operation on the spintronic states stored in two other
the performance of the MTJ is between the CMOS circuit MTJs. It eliminates the need to convert the spintronic states
configurations, the EDP of the MTJ circuit is better than both into an intermediate voltage or current signal with interme-
the CMOS circuits. diate CMOS-based circuitry. The circuit can be used most
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