ELEC 326: Digital Logic Design

Kartik Mohanram
Dept. of Electrical and Computer Engineering
Rice University

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 ELEC 220 background (lectures 1-7)

„ Bits, data types, arithmetic, etc.

„ Transistors, MOSFETs, logic gates
„ Transistor-level diagrams and circuit schematics
„ Logic design with gates, Boolean equivalence
„ Adders
„ Memory types
„ Combinational vs. sequential, latches, flip-flops
„ Finite state machines
„ Logic simplification, Karnaugh maps

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Design metrics

„ How to evaluate performance of a digital circuit

(gate, block, …)?
„ Scalability
„ Cost
„ Speed (delay, operating frequency)
„ Power dissipation
„ Energy to perform a function
„ Reliability

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 Understanding technology scaling

„ Moore’s law
„ If transistor count is an acceptable metric of
processing power
„ Number of transistors that can be crammed into
the same real estate will double every 24 months
„ More an industry driver
„ Semiconductor technology will double its
effectiveness every 18 months
„ The key (in some sense) to this is technology scaling

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A rough timeline – what’s missing?

© Intel Corp.

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 Pictorially

„ http://www.intel.com/technology/mooreslaw/index.htm

© Intel Corp.
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Processor frequency

10000
Doubled every
1000
2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year

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 Processor power

100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

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What’s missing

„ We know now that the trend did top-out?

„ Why?
„ To understand this, we need to look at
„ Die size and
„ Process technology used for fabrication
„ Why is this information important?
„ Broader question
„ How does one evaluate technology alternatives?
„ First-order circuit analysis when we get to

transistors

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 Technology scaling

„ What do the words 0.5 micron, 0.35 micron, 0.25

micron, 0.18 micron, … mean to you
„ Do you see a rough trend in this series?
„ This sqrt(2) shrinking in successive generations is
termed technology scaling
„ Usually attributed to the minimum feature size used
for fabrication
„ Where are we now?

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Why scaling?

„ Technology shrinks by 0.7/generation

„ With every generation can integrate 2X more
functions per chip; chip cost does not increase
significantly
„ Cost of a function decreases by 2X
„ But …
„ How to design chips with more and more functions?
„ Design engineering population does not double every
two years…
„ Hence, a need for more efficient design methods
„ Exploit different levels of abstraction

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 Processor power density

10000
Power Density (W/cm2) Rocket
Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

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The Pentium M: A case study

„ First generation Pentium M

„ Codename Banias
„ 0.13 micron technology
„ 1.3 to 1.7 GHz
„ L2 cache 1 MB
„ Power 24 Watts
„ Transistor count 77 million
„ Die size 82 mm2

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 Banias die photograph

© Intel Corp.

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Second generation Pentium M

„ Codename Dothan
„ 0.09 micron technology
„ 1.7 to 2.0 GHz
„ L2 cache 2 MB
„ Power 21 Watts
„ Transistor count 140 million
„ Die size 87 mm2
„ Let’s analyze these numbers and see if they
conform to technology scaling

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 Types of memory

„ RAM – Random access memory

„ SRAM – Static RAM
„ Microprocessor caches
„ Fast, burns more power
„ Standard design used 6 transistors per cell
„ So, 1 MB of on-chip cache requires ? Transistors
„ What about with ECC (Error Correcting Codes)
„ SDRAM – Synchronous dynamic RAM
„ Off-chip memory
„ Usually used in DIMMs (dual inline memory module)
„ RDRAM, DDR SDRAM, etc. are all flavors of DRAMs

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Side-by-side comparison

„ Dothan die
„ Not to scale, but let’s eyeball it anyway

© Intel Corp.

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 Multi-core dies

„ AMD’s Opteron-based ones

„ Intel’s Montecito
„ Next generation dual-core chip in the Itanium
family
„ McKinley -> Madison -> Montecito
„ Madison – single-core Itanium
„ 0.13 micron technology

„ 9 MB cache memory

„ 432 mm , approx 592 million transistors

2

„ Assignment: Estimate ball-park transistor count

for the Montecito die on next slide

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Montecito die photograph

© Intel Corp.
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 Challenges

„ Deep sub-micron (DSM) or sub-100nm

technologies
∝ DSM ∝ 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Variability • Reuse & IP: Portability
• Reliability, Manufacturability • Predictability
• Power Dissipation • etc.
• Clock distribution

Everything Looks a Little Different …and There’s a Lot of Them!

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