Application Note 4

September 1984

Applications for a New Power Buffer

Jim Williams

A frequent requirement in systems involves driving Buffered Output Line Driver

analog signals into non-linear or reactive loads. Cables,
Figure 1 shows the LT1010 placed within the feedback
transformers, actuators, motors and sample-hold circuits
loop of an operational amplifier. At lower frequencies, the
are examples where the ability to drive difficult loads is
buffer is within the feedback loop and its offset voltage and
required. Although several power buffer amplifiers are
gain error are negligible. At higher frequencies, feedback
available, none have been optimized for driving difficult
is through CF so that phase shift from load capacitance
loads. The LT®1010 can isolate and drive almost any acting against the buffer’s output resistance does not
reactive load. It also offers current limiting and thermal
cause loop instability.
overload protection which protect the device against output
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
fault conditions. The combination of good speed, output Technology Corporation. All other trademarks are the property of their respective owners.
protection, and reactive load driving capability (see box
section, “The LT1010 at a Glance”) make the device useful
in a variety of practical situations. UPDATE
Higher speed buffers are available
on new monolithic processes

RF
20k

CF
68pF
RIN
20k –
INPUT
LM101A LT1010 OUTPUT
+ AN04 F01

30pF

Figure 1. Practical LT1010 Based Boosted Op Amp

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AN4-1
Application Note 4
Figure 2 shows this configuration driving a 50Ω-0.33μF Fast, Stabilized Buffer Amplifier
load. The waveform is clean, with controlled damping. With
Figure 4 shows a way to eliminate this restriction, while
C load increased to a brutal 2μF, the circuit is still stable
maintaining good DC characteristics. Here, the LT1010 is
(Trace A, Figure 3), even though the large capacitance
combined with a wideband gain stage, Q1-Q3, to form a
requires substantial current (Trace B) from the LT1010.
fast inverting configuration. The LT1008 op amp DC sta-
Adjustment of the RF-CF time constant would allow im-
bilizes this stage by biasing the Q2-Q3 emitters to force a
proved damping.
zero DC potential at the circuit’s summing junction. The
Although this circuit is useful, its speed is limited by the roll-offs of the fast stage and the op amp are arranged to
op amp. provide smooth overall circuit response.

A = 5V/DIV
A = 2V/DIV

B = 200mA/DIV

AN04 F02 AN04 F03

HORIZONTAL = 20μs/DIV HORIZONTAL = 50μs/DIV

Figure 2 Figure 3

15V
1N4148
1k Q1
INPUT 2N5486
3.9k 300Ω 10pF

10k 0.01μF
Q2
2N2905 100pF
3.3k
2 4.7k
–
6 –15V 68k
22pF LT1008 1k
3
+ 8 4.7k 0.01μF LT1010 OUTPUT
100pF
Q3
2N2219 BIAS
22Ω

15V
3.9k 300Ω 10pF
CHARACTERISTICS
FULL POWER = 1MHz
1N4148 SETTLING = 5μs/0.01%
SLEW = 100V/μs
AN04 F04

–15V

Figure 4. Fed Forward. Wideband DC-Stabilized Buffer

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AN4-2
 Application Note 4
Because the circuit’s DC stabilization path occurs in parallel ends into the LT1010. The capacitively terminated feedback
with the buffer, higher speed is obtainable. Figure 5 shows divider gives the circuit a DC gain of 1, while allowing AC
the circuit driving a 600Ω-2500pF load. Despite the heavy gains up to 10. Using a 20Ω bias resistor (see box section),
load, the output (Trace B) does a good job of following the the circuit delivers 1VP-P into a typical 75Ω video load. For
input (Trace A) at a gain of –1. applications sensitive to NTSC requirements, dropping the
bias resistor value will aid performance.
Video Line Driving Amplifier
At A = 2, the gain is within 0.5dB to 10MHz with the
In many applications, DC stability is unimportant and –3dB point occurring at 16MHz. At A = 10, the gain is
AC gain is required. Figure 6 shows how to combine the flat (±0.5dB to 4MHz) with a –3dB point at 8MHz. The
LT1010’s load handling capability with a fast, discrete gain peaking adjustment should be optimized under loaded
stage. Q1 and Q2 form a differential stage which single output conditions.

A = 10V/DIV

B = 10V/DIV

AN04 F05
HORIZONTAL = 1μs/DIV

Figure 5

15V

8.2k 25Ω

+ BIAS
22μF +
22μF

LT1010 OUTPUT
(75Ω)

–15V
PEAKING
900Ω
5pF TO 25pF TYPICAL SPECIFICATIONS
INPUT Q1 Q2 1VP-P INTO 75Ω
AT A = 2
1k
Q1, Q2: 2N3866 0.5dB TO 10MHz
GAIN SET
3dB DOWN AT 16MHz
5.1k AT A = 10
+
0.01μF 68μF 0.5dB TO 4MHz
–15V –3dB = 8MHz

AN04 F06

Figure 6. Video Line Driving Amplifier

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Application Note 4
Figure 7 shows a video distribution amplifier. In this ex- Fast, Precision Sample-Hold Circuit
ample, resistors are included in the output line to isolate
Sample-hold circuits require high capacitive load driving
reflections from unterminated lines. If the line characteris-
capability to achieve fast acquisition times. Additionally,
tics are known, the resistors may be deleted. To meet NTSC
other trade-offs must be considered to achieve a good
gain-phase requirements, a small value boost resistor is
design. The conceptual circuit of Figure 8 illustrates some
used. Each 1VP-P channel output is essentially flat through
of the issues encountered. Fast acquisition requires high
6MHz into a 75Ω load.
charge currents and dynamic stability, which the LT1010 can

15V

3Ω
BOOST
75Ω
LT1010

15V

3Ω

75Ω
LT1010

15V 1VP-P
VIDEO
OUTPUTS
INPUT
3Ω INTO 75Ω

75Ω
LT1010

15V

3Ω

75Ω
LT1010
AN04 F07

Figure 7. Video Distribution Amplifier

1k

330pF
–
2 ICHARGE
– LT1056 OUTPUT
6 RON
LT1056 LT1010 +
3
INPUT +
CPARASITIC
10k HOLD CAPACITOR
1000pF
AN04 F08

SAMPLE-HOLD
COMMAND

Figure 8. Conceptual Sample-Hold

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 Application Note 4
provide. To get reasonable droop rate, the hold capacitor Figure 9 shows a circuit which combines the LT1010 with
must be appropriately sized, but too large a value means some techniques to produce a fast, precise sample-hold
FET switch on-resistance will effect acquisition time. If very circuit. Q1 through Q4 constitute a very fast TTL compatible
low on-resistance FETs are used, the parasitic gate-source level shift. Total delay from the TTL input switching into
capacitance becomes significant and a substantial amount hold to Q6 turning off is 16ns. Baker clamped Q1 biases
of charge is removed from the hold capacitor when the Q3’s emitter to switch level shifter Q4. Q2 drives a heavy
gate is switched off. This charge removal causes the stored feedforward network, speeding Q4’s switching. This stage
voltage to abruptly change with the circuit is switched affords low aperture errors, while providing the necessary
into the hold mode. This phenomenon, called “hold step”, level shift for Q6’s gate. The hold step error due to Q6’s
limits accuracy. It can be combatted by increasing the parasitic gate-source capacitance is compensated for by
hold capacitor’s value, but then acquisition time suffers. Q5 and the LT318A amplifier (A3).
Finally, since a TTL compatible input is desirable, the FET
The amount of charge removed by Q6’s parasitic capaci-
requires a level shift. This level shift must provide adequate
tance is signal dependent (Q = CV). To compensate this
pinch-off voltage over the entire range of circuit inputs and
error, A2 measures the circuit output and biases the Q5
must also be fast. Delays will result in aperture errors,
switch. Each time the circuit switches into hold mode, an
introducing dynamic sampling inaccuracies.
appropriate amount of charge is delivered through the

1k

330pF
2
–
2 A2 6
– Q6
LT1056
OUTPUT
A1 6 2N4393 3
LT1056
LT1010 +
3
INPUT +
CPARASITIC
2k
1000pF

15V

S-H INPUT 39pF HP5082-2810 3k 1N4148 4.7k 1.5k

TTL
1 = SAMPLE
0 = HOLD 0.1
1k Q2 Q3
Q1 1000pF
2N2369 470 Q4 15pF 10k
20k 2N2369
1N4148 820 820
–15V

20pF –15V
13k
HP5082-2810
SPARE 5.1k
2.5V
LT1009

2
–
6 A3
LT318A
3
Q5 + AN04 F09
2N2222
3.5k

5k
COMP
TRIM

Figure 9. Fast Sample-Hold with Hold Step Compensation

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AN4-5
Application Note 4
potentiometer—15pF network in Q5’s emitter. The amount amplifier settling time and not capacitor charge time.
of charge is scaled to compensate for charge removal due Pertinent specifications include:
to Q6’s parasitic term. A3’s inverting input is biased so Acquisition time: 2μs to 0.01%
that negative supply shifts, which alter the charge removed
through C parasitic, are accounted for in the compensating Hold settling time: <100ns to 1mV
charge. Compensation is set by grounding the signal input, Aperture time: 16ns
clocking the S-H line and adjusting the potentiometer for
minimum disturbance at the circuit’s output. Motor Speed Control
Figure 10 shows the circuit at work. When the sample-hold The LT1010’s ability to drive difficult loads is exploited
input (Trace A, Figure 10) goes into hold, charge cancella- in Figure 13’s circuit. Here, the buffer drives a motor-
tion occurs and the output (Trace B) sees less than 250μV tachometer combination. The tachometer signal is
of hold step error within 100ns. Without compensation, fed back and compared to a reference current and the
the error would be 50mV (Trace B, Figure 11—Trace A is LM301A amplifier closes a control loop. The 0.47μF
the sample-hold input). capacitor provides stable compensation. Because the
Figure 12 shows the LT1010’s contribution to fast acquisi- tachometer output is bipolar, the speed is controllable in
tion. The circuit acquires a 10V signal in this photograph. both directions, with clean transitions through zero. The
Trace A is the sample-hold input. Trace B shows the LT1010’s thermal protection is particularly useful in this
LT1010 delivering over 100mA to the hold capacitor and application, preventing device destruction in the event
Trace C depicts the output value slewing and settling to of mechanical overload or malfunction.
final value. Note that the acquisition time is limited by

A = 5V/DIV

A = 5V/DIV A = 5V/DIV
B = 100mA/DIV

B = 10mV/DIV
AC-COUPLED B = 50mV/DIV
C = 5V/DIV

AN04 F10 AN04 F11 AN04 F12

HORIZONTAL = 500ns/DIV HORIZONTAL = 500ns/DIV HORIZONTAL = 500ns/DIV

Figure 10 Figure 11 Figure 12

TACH
100k + –
15V
0.47μF
470
15V
1k 100k 2 –
SPEED + –
CONTROL 6
LM301A LT1010
470
3 + 8
MOTOR
1
–15V 30pF
–15V
= 1N4002
MOTOR-GENERATOR = TRANSCOIL-1125-115
MOTOR = 12V/4500RPM
TACH SLOPE = 1.9V/1000RPM

Figure 13. Overload Protected Motor Speed Controller

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AN4-6
 Application Note 4
Fan-Based Temperature Controller decreases until A3 begins to oscillate. A2 provides isola-
Figure 14 shows a way to use the LT1010 to control a fan tion and gain and A4 drives the transformer to generate
motor’s speed to regulate instrument temperature. The fan high voltage for the fan. In this fashion, the loop acts to
employed is one of the new electrostatic types which has maintain a stable instrument temperature by controlling
very high reliability because it contains no wearing parts. the fan’s exhaust rate. The 100μF time constant across the
These devices require high voltage drive. When power is error amplifier pins is typical of such configurations. Fast
applied, the thermistor (located in the fan’s exhaust stream) time constants will produce audibly annoying “hunting” in
is at a high value. This unbalances the A3 amplifier-driven the servo. Optimal values for this time constant and gain
bridge, A1 receives no power, and the fan does not run. depend upon the thermal and airflow characteristics of
As the instrument enclosure warms, the thermistor value the enclosure being controlled.

163k*

1N4148

*1% METAL FILM

T1 = TRIAD F-131P 100μF
RT = Y.S.I. #44014
PIEZO FAN = PIEZO PRODUCTS, #B +
– 20k*
1N4148
A3
LM307 –15V
15k + 20k*

10k 0.1μF
TRIM FOR 2
+
–
60Hz
6 A1 A2 A4
LM301 0.68μF 1M LM307 LT1010 T1
3 PIEZO-FAN
–
+
10k 2.2k
SEC PRI RT
10k
15V
AN04 F14
10k 1k

Figure 14. Piezo-Electric Fan Servo

The LT1010 at a Glance

by R. J. Widlar
The schematic describes the basic elements of the buf- The scheme is not perfect in that the rate of rise of sink
fer design. The op amp drives the output sink transistor, current is noticeably less than for source current. This
Q3, such that the collector current of the output follower can be mitigated by connecting a resistor between the
never drops below the quiescent value (determined by bias terminal at V+, raising quiescent current. A feature
I and the area ratio of D1 and D2). As a result, the high of the final design is that the output resistance is largely
frequency response is essentially that of a simple follower, independent of the follower quiescent current or the
even when Q3 is supplying the load current. The internal output load current. The output will also swing to the
feedback loop is isolated from the effects of capacitive negative rail, which is particularly useful with single
loading in the output lead. supply operation.

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. AN4-7
Application Note 4

The buffer is no more sensitive to supply bypassing than In DC circuits, buffer dissipation is easily computed.
slower op amps as far as stability is concerned. The In AC circuits, signal wave shape and the nature of the
0.1μF disc ceramic capacitors usually recommended for load determine dissipation. Peak dissipation can be sev-
op amps are certainly adequate or low frequency work. eral times average with reactive loads. it is particularly
As always, keeping the capacitor leads short and using important to determine dissipation when driving large
a ground plane are prudent, especially when operating load capacitance.
at high frequencies.
Overload Protection
The buffer slew rate can be reduced by inadequate sup-
ply bypass. With output current changes much above The LT1010 has both instantaneous current limit and
100mA/μs, using 10μF solid tantalum capacitors on both thermal overload protection. Foldback current limiting
supplies is good practice, although bypassing from the has not been used, enabling the buffer to drive complex
positive to the negative supply may suffice. loads without limiting. Because of this, it is capable of
power dissipation in excess of its continuous ratings.
When used in conjunction with an op amp and heavily
loaded (resistive or capacitive), the buffer can couple into Normally, thermal overload protection will limit dissipa-
supply leads common to the op amp, causing stability tion and prevent damage. However, with more than 30V
problems with the overall loop. Adequate bypassing across the conducting output transistor, thermal limiting
can usually be provided by 10μF solid tantalum capaci- is not quick enough to ensure protection in current limit.
tors. Alternately, smaller capacitors could be used with The thermal protection is effective with 40V across the
decoupling resistors. Sometimes the op amp has much conducting output transistor as long as the load current
better high frequency rejection on one supply, so bypass is otherwise limited to 150mA.
requirements are less on this supply.
Drive Impedance
Power Dissipation When driving capacitive loads, the LT1010 likes to be
In many applications, the LT1010 will require heat sinking. driven from a low source impedance at high frequencies.
Thermal resistance, junction to still air, is 150°C/W for Some low power op amps are marginal in this respect.
the TO-39 package and 60°C/W for the TO-3 package. Some care may be required to avoid oscillations, espe-
Circulating air, a heat sink or mounting the TO-3 package to cially at low temperatures.
a printed circuit board will reduce thermal resistance. Bypassing the buffer input with more than 200pF will solve
the problem. Raising the operating current also works,
The LT1010 at a Glance but this can be done only on the TO-3 package.
+POWER The LT1010 Conceptual Schematic
BIAS (20Ω TO +POWER
INCREASES NEGATIVE SLEW RATE
WHILE RAISING QUIESCENT CURRENT V+
TO ~50mA D1 D2
INPUT LT1010 AN04 F15 BIAS
TO-39, TO-220
OR TO-3
– + I2
PACKAGE
A1 Q2
–POWER
15MHz BANDWIDTH Q1 INPUT
100V/μs SLEW RATE I1 R1
DRIVE ±10V INTO 75Ω OUTPUT
5mA QUIESCENT CURRENT
DRIVE CAPACITIVE LOADS > 1μF Q3
CURRENT/THERMAL LIMIT
4.5Vm40V SUPPLY RANGE V–
AN04 F16

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