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ICS2694
Integrated
Circuit
Systems, Inc.
Motherboard Clock Generator
Description Features
The ICS2694 Motherboard Clock Generator is an integrated • Low cost - eliminates multiple oscillators and Count
circuit using PLL and VCO technology to generate virtually all Down Logic
the clock signals required in a PC. The use of the device can be • Primary VCO has 16 Mask Programmable frequencies
generalized to satisfy the timing needs of most digital systems (normally CPU clock)
by reprogramming the VCO or reconfiguring the counter stages
which derive the output frequencies from the VCO’s. • Secondary VCO has 1 Mask Programmable frequency
(usually 96 MHz)
The primary VCO is customarily used to generate the CPU • Pre-programmed versions for typical PC applications
clock and is so labeled on the ICS2694. Pre-programmed • 10 Outputs in addition to the primary CPU clock
frequency sets are listed on page 6. These choices were made
• Capability to reconfigure counter stages to change the
to match the major microprocessor families. CPUSEL (0-3)
allow the user to select the appropriate frequency for the frequencies of the outputs via mask options
application. • Advanced PLL design
• On-chip PLL filters
Due to the filter in the phase-locked loop, the CPUCLK will • Very Flexible Architecture
move in a linear fashion from one frequency to a newly-
selected frequency without glitches. If a fixed CPUCLK value
is desired, CPUSEL (0-3) may be hard wired to the desired
address with STROBE tied high. (It has a pull-up.) For board
test and debug, pulling OUTPUTE to Ground will tristate all
the outputs.
Applications Pin Configuration
• CPU clock and Co-processor clock
• Hard Disk and Floppy Disk clock
• Keyboard clock
OUT2 1 24 OUT3
• Serial Port clock
OUT1 2 23 OUT4
• Bus clock OUT0 3 22 OUT5
• System counting or timing functions OUT9 4 21 OUT6
CPUCLK 5 20 OUT7 (CPUCLK/2)
ICS2694
VSS 6 19 OUT8
DVDD 7 18 AVDD
STROBE 8 17 XTAL2
CPUSEL0 9 16 XTAL1
CPUSEL1 10 15 AVSS
CPUSEL2 11 14 OUTPUTE
CPUSEL3 12 13 CLKIN
24-Pin DIP or SOIC
ICS2694RevA1094
ICS2694
Pin Description
PIN NUMBER NAME DESCRIPTION
1 OUT2 4mA Output.
2 OUT1 4mA Output.
3 OUT0 4mA Output
4 OUT9 4mA Output.
5 CPUCLK 4mA Output driven by Voltage Controlled Oscillator 1 (VC01). VC01 is controlled
by a 16 word ROM.
6 VSS Ground for digital portion of chip.
7 DVDD Plus supply for digital portion of chip.
8 STROBE Input control for transparent latches associated with CPU (0-3) which select one of
16 values for CPUCLK. Holding STROBE high causes the latches to be transparent.
9 CPUSEL0 LSB CPUCLK address bit.
10 CPUSEL1 CPUCLK address bit.
11 CPUSEL2 CPUCLK address bit.
12 CPUSEL3 MSB CPUCLK address bit.
13 CLKIN An alternative input for the reference clock. The crystal oscillator output and CLKIN
are gated together to generate the reference clock for the VCO’s. If CLKIN is used,
XTAL1 should be held high and XTAL2 left open. If the internal oscillator is used,
hold CLKIN high.
14 OUTPUTE Pulling this line low tristates all outputs.
15 AVSS Ground for analog portion of chip.
16 XTAL1 Input of internal crystal oscillator stage.
17 XTAL2 Output of internal crystal oscillator stage. This pin should have nothing connected
to it but one of the quartz crystal terminals.
18 AVDD Positive supply for analog portion of chip.
19 OUT8 4mA Output.
20 OUT7 4mA Output. (Usually assigned as CPUCLK/2 for co-processor use.)
21 OUT6 4mA Output.
22 OUT5 4mA Output.
23 OUT4 4mA Output.
24 OUT3 4mA Output.
ICS2694
Frequency Reference Power Supply Conditioning
The internal reference oscillator contains all of the passive The ICS2694 is a member of the second generation of dot clock
components required. An appropriate series-resonant crystal products. By incorporating the loop filter on chip and upgrad-
should be connected between XTAL1 (1) and XTAL2 (2). In ing the VCO, the ease of application has been substantially
IBM-compatible applications, this will typically be a improved over earlier products. If a stable and noise-free power
14.31818 MHz crystal, but fundamental mode crystals be- supply is available, no external components are required. How-
tween 10 MHz and 25 MHz have been tested. Maintain short ever, in some applications it may be judicious to decouple the
lead lengths between the crystal and the ICS2694. In order to power supply as shown in Figures 1 or 2. Figure 1 is the normal
optimize the quality of the quartz crystal oscillator, the input configuration for 5 volt only applications. Which of the two
switching threshold of XTAL1 is VDD/2 rather than the con- provides superior performance depends on the noise content of
ventional 1.4V of TTL. Therefore, XTAL1 may not respond the power supplies. In general, the configuration of Figure 1 is
properly to a legal TTL signal since TTL is not required to satisfactory. Figure 2 is the more conventional if a 12 volt
exceed VDD/2. Therefore, another clock input CLKIN (pin 13) analog supply is available, although the improved performance
has been added to the chip which is sized to have an input comes at a cost of an extra component; however, the cost of the
switching point of 1.4V. Inside the chip, these two inputs are discretes used in Figure 1’s are less than the cost of Figure 1’s
ANDED. Therefore, when using the XTAL1 and XTAL2, discrete components.
CLKIN should be held high. (It has a pull-up.) When using
CLKIN, XTAL1 should be held high. (It does not have a Since the ICS2694 outputs a large number of high-frequency
pull-up because a pull-up would interfere with the oscillator clocks, conservative design practices are recommended. Care
bias.) should be exercised in the board layout of supply and ground
traces, and adequate power supply decoupling capacitors con-
It is anticipated that some applications will use both clock sistent with the application should be used.
inputs, properly gated, for either board test or unique system
functions. By generating all the system clocks from one refer-
ence input, the phase and delay relationships between the
various outputs will remain relatively fixed, thereby eliminat-
ing problems arising from totally unsynchronized clocks inter-
acting in a system.
+5 +50
C1 C1
DVDD DVDD
.µ1F .µ1F
33 470
+5 AVDD +120 AVDD
R1 C2 C3 R1 D1 C2
VSS, AVSS VSS, AVSS
22µV .µ1F 4.7V .µ1F
Figure 1 Figure 2
ICS2694
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . VDD. . . . . . . . . . . . -0.5V to +7V
Input Voltage . . . . . . . . . . . . . . . . . . VIN . . . . . . . . . . . . -0.5V to VDD +0.5V
Output Voltage . . . . . . . . . . . . . . . . VOUT. . . . . . . . . . -0.5V to VDD +0.5V
Clamp Diode Current . . . . . . . . . . . VIK & IOK . . . . . . . ±30mA
Output Current per Pin . . . . . . . . . . IOUT . . . . . . . . . . . ±50mA
Operating Temperature . . . . . . . . . . TO . . . . . . . . . . . . . 0°C to + 150°C
Storage Temperature . . . . . . . . . . . . TS . . . . . . . . . . . . . -85°C to + 150°C
Power Dissipation . . . . . . . . . . . . . . PD . . . . . . . . . . . . . 500mW
Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that VIN and VOUT be constrained
to > = VSS and < = VDD.
DC Characteristics (0°C to 70°C)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Operating Voltage Range VDD 4.0 5.5 V
Input Low Voltage VIL VDD = 5V VSS 0.8 V
Input High Voltage VIH VDD = 5V 2.0 VDD V
Input Leakage Current IIH VIN = Vcc - 10 uA
Output Low Voltage VOL IOL = 4.0 mA - 0.4 V
Output High Voltage VOH IOH = 4.0 mA 2.4 - V
Supply Current IDD VDD = 5V, CPUCLK = 80 MHz - 55 mA
Internal Pull-up Resistors RUP * VDD = 5V, Vin = 0V 50 - k ohm
Input Pin Capacitance Cin Fc = 1 MHz - 8 pF
Output Pin Capacitance Cout Fc = 1 MHz - 12 pF
* The following inputs have pull-ups: OUTPUTE, STROBE, CPUSEL (0-3), CLKIN.
ICS2694
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
1. Xtal Frequency = 14.31818 MHz
2. All units are in nanoseconds (ns).
3. Rise and fall time is between 0.8 and 2.0 VDC.
4. Output pin loading = 15pF
5. Duty cycle is measured at 1.4V.
6. Supply Voltage Range = 4.5 to 5.5 volts
7. Temperature Range = 0°C to 70°C
SYMBOL PARAMETER MIN MAX NOTES
STROBE TIMING
Tpw Strobe Pulse Width 20 -
Tsu Setup Time Data to Strobe 10 -
Thd Hold Time Data to Strobe 10 -
FOUT TIMING
Tr Rise Time - 3 Duty Cycle 40% min. to 60% max.
Tf Fall Time - 3 at 80 MHz
- Frequency Error 0.5 %
- Maximum Frequency 135 MHz
Note:
Pattern -004 has rising edges of CPUCLK and CPUCLK/2 matched to ± 2 ns.
Tpw
STROBE
CPUSEL (0-3)
Tsu Thd
ICS2694
24-Pin DIP Package
Ordering Information
ICS2694N-XXX
Example:
ICS XXXX M -XXX
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
N=DIP (Plastic)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
ICS2694
LEAD COUNT 14L 16L 18L 20L 24L 28L 32L
DIMENSION L 0.354 0.404 0.454 0.504 0.604 0.704 0.804
SOIC Packages
Ordering Information
ICS2694M-XXX
Example:
ICS XXXX M -XXX
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
ICS2694
Another alternative for CPU CLOCK generation is the
ICS2694 Standard Patterns ICS2494-244 if the additional functions of the ICS2694 are
not needed in the application.
32 MHz 1 24 16 MHz
1.846 MHz 2 23 8 MHz
24 MHz 3 22 9.6 MHz ICS ICS2494-
ICS2694-004
6 MHz 4 21 14.318 MHz Part Number 244
CPUCLK 5 20 CPUCLK/2 Address FS3-0 Frequency
VSS 6 19 1.19 MHz (Hex) (MHz)
DVDD 7 18 AVDD
0 20
STROBE 8 17 XTAL2
1 24
CPUSEL0 9 16 XTAL1
CPUSEL1 10 15 AVSS 2 32
CPUSEL2 11 14 OUTPUTE 3 40
CPUSEL3 12 13 CLKIN 4 50
5 66.6
6 80
7 100
CPUSEL0-3 CPUCLK OUTPUT (Pin 5)
8 54
(Hex) (MHz)
9 70
0 2
0 90
1 10
B 110
2 20
C 25
3 24
D 33.3
4 25
E 40
5 32
F 50
6 33.33
7 40
Address MS1-0 Frequency
8 48 (Hex) (MHz)
9 50 0 16
10 54 1 24
11 66.67 2 50
12 68 3 66.6
13 80
14 100
15 16
Note: Pattern -004 has rising edges of CPUCLK and
CPUCLK/2 matched to ± 2 ns.
