ELEMENTS OF EMBEDDED SYSTEMS:

An embedded system is a combination of 3 things, Hardware Software Mechanical

Components and it is supposed to do one specific task only. A typical embedded system contains
a single chip controller which acts as the master brain of the system. Diagrammatically an
embedded system can be represented as follows:

FPGA/ASIC/DSP/SoC
Embedded
Microprocessor/controller
Firmware

Memory

Communication Interface

System
I/p Ports Core O/p Ports
(Sensors)
(Actuators)

Other supporting
Integrated Circuits &
subsystems

Embedded System

Real World

Embedded systems are basically designed to regulate a physical variable (such

Microwave Oven) or to manipulate the state of some devices by sending some signals to the
actuators or devices connected to the output port system (such as temperature in Air
Conditioner), in response to the input signal provided by the end users or sensors which are
connected to the input ports. Hence the embedded systems can be viewed as a reactive
system.

Page 1

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The control is achieved by processing the information coming from the sensors and user
interfaces and controlling some actuators that regulate the physical variable.
Keyboards, push button, switches, etc. are Examples of common user interface input
devices and LEDs, LCDs, Piezoelectric buzzers, etc examples for common user interface
output devices for a typical embedded system.The requirement of type of user interface
changes from application to application based on domain.
Some embedded systems do not require any manual intervention for their operation.
They automatically sense the input parameters from real world through sensors which are
connected at input port. The sensor information is passed to the processor after signal
conditioning and digitization. The core of the system performs some predefined operations
on input data with the help of embedded firmware in the system and sends some actuating
signals to the actuator connect connected to the output port of the system.
The memory of the system is responsible for holding the code (control algorithm and
other important configuration details). There are two types of memories are used in any
embedded system. Fixed memory (ROM) is used for storing code or program. The user
cannot change the firmware in this type of memory. The most common types of memories
used in embedded systems for control algorithm storage are
OTP,PROM,UVEPROM,EEPROM and FLASH
An embedded system without code (i.e. the control algorithm) implemented memory has
all the peripherals but is not capable of making decisions depending on the situational as well
as real world changes.
Memory for implementing the code may be present on the processor or may be
implemented as a separate chip interfacing the processor
In a controller based embedded system, the controller may contain internal memory for
storing code such controllers are called Micro-controllers with on-chip ROM, eg. Atmel
AT89C51.

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 The Core of the Embedded Systems: The core of the embedded system falls into any one
of the following categories.


General Purpose and Domain
 Specific Processors
 o Microprocessors

 o Microcontrollers

o Digital Signal Processors

 
 Programmable Logic Devices (PLDs)
 
 Application Specific Integrated Circuits (ASICs)

 
Commercial off the shelf Components (COTS)

GENERAL PURPOSE AND DOMAIN SPECIFIC PROCESSOR:

Almost 80% of the embedded systems are processor/ controller based.

The processor may be microprocessor or a microcontroller or digital signal processor,
depending on the domain and application.
Microprocessor:
A silicon chip representing a Central Processing Unit (CPU), which is capable of
performing arithmetic as well as logical operations according to a pre-defined set of
Instructions, which is specific to the manufacturer

In general the CPU contains the Arithmetic and Logic Unit (ALU), Control Unit and
Working registers

Microprocessor is a dependant unit and it requires the combination of other hardware like
Memory, Timer Unit, and Interrupt Controller etc for proper functioning.

Intel claims the credit for developing the first Microprocessor unit Intel 4004, a 4 bit
processor which was released in Nov 1971

· Developers of microprocessors.
Intel – Intel 4004 – November 1971(4-bit)
Intel – Intel 4040.
Intel – Intel 8008 – April 1972.
Intel – Intel 8080 – April 1974(8-bit).
Motorola – Motorola 6800.
Intel – Intel 8085 – 1976.
Zilog - Z80 – July 1976

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 Microcontroller:

A highly integrated silicon chip containing a CPU, scratch pad RAM, Special and
 General purpose Register Arrays, On Chip ROM/FLASH memory for program storage,
Timer and Interrupt control units and dedicated I/O ports
 
 Microcontrollers can be considered as a super set of Microprocessors


Microcontroller can be general purpose (like Intel 8051, designed for generic applications
 AVR from Atmel Corporation.
and domains) or application specific (Like Automotive
 Designed specifically for automotive applications)

  working,
Since a microcontroller contains all the necessary functional blocks for independent
they found greater place in the embedded domain in place of microprocessors
 
 Microcontrollers are cheap, cost effective and are readily available in the market
 
Texas Instruments TMS 1000 is considered as the world‟s first microcontroller

Microprocessor Vs Microcontroller:

Microprocessor Microcontroller
A silicon chip representing a Central Processing Unit A microcontroller is a highly integrated chip that
(CPU), which is capable of performing arithmetic as contains a CPU, scratch pad RAM, Special and
well as logical operations according to a pre-defined set General purpose Register Arrays, On Chip
of Instructions ROM/FLASH memory for program storage, Timer
and Interrupt control units and dedicated I/O ports
It is a dependent unit. It requires the combination of It is a self contained unit and it doesn’t require
other chips like Timers, Program and data memory external Interrupt Controller, Timer, UART etc for
chips, Interrupt controllers etc for functioning its functioning

Most of the time general purpose in design and Mostly application oriented or domain specific
operation
Doesn‟t contain a built in I/O port. The I/O Port Most of the processors contain multiple built-in I/O
functionality needs to be implemented with the help of ports which can be operated as a single 8 or 16 or 32
external Programmable Peripheral Interface Chips like bit Port or as individual port pins
8255
Targeted for high end market where performance is Targeted for embedded market where performance is
important not so critical (At present this demarcation is invalid)

Limited power saving options compared to Includes lot of power saving features
microcontrollers

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General Purpose Processor (GPP) Vs Application Specific Instruction Set Processor (ASIP)

 
General Purpose Processor or GPP is a processor designed for general computational tasks


GPPs are produced in large volumes and targeting the general market. Due to the high
 production, the per unit cost for a chip is low compared to ASIC or other specific
volume
 ICs


A typical general purpose processor contains an Arithmetic and Logic Unit (ALU) and Control
 Unit (CU)


Application Specific Instruction Set processors (ASIPs) are processors with architecture
and instruction set optimized to specific domain/application requirements like Network

processing, Automotive, Telecom, media applications, digital signal processing, control
 applications etc.

ASIPs fill the architectural spectrum
between General Purpose Processors and Application
 Specific Integrated Circuits (ASICs)


The need for an ASIP arises when the traditional general purpose processor are unable to meet the
 increasing application needs


Some Microcontrollers (like Automotive AVR, USB AVR from Atmel), System on
Processors etc are examples of Application Specific Instruction Set
Chips, Digital Signal
 Processors (ASIPs)

 and on-chip peripherals, demanded by the application requirement,
ASIPs incorporate a processor
program and data memory

Digital Signal Processors (DSPs):

Powerful special purpose 8/16/32 bit microprocessors designed specifically to meet the
computational demands and power constraints of today's embedded audio, video, and
communications applications

Digital Signal Processors are 2 to 3 times faster than the general purpose microprocessors
in signal processing applications

DSPs implement algorithms in hardware which speeds up the execution whereas general
purpose processors implement the algorithm in firmware and the speed of execution
depends primarily on the clock for the processors

DSP can be viewed as a microchip designed for performing high speed computational
operations for „addition‟, „subtraction‟, „multiplication‟ and „division‟

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 A typical Digital Signal Processor incorporates the following key units
 
 Program Memory
 
Data Memory

 
Computational Engine

 
I/O Unit

Audio video signal processing, telecommunication and multimedia applications are

typical examples where DSP is employed

RISC V/s CISC Processors/Controllers:

RISC CISC
Lesser no. of instructions Greater no. of Instructions
Instruction Pipelining and increased execution Generally no instruction pipelining feature
speed
Orthogonal Instruction Set (Allows each instruction Non Orthogonal Instruction Set (All instructions
to operate on any register and use any addressing are not allowed to operate on any register and
mode) use any addressing mode. It is instruction
specific)
Operations are performed on registers only, the Operations are performed on registers or
only memory operations are load and store memory depending on the instruction

Large number of registers are available Limited no. of general purpose registers
Programmer needs to write more code to execute a . A programmer can achieve the desired
task since the instructions are simpler ones functionality with a single instruction which in
turn provides the effect of using more simpler
single instructions in RISC
Single, Fixed length Instructions Variable length Instructions

Less Silicon usage and pin count More silicon usage since more additional
decoder logic is required to implement the
complex instruction decoding.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture

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Harvard V/s Von-Neumann Processor/Controller Architecture

The terms Harvard and Von-Neumann refers to the processor architecture design.

Microprocessors/controllers based on the Von-Neumann architecture shares a single

common bus for fetching both instructions and data. Program instructions and data are
stored in a common main memory

Microprocessors/controllers based on the Harvard architecture will have separate data

bus and instruction bus. This allows the data transfer and program fetching to occur
simultaneously on both buses

With Harvard architecture, the data memory can be read and written while the program
memory is being accessed. These separated data memory and code memory buses allow
one instruction to execute while the next instruction is fetched (“Pre-fetching”)

I/O CPU Memory

Program CPU Data Memory

Memory

Single shared Bus

Harvard V/s Von-Neumann Processor/Controller Architecture:

Harvard Architecture Von-Neumann Architecture

Separate buses for Instruction and Data fetching Single shared bus for Instruction and Data
fetching
Easier to Pipeline, so high performance can be Low performance Compared to Harvard
achieved Architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes†
Since data memory and program memory are Since data memory and program memory
stored physically in different locations, no are stored physically in same chip, chances
chances for accidental corruption of program for accidental corruption of program
memory memory

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Big-endian V/s Little-endian processors:


Endianness specifies the order in which the data is stored in the memory by processor
operations in a multi byte system (Processors whose word size is greater than one byte).
 the word length is two byte then data can be stored in memory in two different
Suppose
ways

Higher order of data byte at the higher memory and lower order of data byte at
location just below the higher memory

Lower order of data byte at the higher memory and higher order of data byte at
location just below the higher memory


Little-endian means the lower-order byte of the data is stored in memory at the lowest 
 address, and the higher-order byte at the highest address. (The little end comes first)


Big-endian means the higher-order byte of the data is stored in memory at the lowest address,
and the lower-order byte at the highest address. (The big end comes first.)

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Load Store Operation & Instruction Pipelining:

The RISC processor instruction set is orthogonal and it operates on registers. The memory access
related operations are performed by the special instructions load and store. If the operand is
specified as memory location, the content of it is loaded to a register using the load instruction.
The instruction store stores data from a specified register to a specified memory location

Instruction Pipelining

The conventional instruction execution by the processor follows the fetch-decode-

execute sequence

The „fetch‟ part fetches the instruction from program memory or code memory and
the decode part decodes the instruction to generate the necessary control signals

The execute stage reads the operands, perform ALU operations and stores the result.
In conventional program execution, the fetch and decode operations are performed in
sequence

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 During the decode operation the memory address bus is available and if it possible to
effectively utilize it for an instruction fetch, the processing speed can be increased

In its simplest form instruction pipelining refers to the overlapped execution of

instructions

Application Specific Integrated Circuit (ASIC):

A microchip designed to perform a specific or unique application. It is used as
replacement to conventional general purpose logic chips.

ASIC integrates several functions into a single chip and thereby reduces the system
development cost

Most of the ASICs are proprietary products. As a single chip, ASIC consumes very small
area in the total system and thereby helps in the design of smaller systems with high
capabilities/functionalities.

ASICs can be pre-fabricated for a special application or it can be custom fabricated by

using the components from a re-usable „building block‟ library of components for a
particular customer application

Fabrication of ASICs requires a non-refundable initial investment (Non Recurring

Engineering (NRE) charges) for the process technology and configuration expenses

If the Non-Recurring Engineering Charges (NRE) is born by a third party and the
Application Specific Integrated Circuit (ASIC) is made openly available in the market,
the ASIC is referred as Application Specific Standard Product (ASSP)

The ASSP is marketed to multiple customers just as a general-purpose product , but to a

smaller number of customers since it is for a specific application.

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 Some ASICs are proprietary products , the developers are not interested in revealing the
internal details.

Programmable Logic Devices (PLDs):


Logic devices provide specific functions, including device-to-device interfacing, data
communication, signal processing, data display,  timing and control operations, and
 almost every other function a system must perform.


Logic devices can be classified into two broad categories - Fixed and Programmable. The
circuits in a fixed logic device are permanent, they perform one function or set of
 functions - once manufactured, they cannot be changed


Programmable logic devices (PLDs) offer customers a wide range of logic capacity,
features, speed, and voltage characteristics -and these devices can be re-configured to
 perform any number of functions at any time


Designers can use inexpensive software tools to quickly develop, simulate, and test their
logic designs in PLD based design. The design can be quickly programmed into a device,
 and immediately tested in a live circuit


PLDs are based onre-writable memory technology and the device is reprogrammed to
change the design

Programmable Logic Devices (PLDs) – CPLDs and FPGA

Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices
(CPLDs) are the two major types of programmable logic devices

FPGA:
FPGA is an IC designed to be configured by a designer after manufacturing.

FPGAs offer the highest amount of logic density, the most features, and the highest
performance.

Logic gate is Medium to high density ranging from 1K to 500K system gates

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 These advanced FPGA devices also offer features such as built-in hardwired processors
(such as the IBM Power PC), substantial amounts of memory, clock management
systems, and support for many of the latest, very fast device-to-device signaling
technologies

Figure: FPGA Architecture

These advanced FPGA devices also offer features such as built-in hardwired processors,
substantial amounts of memory, clock management systems, and support for many of the
latest, very fast device-to-device signaling technologies.

FPGAs are used in a wide variety of applications ranging from data processing and
storage, to instrumentation, telecommunications, and digital signal processing

CPLD:

A complex programmable logic device (CPLD) is a programmable logic device with
complexity between that of PALs and FPGAs, and architectural features of both.

CPLDs, by contrast, offer much smaller amounts of logic - up to about 10,000 gates.

CPLDs offer very predictable timing characteristics and are therefore ideal for critical
control applications.

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 CPLDs such as the Xilinx CoolRunner series also require extremely low amounts of
power and are very inexpensive, making them ideal for cost-sensitive, battery-operated,
portable applications such as mobile phones and digital handheld assistants.

ADVANTAGES OF PLDs:

• PLDs offer customer much more flexibility during design cycle

• PLDSs do not require long lead times for prototype or production-the PLDs are already
on a distributor‟s self and ready for shipment

• PLDs do not require customers to pay for large NRE costs and purchase expensive mask
sets

• PLDs allow customers to order just the number of parts required when they need them.
allowing them to control inventory.

• PLDs are reprogrammable even after a piece of equipment is shipped to a customer.

• The manufacturers able to add new features or upgrade the PLD based products that are
in the field by uploading new programming file

Commercial off the Shelf Component (COTS):

A Commercial off-the-shelf (COTS) product is one which is used „as-is‟

COTS products are designed in such a way to provide easy integration and
interoperability with existing system components

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Typical examples for the COTS hardware unit are Remote Controlled Toy Car control
unit including the RF Circuitry part, High performance, high frequency microwave
electronics (2 to 200 GHz), High bandwidth analog-to-digital converters, Devices and
components for operation at very high temperatures, Electro-optic IR imaging arrays,
UV/IR Detectors etc

A COTS component in turn contains a General Purpose Processor (GPP) or Application

Specific Instruction Set Processor (ASIP) or Application Specific Integrated Chip
(ASIC)/Application Specific Standard Product (ASSP) or Programmable Logic Device
(PLD)

The major advantage of using COTS is that they are readily available in the market,
cheap and a developer can cut down his/her development time to a great extend.

There is no need to design the module yourself and write the firmware .

Everything will be readily supplied by the COTs manufacturer.

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 The major problem faced by the end-user is that there are no operational and
manufacturing standards.

The major drawback of using COTs component in embedded design is that the
manufacturer may withdraw the product or discontinue the production of the COTs at any
time if rapid change in technology

This problem adversely affect a commercial manufacturer of the embedded system which
makes use of the specific COTs

Memory:
Memory is an important part of an embedded system. The memory used in embedded
system can be either Program Storage Memory (ROM) or Data memory (RAM)

Certain Embedded processors/controllers contain built in program memory and data

memory and this memory is known as on-chip memory

Certain Embedded processors/controllers do not contain sufficient memory inside the

chip and requires external memory called off-chip memory or external memory.

Memory – Program Storage Memory:

 
 Stores the program instructions


Retains its contents even
after the power to it is turned off. It is generally known as Non
 volatile storage memory

 
Depending on the fabrication, erasing and programming techniques they are classified into

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 FLASH Code Memory NVRAM
(ROM)

PROM Masked ROM

EPROM EEPROM
(OTP) (MROM)

1. Masked ROM (MROM):

One-time programmable memory.

Uses hardwired technology for storing data.

The device is factory programmed by masking and metallization process according to

the data provided by the end user.

The primary advantage of MROM is low cost for high volume production.

MROM is the least expensive type of solid state memory.

Different mechanisms are used for the masking process of the ROM, like
 
 Creation of an enhancement or depletion mode transistor through channel implant


By creating the memory cell either using a standard transistor or a high threshold
 transistor.


In the high threshold mode, the supply voltagerequired to turn ON the transistor is
 above the normal ROM IC operating voltage.


 ensures that the transistor is always off and the memory cell stores always logic
This
0.

The limitation with MROM based firmware storage is the inability to modify the
device firmware against firmware upgrades.

The MROM is permanent in bit storage, it is not possible to alter the bit information

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2. Programmable Read Only Memory (PROM) / (OTP) :

It is not pre-programmed by the manufacturer

The end user is responsible for Programming these devices.

PROM/OTP has nichrome or polysilicon wires arranged in a matrix, these wires can be
functionally viewed as fuses.

It is programmed by a PROM programmer which selectively burns the fuses according to

the bit pattern to be stored.

Fuses which are not blown/burned represents a logic “1” where as fuses which are
blown/burned represents a logic “0”.The default state is logic “1”.

OTP is widely used for commercial production of embedded systems whose proto-typed
versions are proven and the code is finalized.

It is a low cost solution for commercial production.

OTPs cannot be reprogrammed.

3. Erasable Programmable Read Only Memory (EPROM):

Erasable Programmable Read Only (EPROM) memory gives the flexibility to re-program
the same chip.

During development phase , code is subject to continuous changes and using an OTP is
not economical.

EPROM stores the bit information by charging the floating gate of an FET

Bit information is stored by using an EPROM Programmer, which applies high voltage to
charge the floating gate

EPROM contains a quartz crystal window for erasing the stored information. If the
window is exposed to Ultra violet rays for a fixed duration, the entire memory will be
erased

Even though the EPROM chip is flexible in terms of re-programmability, it needs to be

taken out of the circuit board and needs to be put in a UV eraser device for 20 to 30
minutes

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4. Electrically Erasable Programmable Read Only Memory (EEPROM):

Erasable Programmable Read Only (EPROM) memory gives the flexibility to re-program
the same chip using electrical signals

The information contained in the EEPROM memory can be altered by using electrical
signals at the register/Byte level

They can be erased and reprogrammed within the circuit

These chips include a chip erase mode and in this mode they can be erased in a few
milliseconds

It provides greater flexibility for system design

The only limitation is their capacity is limited when compared with the standard ROM (A
few kilobytes).

5. Program Storage Memory – FLASH

FLASH memory is a variation of EEPROM technology.

FALSH is the latest ROM technology and is the most popular ROM technology used in
today‟s embedded designs

It combines the re-programmability of EEPROM and the high capacity of standard

ROMs

FLASH memory is organized as sectors (blocks) or pages

FLASH memory stores information in an array of floating gate MOSFET transistors

The erasing of memory can be done at sector level or page level without affecting the
other sectors or pages

Each sector/page should be erased before re-programming

The typical erasable capacity of FLASH is of the order of a few 1000 cycles.

Read-Write Memory/Random Access Memory (RAM)

 
 RAM is the data memory or working memory of the controller/processor
 
RAM is volatile, meaning when the power is turned off, all the contents are destroyed

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 
RAM is a direct access memory, meaning we can access the desired memory location
directly without the need for traversing through the entire memory
locations to reach the
desired memory position (i.e. Random Access of memory location)

Read/Write
Memory (RAM)

SRAM DRAM NVRAM

1. Static RAM (SRAM):

 
 Static RAM stores data in the form of Voltage.
 
They are made up of flip-flops


 cell (bit) is realized using
In typical implementation, an SRAM
 6 transistors (or 6 MOSFETs).


 
Four of the transistors are used for building the latch (flip-flop)
part of the memory cell and 2 for controlling the access.
 
 Static RAM is the fastest form of RAM available.
 
SRAM is fast in operation due to its resistive networking and switching capabilities

2. Dynamic RAM (DRAM)

 
Dynamic RAM stores data in the form of charge. They are made up of MOS transistor gates



The advantages of DRAM are its high density and low cost compared to
 SRAM


The disadvantage is that since the information is stored as charge it
gets leaked off with time and to prevent this they need to be
 refreshed periodically


Special circuits called DRAM controllers are used for  the refreshing operation. The refresh
operation is done periodically in milliseconds interval

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SRAM Vs DRAM:

SRAM Cell DRAM Cell

Made up of 6 CMOS transistors (MOSFET) Made up of a MOSFET and a capacitor

Doesn‟t Require refreshing Requires refreshing
Low capacity (Less dense) High Capacity (Highly dense)
More expensive Less Expensive
Fast in operation. Typical access time is 10ns Slow in operation due to refresh
requirements. Typical access time is 60ns.
Write operation is faster than read operation.

3. Non Volatile RAM (NVRAM):

 
 Random access memory with battery backup


  battery for providing supply to the
It contains Static RAM based memory and a minute
memory in the absence of external power supply
 
 The memory and battery are packed together in a single package


  is used for the non volatile storage of results of operations or for setting up of flags
NVRAM
etc
 
 The life span of NVRAM is expected to be around 10 years
 
DS1744 from Maxim/Dallas is an example for 32KB NVRAM

Memory selection for Embedded Systems:

• Selection of suitable memory is very much essential step in high performance
applications, because the challenges and limitations of the system performance are often
decided upon the type of memory architecture.

• Systems memory requirement depend primarily on the nature of the application that is
planned to run on the system.

• Memory performance and capacity requirement for low cost systems are small, whereas
memory throughput can be the most critical requirement in a complex, high performance
system.

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 • Following are the factors that are to be considered while selecting the memory devices,
 
 Speed
 
Data storage size and capacity

 
Bus width

 
Power consumption

 
Cost

Embedded system requirements:


 Program memory for holding  control algorithm or embedded OS and the applications
designed to run on top of OS.
 
 Data memory for holding variables and temporary data during task execution.
 
Memory for holding non-volatile data which are modifiable by the application.

The memory requirement for an embedded system in terms of RAM (SRAM/DRAM)

and ROM (EEPROM/FLASH/NVRAM) is solely dependent on the type of the embedded
system and applications for which it is designed.

There is no hard and fast rule for calculating the memory requirements.

Lot of factors need to be considered for selecting the type and size of memory for
embedded system.

Example: Design of Embedded based electronic Toy.

SOC or microcontroller can be selected based type(RAM &ROM) and size of on-chip
memory for the design of embedded system.

If on-chip memory is not sufficient then how much external memory need to be
interfaced.

If the ES design is RTOS based ,the RTOS requires certain amount of RAM for its
execution and ROM for storing RTOS Image.

The RTOS suppliers gives amount of run time RAM requirements and program memory
requirements for the RTOS.

Additional memory is required for executing user tasks and user applications.

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On a safer side, always add a buffer value to the total estimated RAM and ROM
requirements.

A smart phone device with windows OS is typical example for embedded device requires
say 512MB RAM and 1GB ROM are minimum requirements for running the mobile
device.

And additional RAM &ROM memory is required for running user applications.

So estimate the memory requirements for install and run the user applications without
facing memory space.

Memory can be selected based on size of the memory ,data bus and address bus size of
the processor/controller.

Memory chips are available in standard sizes like 512 bytes,1KB,2KB ,4KB,8KB,16 KB
….1MB etc.

FLASH memory is the popular choice for ROM in embedded applications .

It is powerful and cost-effective solid state storage technology for mobile electronic
devices and other consumer applications.

Flash memory available in two major variants

1. NAND FLASH 2. NOR FLASH

NAND FLASH is a high density low cost non-volatile storage memory.

NOR FLASH is less dense and slightly expensive but supports Execute in place(XIP).

The XIP technology allows the execution of code memory from ROM itself without the
need for copying it to the RAM.

The EEPROM is available as either serial interface or parallel interface chip.

If the processor/controller of the device supports serial interface and the amount of data
to write and read to and from the device (Serial EEPROM) is less.

The serial EEPROM saves the address space of the total system.

The memory capacity of the serial EEPROM is expressed in bits or Kilobits.

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 Industrial grade memory chips are used in certain embedded devices may be operated at
extreme environmental conditions like high temperature.

Sensors & Actuators:

• Embedded system is in constant interaction with the real world

• Controlling/monitoring functions executed by the embedded system is achieved in

accordance with the changes happening to the Real World.

• The changes in the system environment or variables are detected by the sensors
connected to the input port of the embedded system.

• If the embedded system is designed for any controlling purpose, the system will produce
some changes in controlling variable to bring the controlled variable to the desired value.

• It is achieved through an actuator connected to the out port of the embedded system.

Sensor:
A transducer device which converts energy from one form to another for any
measurement or control purpose. Sensors acts as input device

Eg. Hall Effect Sensor which measures the distance between the cushion and magnet in
the Smart Running shoes from adidas

Example: IR, humidity , PIR(passive infra red) , ultrasonic , piezoelectric , smoke

sensors

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Actuator:

A form of transducer device (mechanical or

electrical) which converts signals to
corresponding physical action (motion).
Actuator acts as an output device

Eg. Micro motor actuator which adjusts the

position of the cushioning element in the
Smart Running shoes from adidas

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The I/O Subsystem:


 facilitates the interaction of the
The I/O subsystem of the embedded system
 embedded system with external world



The interaction happens through the sensors and actuators connected to the
 Input and output ports respectively of the embedded system


The sensors may not be directly interfaced to the Input ports, instead
 conditioning and translating
they may be interfaced through signal
 systems like ADC, Optocouplers etc

1. I/O Devices - Light Emitting Diode (LED):

Vcc
Light Emitting Diode (LED) is an output device for visual

R
indication in any embedded system

LED can be used as an indicator for the status of various signals

or situations.

Typical examples are indicating the presence of power conditions

GND
like „Device ON‟, „Battery low‟ or „Charging of battery‟ for a
battery operated handheld embedded devices

LED is a p-n junction diode and it contains an anode and a cathode.

For proper functioning of the LED, the anode of it should be connected to +ve terminal
of the supply voltage and cathode to the –ve terminal of supply voltage

The current flowing through the LED must limited to a value below the maximum current
that it can conduct.

A resister is used in series between the power supply and the resistor to limit the current
through the LED

2. I/O Devices – 7-Segment LED Display

The 7 – segment LED display is an output device for displaying alpha numeric characters

It contains 8 light-emitting diode (LED) segments arranged in a special form. Out of the 8
LED segments, 7 are used for displaying alpha numeric characters

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 The LED segments are named A to G and the decimal point LED segment is named as
DP

The LED Segments A to G and DP should be lit accordingly to display numbers and
characters

The 7 – segment LED displays are available in two different configurations, namely;
Common anode and Common cathode

In the Common anode configuration, the anodes of the 8 segments are connected
commonly whereas in the Common cathode configuration, the 8 LED segments share a
common cathode line

Based on the configuration of the 7 – segment LED unit, the LED segment anode or
cathode is connected to the Port of the processor/controller in the order „A‟ segment to
the Least significant port Pin and DP segment to the most significant Port Pin.

The current flow through each of the LED segments should be limited to the maximum
value supported by the LED display unit

Anode Common Cathode LED Display

DP GFEDCB A

DPGF ED C B A
Common Anode LED Display Cathode

The typical value for the current falls within the range of 20mA

The current through each segment can be limited by connecting a current limiting resistor
to the anode or cathode of each segment

3. I/O Devices – Optocoupler

Optocoupler is a solid state device to isolate two parts of a circuit.

Optocoupler combines an LED and a photo-transistor in a single housing (package)

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 In electronic circuits, optocoupler is used for suppressing interference in data
communication, circuit isolation, High voltage separation, simultaneous separation and
intensification signal etc Vcc

LED AT89C51 LED

I/p interface Port Pin
O/p interface
Port Pin
Photo-transistor Photo-transistor

Opto-Coupler Microcontroller Opto-Coupler

IC MCT2M IC MCT2M

Optocouplers can be used in either input circuits or in output circuits

4. I/O Devices – Stepper Motor:

Stepper motor is an electro mechanical device which generates discrete
displacement (motion) in response to dc electrical signals

It differs from the normal dc motor in its operation. The dc motor produces
continuous rotation on applying dc voltage whereas a stepper motor produces discrete
rotation in response to the dc voltage applied to it

Stepper motors are widely used in industrial embedded

applications, consumer electronic products and robotics
control systems A
GND

M
The paper feed mechanism of a printer/fax makes use C
of stepper motors for its functioning.

Based on the coil winding arrangements, a two phase

B D
stepper motor is classified into
GND

 
 Unipolar
 
Bipolar

Page 27 of 111
 
Unipolar: A unipolar stepper motor contains two windings per phase. The direction of
rotation (clockwise or anticlockwise) of a stepper motor is controlled by changing the
direction of current flow. Current in one direction flows through one coil and in the
the direction of rotation
opposite direction flows through the other coil. It is easy to shift
 by just switching the terminals to which the coils are connected


Bipolar: A bipolar stepper motor contains single winding per phase. For reversing the
motor rotation the current flow through thewindings is reversed dynamically. It requires
 complex circuitry for current flow reversal

5. The I/O Subsystem – I/O Devices – Relay:

 
 An electro mechanical device which acts as dynamic path selectors for signals and power.


 The „Relay‟ unit contains a relay coil
made up of insulated wire on a metal core and a metal
armature with one or more contacts.
 
 „Relay‟ works on electromagnetic principle.


When a voltage is applied tothe relay coil, current flows through the coil, which in turn
generates a magnetic field.
CoilR

Relay
Coil
elay

oi
el
R

C
y
a

Single Pole Single Single Pole Single Single Pole Double

Throw Normally Throw Normally Throw
Open Closed
 
 The magnetic field attracts the armature core and moves the contact point.
 
The movement of the contact point changes the power/signal flow path.


The Relay is normallycontrolled using a relay driver circuit connected to the port pin of the
 processor/controller


A transistor can be used as the relaydriver. The transistor can be selected depending on the
relay driving current requirements.

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6. The I/O Subsystem – I/O Devices -Piezo Buzzer:
• It is a piezoelectric device for generating audio indications in embedded applications.

• A Piezo buzzer contains a piezoelectric diaphragm which produces audible sound in

response to the voltage applied to it.

• Piezoelectric buzzers are available in two types

1.Self-driving 2.External driving

• Self-driving contains are the necessary components to

generate sound at a predefined tone.

• External driving piezo Buzzers supports the generation of different tones.

• The tone can be varied by applying a variable pulse train to the piezoelectric buzzer.

• A Piezo Buzzer can be directly interfaced to the port pin of the processor/Controller.

7. The I/O Subsystem – I/O Devices – Push button switch:

 
 Push Button switch is an input device.


Push button switch comes
 in two configurations, namely „Push to Make‟
 and „Push to Break‟


contact when
The switch is normally in the open state and it makes a circuit
it is pushed or pressed in the „Push to Make‟ configuration.

 In the „Push to Break‟ configuration, the switch is

normally in the closed state and it breaks the
circuit contact when it is pushed or pressed


The push button stays in the „closed‟ (For Push
to Make type) or „open‟ (For Push to Break
type) state as long as it is kept in the pushed
  the circuit connection
state and it breaks/makes
when it is released.
 
Push button is used for generating a momentary pulse

Page 29 of 111
Page 30 of 111
Page 31 of 111
Text Book:-

1. Introduction to Embedded Systems – Shibu K.V Mc Graw Hill

Page 32 of 111
Communication Interface:
• Communication interface is essential for communicating with various subsystems of the
embedded system and with the external world

• The communication interface can be viewed in two different perspectives; namely;

1. Device/board level communication interface (Onboard Communication Interface)

2. Product level communication interface (External Communication Interface)

1. Device/board level communication interface (Onboard Communication Interface):

The communication channel which interconnects the various components within an
embedded product is referred as Device/board level communication interface (Onboard
Communication Interface)

 Examples: Serial interfaces like I2C, SPI, UART, 1-Wire etc and Parallel bus interface

2. Product level communication interface (External Communication Interface):

The „Product level communication interface‟ (External Communication Interface) is

responsible for data transfer between the embedded system and other devices or modules. The
external communication interface can be either wired media or wireless media and it can be a
serial or parallel interface.

 Examples for wireless communication interface: Infrared (IR), Bluetooth (BT), Wireless
LAN (Wi-Fi), Radio Frequency waves (RF), GPRS etc.
 Examples for wired interfaces: RS-232C/RS-422/RS 485, USB, Ethernet (TCP-IP), IEEE
1394 port, Parallel port etc.

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1. Device/board level or On board communication interfaces: The
Communication channel which interconnects the various components within an embedded
product is referred as Device/board level communication interface (Onboard Communication
Interface)

These are classified into

1.1 I2C (Inter Integrated Circuit) Bus
1.2 SPI (Serial Peripheral Interface) Bus
1.3 UART (Universal Asynchronous Receiver Transmitter)
1.4 1-Wires Interface

1.5 Parallel Interface

1 I2C (Inter Integrated Circuit) Bus:

Inter Integrated Circuit Bus (I2C - Pronounced „I square C‟) is a synchronous bi-directional half
duplex (one-directional communication at a given point of time) two wire serial interface
bus.The concept of I2C bus was developed by „Philips Semiconductors‟ in the early 1980‟s. The
original intention of I2C was to provide an easy way of connection between a
microprocessor/microcontroller system and the peripheral chips in Television sets.

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The I2C bus is comprised of two bus lines, namely; Serial Clock – SCL and Serial Data – SDA.

SCL line is responsible for generating synchronization clock pulses and SDA is
responsible for transmitting the serial data across devices.I2C bus is a shared bus system to
which many number of I2C devices can be connected. Devices connected to the I2C bus can act
as either „Master‟ device or „Slave‟ device.
The „Master‟ device is responsible for controlling the communication by
initiating/terminating data transfer, sending data and generating necessary synchronization clock

pulses.

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 Slave devices wait for the commands from the master and respond upon receiving the
commands. Master and „Slave‟ devices can act as either transmitter or receiver. Regardless
whether a master is acting as transmitter or receiver, the synchronization clock signal is

generated by the „Master‟ device only.I2C supports multi masters on the same bus.
The sequence of operation for communicating with an I2C slave device is:
1. Master device pulls the clock line (SCL) of the bus to „HIGH‟
2. Master device pulls the data line (SDA) „LOW‟, when the SCL line is at logic
„HIGH‟ (This is the „Start‟ condition for data transfer)


3. Master sends the address (7 bit or 10 bit wide) of the „Slave‟ device to which it wants to
communicate, over the SDA line.
4. Clock pulses are generated at the SCL line for synchronizing the bit reception by the
slave device.
5. The MSB of the data is always transmitted first.
6. The data in the bus is valid during the „HIGH‟ period of the clock signal
7. In normal data transfer, the data line only changes state when the clock is low.

8. Master waits for the acknowledgement bit from the slave device whose address is sent on
the bus along with the Read/Write operation command.

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9. Slave devices connected to the bus compares the address received with the address
assigned to them
10. The Slave device with the address requested by the master device responds by sending an
acknowledge bit (Bit value =1) over the SDA line
11. Upon receiving the acknowledge bit, master sends the 8bit data to the slave device over
SDA line, if the requested operation is „Write to device‟.
12. If the requested operation is „Read from device‟, the slave device sends data to the
master over the SDA line.
13. Master waits for the acknowledgement bit from the device upon byte transfer complete
for a write operation and sends an acknowledge bit to the slave device for a read
operation
14. Master terminates the transfer by pulling the SDA line „HIGH‟ when the clock line SCL
is at logic „HIGH‟ (Indicating the „STOP‟ condition).

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1.2 Serial Peripheral Interface (SPI) Bus:
The Serial Peripheral Interface Bus (SPI) is a synchronous bi-directional full duplex four wire
serial interface bus. The concept of SPI is introduced by Motorola.SPI is a single master multi-
slave system.

It is possible to have a system where more than one SPI device can be master, provided
the condition only one master device is active at any given point of time, is satisfied.

SPI is used to send data between Microcontrollers and small peripherals such as shift
registers, sensors, and SD cards.


SPI requires four signal lines for communication. They are:
Master Out Slave In (MOSI): Signal line carrying the data from master to slave device. It is
also known as Slave Input/Slave Data In (SI/SDI)
Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It is
also known as Slave Output (SO/SDO)

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Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low signal.
The master device is responsible for generating the clock signal.
Master device selects the required slave device by asserting the corresponding slave devices
slave select signal „LOW‟.
 The data out line (MISO) of all the slave devices when not selected floats at high impedance
state
 The serial data transmission through SPI Bus is fully configurable.
 SPI devices contain certain set of registers for holding these configurations.
 The Serial Peripheral Control Register holds the various configuration parameters like
master/slave selection for the device, baudrate selection for communication, clock signal
control etc.
 The status register holds the status of various conditions for transmission and reception.SPI
works on the principle of „Shift Register‟.
 The master and slave devices contain a special shift register for the data to transmit or
receive.
 The size of the shift register is device dependent. Normally it is a multiple of 8.

 During transmission from the master to slave, the data in the master‟s shift register is
shifted out to the MOSI pin and it enters the shift register of the slave device through the
MOSI pin of the slave device.

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  At the same time the shifted out data bit from the slave device’s shift register enters the
shift register of the master device through MISO pin

I2C V/S SPI:

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1-wire interface (protocol)

1- Wire is a device communications bus system designed by Dallas Semiconductor Corp. that
provides low-speed data, signaling, and power over a single conductor.

1-Wire is similar in concept to I²C, but with lower data rates and longer range. It is typically used
to communicate with small inexpensive devices such as digital thermometers and weather
instruments.
One distinctive feature of the bus is the possibility of using only two wires: data and ground.
To accomplish this, 1-Wire devices include an 800 pF capacitor to store charge, and to power the
device during periods when the data line is active
There is always one master in overall charge, which may be a PC or a microcontroller.
The master initiates activity on the bus, simplifying the avoidance of collisions on the bus.
Protocols are built into the software to detect collisions. After a collision, the master retries the
required communication.

Many devices can share the same bus. Each device on the bus has a unique 64-bit serial
number. The least significant byte of the serial number is an 8-bit number that tells the type of
the device. The most significant byte is a standard (for the 1-wire bus) 8-bit CRC.
The master starts a transmission with a reset pulse, which pulls the wire to 0 volts for at least 480
µs. This resets every slave device on the bus. After that, any slave device, if present, shows that
it exists with a "presence" pulse: it holds the bus low for at least 60 µs after the master releases
the bus.

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 To send a "1", the bus master sends a very brief (1– 15 µs) low pulse. To send a "0", the
master sends a 60 µs low pulse.When receiving data, the master start sends a 1–15-µs 0-volt
pulse to slave each bit. If the transmitting does unit wants to send a "1", it to the nothing, and the
bus goes transmitting pulled-up voltage. If the "0", it pulls slave wants to send the data line to
ground for 60 µs.

PARALLEL COMMUNICATION:
In data transmission, parallel communication is a method of conveying multiple binary
digits (bits) simultaneously. It contrasts with communication. The communication channel is the
number of electrical conductors used at the physical layer to convey bits.
Parallel communication implies more than one such conductor. For example, an 8-bit
parallel channel will convey eight bits (or a byte) simultaneously, whereas a serial channel would
convey those same bits sequentially, one at a time. Parallel communication is and always has
been widely used within integrated circuits, in peripheral buses, and in memory devices such as
RAM.

2. Product level communication interface (External Communication

Interface): The Product level communication interface‟ (External Communication Interface) is

responsible for data transfer between the embedded system and other devices or modules

It is classified into two types

1. Wired communication interface
2. Wireless communication interface:

1. Wired communication interface: Wired communication interface is an interface used to

transfer information over a wired network.

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It is classified into following types.

1. RS-232C/RS-422/RS 485

2. USB

RS-232C:
 RS-232 C (Recommended Standard number 232, revision C from the Electronic Industry
Association) is a legacy, full duplex, wired, asynchronous serial communication interface
 RS-232 extends the UART communication signals for external data communication.
 UART uses the standard TTL/CMOS logic (Logic „High‟ corresponds to bit value 1 and
Logic „LOW‟ corresponds to bit value 0) for bit transmission whereas RS232 use the
EIA standard for bit transmission.
 As per EIA standard, a logic „0‟ is represented with voltage between +3 and +25V and a
logic „1‟ is represented with voltage between -3 and -25V.
 In EIA standard, logic „0‟ is known as „Space‟ and logic „1‟ as „Mark‟.

The RS232 interface define various handshaking and control signals for communication
apart from the „Transmit‟ and „Receive‟ signal lines for data communication

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RS-232 supports two different types of connectors, namely; DB-9: 9-Pin connector and DB-25:
25-Pin connector.

Fig: DB-25:25-Pin connector.

Fig: DB-9:9-Pin connector.

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 RS-232 is a point-to-point communication interface and the devices involved in RS-232
communication are called „Data Terminal Equipment (DTE)‟ and „Data Communication
Equipment (DCE)‟.
 If no data flow control is required, only TXD and RXD signal lines and ground line (GND)
are required for data transmission and reception.
 The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper
data transmission.
 If hardware data flow control is required for serial transmission, various control signal lines
of the RS-232 connection are used appropriately.
 The control signals are implemented mainly for modem communication and some of them
may be irrelevant for other type of devices.
 The Request to Send (RTS) and Clear To Send (CTS) signals co-ordinate the communication
between DTE and DCE.
 Whenever the DTE has a data to send, it activates the RTS line and if the DCE is ready to
accept the data, it activates the CTS line.
 The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data.
 The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a
communication link.
 DTR should be in the activated state before the activation of DSR.
 The Data Carrier Detect (DCD) is used by the DCE to indicate the DTE that a good signal is
being received.

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 Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line.
 As per the EIA standard RS-232 C supports baudrates up to 20Kbps (Upper limit 19.2Kbps).
 The commonly used baudrates by devices are 300bps, 1200bps, 2400bps, 9600bps,
11.52Kbps and 19.2Kbps.
 The maximum operating distance supported in RS-232 communication is 50 feet at the
highest supported baudrate.
 Embedded devices contain a UART for serial communication and they generate signal levels
conforming to TTL/CMOS logic.
 A level translator IC like MAX 232 from Maxim Dallas semiconductor is used for converting
the signal lines from the UART to RS-232 signal lines for communication.
 On the receiving side the received data is converted back to digital logic level by a converter
IC.
 Converter chips contain converters for both transmitter and receiver.
 RS-232 uses single ended data transfer and supports only point-to-point communication and
not suitable for multi-drop communication.

USB (UNIVERSAL SERIAL BUS):

 External Bus Standard.

 Allows connection of peripheral devices.
 Connects Devices such as keyboards, mice, scanners, printers, joysticks, audio
devices, disks.
 Facilitates transfers of data at 480 (USB 2.0 only), 12 or 1.5 Mb/s (mega-
bits/second).
 Developed by a Special Interest Group including Intel, Microsoft, Compact, DEC,
IBM, Northern Telecom and NEC originally in 1994.
 Low-Speed: 10 – 100 kb/s
 1.5 Mb/s signaling bit rate
 Full-Speed: 500 kb/s – 10 Mb/s 12 Mb/s signaling bit rate
 High-Speed: 400 Mb/s

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 480 Mb/s signaling bit rate

 NRZI with bit stuffing used

 SYNC field present for every packet

 There exist two pre-defined connectors in any USB system - Series “A” and Series “B”
Connectors.

 Series “A” cable: Connects USB devices to a hub port.

 Series “B” cable: Connects detachable devices (hot- swappable)

Bus Topology:

 Connects computer to peripheral devices.

 Ultimately intended to replace parallel and serial ports
 Tiered Star Topology
 All devices are linked to a common point referred to as the root hub.
7
 Specification allows for up to 127 (2 -1) different devices.

 Four wire cable serves as interconnect of system - power, ground and two differential
signaling lines.
 USB is a polled bus-all transactions are initiated by host.

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USB HOST: Device that controls entire system usually a PC of some form. Processes data
arriving to and from the USB port.

USB HUB: Tests for new devices and maintains status information of child devices.Serve as
repeaters, boosting strength of up and downstream signals. Electrically isolates devices from one
another - allowing an expanded number of devices.
2.Wireless communication interface : Wireless communication interface is an interface used to
transmission of information over a distance without help of wires, cables or any other forms of
electrical conductors.

They are basically classified into following types

1. Infrared
2. Bluetooth
3. Wi-Fi
4. Zigbee
5. GPRS

INFRARED:

 Infrared is a certain region in the light spectrum

 Ranges from .7µ to 1000µ or .1mm

 Broken into near, mid, and far infrared

 One step up on the light spectrum from visible light

 Measure of heat

Most of the thermal radiation emitted by objects near room temperature is infrared. Infrared
radiation is used in industrial, scientific, and medical applications. Night-vision devices using
active near-infrared illumination allow people or animals to be observed without the observer
being detected.

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IR transmission:
The transmitter of an IR LED inside its circuit, which emits infrared light for every electric pulse
given to it. This pulse is generated as a button on the remote is pressed, thus completing the
circuit, providing bias to the LED.

The LED on being biased emits light of the wavelength of 940nm as a series of pulses,
corresponding to the button pressed. However since along with the IR LED many other sources
of infrared light such as us human beings, light bulbs, sun, etc, the transmitted information can be
interfered. A solution to this problem is by modulation. The transmitted signal is modulated using
a carrier frequency of 38 KHz (or any other frequency between 36 to 46 KHz). The IR LED is
made to oscillate at this frequency for the time duration of the pulse. The information or the light
signals are pulse width modulated and are contained in the 38 KHz frequency.

IR supports data rates ranging from 9600bits/second to 16Mbps

Serial infrared: 9600bps to 115.2 kbps

Medium infrared: 0.576Mbps to 1.152 Mbps

Fast infrared: 4Mbps

BLUETOOTH:

Bluetooth is a wireless technology standard for short distances (using short-wavelength UHF
band from 2.4 to 2.485 GHz)for exchanging data over radio waves in the ISM and mobile
devices, and building personal area networks (PANs).Invented by telecom vendor Ericsson in
1994, it was originally conceived as a wireless alternative to RS- 232 data cables.

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 Bluetooth uses a radio technology called frequency- hopping spread spectrum. Bluetooth
divides transmitted data into packets, and transmits each packet on one of 79 designated
Bluetooth channels. Each channel has a bandwidth of 1 MHz. It usually performs 800 hops per
second, with Adaptive Frequency-Hopping (AFH) enabled

Originally, Gaussian frequency-shift keying (GFSK) modulation was the only modulation
scheme available. Since the introduction of Bluetooth 2.0+EDR, π/4-DQPSK (Differential
Quadrature Phase Shift Keying) and 8DPSK modulation may also be used between compatible
devices. Bluetooth is a packet-based protocol with a master- slave structure. One master may
communicate with up to seven slaves in a piconet. All devices share the master's clock. Packet
exchange is based on the basic clock, defined by the master, which ticks at312.5 µs intervals.

A master BR/EDR Bluetooth device can communicate with a maximum of seven devices
in a piconet (an ad-hoc computer network using Bluetooth technology), though not all devices
reach this maximum. The devices can switch roles, by agreement, and the slave can become the
master (for example, a headset initiating a connection to a phone necessarily begins as master—
as initiator of the connection—but may subsequently operate as slave).

Wi-Fi:
 Wi-Fi is the name of a popular wireless networking technology that uses radio waves to
provide wireless high-speed Internet and network connections
 Wi-Fi follows the IEEE 802.11 standard
 Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication
 Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless
Access point to manage the communications.
 The Wi-Fi router is responsible for restricting the access to a network, assigning IP address to
devices on the network, routing data packets to the intended devices on the network.

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  Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in
the form of radio signals through an antenna.
 Wi-Fi operates at 2.4GHZ or 5GHZ of radio spectrum and they co-exist with other ISM
band devices like Bluetooth.
 A Wi-Fi network is identified with a Service Set Identifier (SSID). A Wi-Fi device can
connect to a network by selecting the SSID of the network and by providing the
credentials if the network is security enabled
 Wi-Fi networks implements different security mechanisms for authentication and data
transfer.
 Wireless Equivalency Protocol (WEP), Wireless Protected Access (WPA) etc are some of
the security mechanisms supported by Wi-Fi networks in data communication.

ZIGBEE:

Zigbee is an IEEE 802.15.4-based specification for a suite of high- level communication

protocols used to create personal area networks with small, low-power digital radios, such as for
home automation, medical device data collection, and other low-power low-bandwidth needs,
designed for small scale projects which need wireless connection.Hence, zigbee is a low-power,
low data rate, and close proximity (i.e., personal area) wireless ad hoc network.The technology

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defined by the zigbee specification is intended to be simpler and less expensive than other
wireless personal area networks (WPANs), such as Bluetooth or Wi-Fi . Applications include
wireless light switches, electrical meters with in-home-displays, traffic management systems, and
other consumer and industrial equipment that require short-range low- rate wireless data transfer.
Its low power consumption limits transmission distances to 10– 100 meters line-of-sight,
depending on power output and environmental characteristics. Zigbee devices can transmit data
over long distances by passing data through a mesh network of intermediate devices to reach
more distant ones.

Zigbee Coordinator: The zigbee coordinator acts as the root of the zigbee network. The ZC is
responsible for initiating the Zigbee network and it has the capability to store information about
the network.

Zigbee Router: Responsible for passing information from device to another device or to another
ZR.

Zigbee end device:End device containing zigbee functionality for data communication. It can
talk only with a ZR or ZC and doesn’t have the capability to act as a mediator for transferring
data from one device to another.

Zigbee supports an operating distance of up to 100 metres at a data rate of 20 to 250 Kbps.

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General Packet Radio Service(GPRS):

General Packet Radio Service (GPRS) is a packet oriented mobile data service on the 2G and
3G cellular communication system's global system for mobile communications (GSM).GPRS
was originally standardized by European Telecommunications Standards Institute (ETSI) GPRS
usage is typically charged based on volume of data transferred, contrasting with circuit switched
data, which is usually billed per minute of connection time. Sometimes billing time is broken
down to every third of a minute. Usage above the bundle cap is charged per megabyte, speed
limited, or disallowed.

Services offered:

 GPRS extends the GSM Packet circuit switched data capabilities and makes the
following services possible:
 SMS messaging and broadcasting
 "Always on" internet access
 Multimedia messaging service (MMS)
 Push-to-talk over cellular (PoC)
 Instant messaging and presence-wireless village Internet applications for smart devices
through wireless application protocol (WAP).
 Point-to-point (P2P) service: inter-networking with the Internet (IP).
 Point-to-multipoint (P2M) service]: point-to- multipoint multicast and point-to-multipoint
group calls.

Text Book:-

1. Introduction to Embedded Systems – Shibu K.V Mc Graw Hill

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 Embedded Firmware
Introduction:
The control algorithm (Program instructions) and or the configuration
settings that an embedded system developer dumps into the code (Program)
memory of the embedded system
It is an un-avoidable part of an embedded system.
The embedded firmware can be developed in various methods like
o Write the program in high level languages like Embedded C/C++
using an Integrated Development Environment (The IDE will contain
an editor, compiler, linker, debugger, simulator etc. IDEs are different
for different family of processors/controllers.
o Write the program in Assembly Language using the Instructions
Supported by your application’s target processor/controller

Embedded Firmware Design & Development:

The embedded firmware is responsible for controlling the various

peripherals of the embedded hardware and generating response in
accordance with the functional requirements of the product.

The embedded firmware is the master brain of the embedded system.

The embedded firmware imparts intelligence to an Embedded system.

It is a onetime process and it can happen at any stage.

The product starts functioning properly once the intelligence imparted to the
product by embedding the firmware in the hardware.

The product will continue serving the assigned task till hardware breakdown
occurs or a corruption in embedded firmware.

In case of hardware breakdown , the damaged component may need to be

replaced and for firmware corruptions the firmware should be re-loaded, to
bring back the embedded product to the normal functioning.

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 The embedded firmware is usually stored in a permanent memory (ROM)
and it is non alterable by end users.

Designing Embedded firmware requires understanding of the particular

embedded product hardware, like various component interfacing, memory
map details, I/O port details, configuration and register details of various
hardware chips used and some programming language (either low level
Assembly Language or High level language like C/C++ or a combination of
the two)

The embedded firmware development process starts with the conversion of

the firmware requirements into a program model using various modeling
tools.

The firmware design approaches for embedded product is purely dependent

on the complexity of the functions to be performed and speed of operation
required.

There exist two basic approaches for the design and implementation of
embedded firmware, namely;

 The Super loop based approach

 The Embedded Operating System based approach

The decision on which approach needs to be adopted for firmware

development is purely dependent on the complexity and system
requirements

1. Embedded firmware Design Approaches – The Super loop:

The Super loop based firmware development approach is Suitable for

applications that are not time critical and where the response time is not so
important (Embedded systems where missing deadlines are acceptable).

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 It is very similar to a conventional procedural programming where the code
is executed task by task

The tasks are executed in a never ending loop.

The task listed on top on the program code is executed first and the tasks just
below the top are executed after completing the first task

A typical super loop implementation will look like:

1. Configure the common parameters and perform initialization for

various hardware components memory, registers etc.
2. Start the first task and execute it
3. Execute the second task
4. Execute the next task
5. :
6. :
7. Execute the last defined task
8. Jump back to the first task and follow the same flow.
The ‘C’ program code for the super loop is given below

void main ()
{
Configurations ();
Initializations ();
while (1)
{
Task 1 ();
Task 2 ();
:

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 :
Task n ();
}
}
Pros:

Doesn’t require an Operating System for task scheduling and monitoring and
free from OS related overheads
Simple and straight forward design
Reduced memory footprint
Cons:

Non Real time in execution behavior (As the number of tasks increases the
frequency at which a task gets CPU time for execution also increases)

Any issues in any task execution may affect the functioning of the product
(This can be effectively tackled by using Watch Dog Timers for task
execution monitoring)

Enhancements:
 Combine Super loop based technique with interrupts

 Execute the tasks (like keyboard handling) which require Real time attention
as Interrupt Service routines.

2. Embedded firmware Design Approaches – Embedded OS based Approach:

The embedded device contains an Embedded Operating System which can

be one of:

 A Real Time Operating System (RTOS)

 A Customized General Purpose Operating System (GPOS)

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 The Embedded OS is responsible for scheduling the execution of user tasks
and the allocation of system resources among multiple tasks

It Involves lot of OS related overheads apart from managing and executing

user defined tasks

Microsoft® Windows XP Embedded is an example of GPOS for embedded

devices

Point of Sale (PoS) terminals, Gaming Stations, Tablet PCs etc are examples
of embedded devices running on embedded GPOSs

‘Windows CE’, ‘Windows Mobile’,‘QNX’, ‘VxWorks’, ‘ThreadX’,

‘MicroC/OS-II’, ‘Embedded Linux’, ‘Symbian’ etc are examples of RTOSs
employed in Embedded Product development

Mobile Phones, PDAs, Flight Control Systems etc are examples of

embedded devices that runs on RTOSs

Embedded firmware Development Languages/Options

Assembly Language

High Level Language

o Subset of C (Embedded C)
o Subset of C++ (Embedded C++)
o Any other high level language with supported Cross-compiler

Mix of Assembly & High level Language

o Mixing High Level Language (Like C) with Assembly Code

o Mixing Assembly code with High Level Language (Like C)
o Inline Assembly

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 1. Embedded firmware Development Languages/Options – Assembly
Language

‘Assembly Language’ is the human readable notation of ‘machine

language’
‘Machine language’ is a processor understandable language
Machine language is a binary representation and it consists of 1s and 0s
Assembly language and machine languages are processor/controller
dependent
An Assembly language program written for one processor/controller family
will not work with others
Assembly language programming is the process of writing processor specific
machine code in mnemonic form, converting the mnemonics into actual
processor instructions (machine language) and associated data using an
assembler

The general format of an assembly language instruction is an Opcode

followed by Operands

The Opcode tells the processor/controller what to do and the Operands

provide the data and information required to perform the action specified by
the opcode

It is not necessary that all opcode should have Operands following them.
Some of the Opcode implicitly contains the operand and in such situation no
operand is required. The operand may be a single operand, dual operand or
more

The 8051 Assembly Instruction

MOV A, #30

Moves decimal value 30 to the 8051 Accumulator register. Here MOV A is the
Opcode and 30 is the operand (single operand). The same instruction when written
in machine language will look like

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 01110100 00011110

The first 8 bit binary value 01110100 represents the opcode MOV A and the second
8 bit binary value 00011110 represents the operand 30.

Assembly language instructions are written one per line

A machine code program consists of a sequence of assembly language
instructions, where each statement contains a mnemonic (Opcode +
Operand)
Each line of an assembly language program is split into four fields as:

LABEL OPCODE OPERAND COMMENTS

LABEL is an optional field. A ‘LABEL’ is an identifier used extensively in

programs to reduce the reliance on programmers for remembering where
data or code is located. LABEL is commonly used for representing

A memory location, address of a program, sub-routine, code portion etc.

 The maximum length of a label differs between assemblers.

Assemblers insist strict formats for labeling. Labels are always
suffixed by a colon and begin with a valid character. Labels can
contain number from 0 to 9 and special character _ (underscore).

;###############################################################
; SUBROUTINE FOR GENERATING DELAY
; DELAY PARAMETR PASSED THROUGH REGISTER R1
; RETURN VALUE NONE,REGISTERS USED: R0, R1
;###############################################################
##### DELAY: MOV R0, #255 ; Load Register R0 with 255

DJNZ R1, DELAY; Decrement R1 and loop till R1= 0

RET ; Return to calling program

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  The symbol ; represents the start of a comment. Assembler ignores the
text in a line after the ; symbol while assembling the program
 DELAY is a label for representing the start address of the memory
location where the piece of code is located in code memory
 The above piece of code can be executed by giving the label DELAY as
part of the instruction. E.g. LCALL DELAY; LMP DELAY
2. Assembly Language – Source File to Hex File Translation:
The Assembly language program written in assembly code is saved as
.asm (Assembly file) file or a .src (source) file or a format supported by
the assembler
Similar to ‘C’ and other high level language programming, it is possible
to have multiple source files called modules in assembly language
programming. Each module is represented by a ‘.asm’ or ‘.src’ file or the
assembler supported file format similar to the ‘.c’ files in C programming
The software utility called ‘Assembler’ performs the translation of
assembly code to machine code
The assemblers for different family of target machines are different. A51
Macro Assembler from Keil software is a popular assembler for the 8051
family micro controller

Figure 5: Assembly Language to machine language conversion process

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 Each source file can be assembled separately to examine the syntax errors
and incorrect assembly instructions
Assembling of each source file generates a corresponding object file. The
object file does not contain the absolute address of where the generated
code needs to be placed (a re-locatable code) on the program memory
The software program called linker/locater is responsible for assigning
absolute address to object files during the linking process
The Absolute object file created from the object files corresponding to
different source code modules contain information about the address
where each instruction needs to be placed in code memory
A software utility called ‘Object to Hex file converter’ translates the
absolute object file to corresponding hex file (binary file)
Advantages:

 1.Efficient Code Memory & Data Memory Usage (Memory Optimization):

 The developer is well aware of the target processor architecture and

memory organization, so optimized code can be written for
performing operations.
 This leads to less utilization of code memory and efficient utilization
of data memory.
 2.High Performance:

 Optimized code not only improves the code memory usage but also
improves the total system performance.
 Through effective assembly coding, optimum performance can be
achieved for target processor.
 3.Low level Hardware Access:

 Most of the code for low level programming like accessing external
device specific registers from OS kernel ,device drivers, and low level
interrupt routines, etc are making use of direct assembly coding.

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  4.Code Reverse Engineering:

 It is the process of understanding the technology behind a product by

extracting the information from the finished product.
 It can easily be converted into assembly code using a dis-assembler
program for the target machine.
Drawbacks:

1.High Development time:

 The developer takes lot of time to study about architecture ,memory

organization, addressing modes and instruction set of target
processor/controller.
 More lines of assembly code is required for performing a simple
action.
2.Developer dependency:

 There is no common written rule for developing assembly language

based applications.

3.Non portable:

 Target applications written in assembly instructions are valid only for

that particular family of processors and cannot be re-used for another
target processors/controllers.
 If the target processor/controller changes, a complete re-writing of the
application using assembly language for new target
processor/controller is required.
2. Embedded firmware Development Languages/Options – High Level
Language

The embedded firmware is written in any high level language like C, C++

A software utility called ‘cross-compiler’ converts the high level language to

target processor specific machine code

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  The cross-compilation of each module generates a corresponding object
file. The object file does not contain the absolute address of where the
generated code needs to be placed (a re-locatable code) on the program
memory
 The software program called linker/locater is responsible for assigning
absolute address to object files during the linking process
 The Absolute object file created from the object files corresponding to
different source code modules contain information about the address where
each instruction needs to be placed in code memory
 A software utility called ‘Object to Hex file converter’ translates the
absolute object file to corresponding hex file (binary file)
Embedded firmware Development Languages/Options – High Level
Language – Source File to Hex File Translation

Library Files

Source File 1
Module
(.c /.c++ etc) Object File 1
Cross-compiler
(Module-1)

Source File 2
Module
(.c /.c++ etc) Object File 2
Cross-compiler
(Module-2)

Object to Hex File Linker/

Absolute Object File
Converter Locator

Machine Code
(Hex File)

Figure 6: High level language to machine language conversion process

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Advantages:

Reduced Development time: Developer requires less or little

knowledge on internal hardware details and architecture of the target
processor/Controller.

Developer independency: The syntax used by most of the high level

languages are universal and a program written high level can easily
understand by a second person knowing the syntax of the language

Portability: An Application written in high level language for

particular target processor /controller can be easily be converted to
another target processor/controller specific application with little or
less effort

Drawbacks:

• The cross compilers may not be efficient in generating the optimized

target processor specific instructions.

• Target images created by such compilers may be messy and non-

optimized in terms of performance as well as code size.

• The investment required for high level language based development

tools (IDE) is high compared to Assembly Language based firmware
development tools.

Embedded firmware Development Languages/Options – Mixing of Assembly

Language with High Level Language

Embedded firmware development may require the mixing of Assembly

Language with high level language or vice versa.

Interrupt handling, Source code is already available in high level

language\Assembly Language etc are examples

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 High Level language and low level language can be mixed in three different
ways

 Mixing Assembly Language with High level language like ‘C’

 Mixing High level language like ‘C’ with Assembly Language

 In line Assembly

The passing of parameters and return values between the high level and low
level language is cross-compiler specific

1. Mixing Assembly Language with High level language like ‘C’

(Assembly Language with ‘C’):

Assembly routines are mixed with ‘C’ in situations where the entire program
is written in ‘C’ and the cross compiler in use do not have built in support
for implementing certain features like ISR.

If the programmer wants to take advantage of the speed and optimized code
offered by the machine code generated by hand written assembly rather than
cross compiler generated machine code.

For accessing certain low level hardware ,the timing specifications may be
very critical and cross compiler generated machine code may not be able to
offer the required time specifications accurately.

Writing the hardware/peripheral access routine in processor/controller

specific assembly language and invoking it from ‘C’ is the most advised
method.

Mixing ‘C’ and assembly is little complicated.

The programmer must be aware of how to pass parameters from the ‘C’
routine to assembly and values returned from assembly routine to ‘C’ and
how Assembly routine is invoked from the ‘C’ code.

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 Passing parameter to the assembly routine and returning values from the
assembly routine to the caller ‘C’ function and the method of invoking the
assembly routine from ‘C’ code is cross compiler dependent.

There is no universal written rule for purpose.

We can get this information from documentation of the cross compiler.

Different cross compilers implement these features in different ways

depending on GPRs and memory supported by target processor/controller

2. Mixing High level language like ‘C’ with Assembly Language

(‘C’ with Assembly Language)

The source code is already available in assembly language and routine

written in a high level language needs to be included to the existing code.

The entire source code is planned in Assembly code for various reasons like
optimized code, optimal performance, efficient code memory utilization and
proven expertise in handling the assembly.

The functions written in ‘C’ use parameter passing to the function and
returns values to the calling functions.

The programmer must be aware of how parameters are passed to the

function and how values returned from the function and how function is
invoked from the assembly language environment.

Passing parameter to the function and returning values from the function
using CPU registers , stack memory and fixed memory.

Its implementation is cross compiler dependent and varies across compilers.

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3.In line Assembly:

• Inline assembly is another technique for inserting the target

processor/controller specific assembly instructions at any location of source
code written in high level language ‘C’

• Inline Assembly avoids the delay in calling an assembly routine from a ‘C’
code.

• Special keywords are used to indicate the start and end of Assembly
instructions

• E.g #pragma asm

Mov A,#13H

#pragma ensasm

• Keil C51 uses the keywords #pragma asm and #pragma endasm to indicate
a block of code written in assembly.

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