Stanford CS Junji Ogawa MH students Feb. 11th.

1999

DRAM Design Overview

DRAM Design Overview

Stanford University
Junji Ogawa
jogawa@cis.stanford.edu

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Contents

・Trends of Standard DRAM

・History of DRAM Circuits
・Cell, Array and Major Circuits
・Embedded DRAM
・ASM Example
・Summary

Feb. 11th. 1998 Junji Ogawa

Page 1
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Standard DRAM Development

4G
1000
1G
500 256M 4G
Conference Early Production
64M
Die Size(mm2)

200
256M Production
100 64M
16M 128M
50 1G
i-line KrF KrF+α ArF ?
Rule
0.50 0.35 0.25 0.18 0.13 0.10 (um)
20
90 92 94 96 98 00 02 04 06 08 10
Year
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Bit Cost Trend of DRAMs

4 -0
10 10

3 -1
10 10
size
Die
Density（Mbits)

ity
Die Size（mm2)

Bit Cost（$）

2 -2
10 ns 10
Rule（µm）

De
1 -3
10 10
Bit Cost
0 -4
10 Rule 10

-1 16M -5
10 64M 10
256M
1G
-2
4G -6
10 10
1980 1985 1990 1995 2000 2005 2010 Year

Feb. 11th. 1998 Junji Ogawa

Page 2
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Access Time Trend

f CLK (Popular Synchronous Frequency :MHz)

2 9
10 10

1/tAA (/CAS Access Frequency :MHz)

TRAC (/RAS Access Time :ns)
Power Supply Voltage (V)

VCCx10
TRAC

8
10
1 10

1/tAA
f CLK

7
1 10
4M 16M 64M 256M 1G 4G

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Standard DRAM Column Access Mode

Product Volume [ 100 million ]

25 -- ?
FPM >128M
64M SD

20 -- SD
64M RD
Rambus
16M
EDO SD SDRAM

10 -- 16M EDO

4M

0 --
'97 '98 '99 2000
Year

Feb. 11th. 1998 Junji Ogawa

Page 3
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

DRAM Operating Frequency v.s. Customizability

ASSP/ASIC
Function rich DRAM
Customizability

DRAM/Logi
c
WRAM

CDRAM High-speed
VRAM MDRAM DRAM
Standard

EDRAM SLDRAM

DDR
RAMBUS Target
SDRAM
EDO

100MHz 200MHz 500MHz 1GHz 2GHz

Operating Frequency
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

VCC & VII & WL Voltage Trend

Internally Regulated Supply Voltage(v)

8 Internally Regulated Supply Voltage(V)

Power Supply Voltage (V)
Word Boost Level(V)

6
Power Supply Voltage (v)
Word Boost Voltage (v)

0
4M 16M 64M 256M 1G 4G
Bit Density

Feb. 11th. 1998 Junji Ogawa

Page 4
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Power Dissipation Trend

1 1
10 10
Active Power tRC=min. (A) VCC
Power Supply Voltage (V)

( Low Power mode: mA)

Low Power
0 0
10 Stand-by Power 10

Stand-by Power
-1 -1
10 10
Active Power

-2 -2
10 10
4M 16M 64M 256M 1G 4G

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Refresh Specification Trend

Numbers of Active S／As Refresh Interval (max.:ms)

Numbers of Active Sense Amplifiers

Refresh Cycles Busy Rate (µ s)

Distributed Refresh Interval
5 3
10 10
Distributed Refresh Interval
Refresh Interval (max.:ms)

4 2
10 10
Busy Rate (µ S)
Refresh Cycles

3 1
10 10

2 0
10 10
1M 4M 16M 64M256M 1G 4G

Feb. 11th. 1998 Junji Ogawa

Page 5
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

History
・1K DRAM Intel 1103 introduced late 1971
-3Tr PMOS, 1P1M,
-Vdd=0v,Vss=16v,Vbb=20v, Trac=300ns
・4K DRAM TI TMS4030 introduced 1973
-1Tr NMOS, 1P1M, TTL I/O
-Vdd=12v,Vdd=5v, Vss=0v,Vbb=-3/-5v

・16K DRAM Mostek MK4116 introduced 1977

-1Tr NMOS, 2P1M, Address multiplex
-Vdd=12v,Vdd=5v, Vss=0v,Vbb=-5v, Trac=250ns
**Open / Folded bit line, Double poly cell, Multi-PS
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Bascic Bitline Structure (1)

Open Bitlines Folded Bitlines

Memory Memory /BL BL

BL
Array Array
WL WL

S/As S/As

Open BL Folded BL
Memory
Array Cell Size 6F2 Cell Size 8F2
/BL WL pitch: 3F WL pitch: 4F
BL pitch: 2F BL pitch: 2F

Denser Memory Relaxed S/A layout pitch

Uneven WL coupling Even WL coupling

Feb. 11th. 1998 Junji Ogawa

Page 6
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

History (cont’d)
・64K DRAM (’80,conference’79)
-Many changes at once - no dominant design
-Standardized, Page mode, Refresh functions
-Vcc=5v only,Vss=0v,Internal Vbb, Trac=200ns
-Boosted wordline, Active restore

・256K DRAM (’83,conference’82)

-1Tr NMOS, 3P1M(FJ), I.I. mask increasing
-Vcc=5v only, Nibble/SC/CBR func., Trac=150ns
-Open v.s. Folded, Redundancy, CMOS prototype
-Vdd bitline pre-charge
-Some ASM, Wide I/O (x4)
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

History (cont’d)
・1M DRAM (’86,conference’84)
-N-well CMOS, 3P1M, Vdd/2 cell plate
-Half Vdd bitline reference and pre-charge,
-Shared folded bitline
-x4/x8, Package and module variety, Test circuits

・4M DRAM (’89, conference’87)

-3D stacked or trench cell, CMOS, 4P1M,
-x16, Fast page/Self refresh, Trac=80ns
-Current-mirror data bus amp., Boosted I/O driver
-Word line strapping, Triple-well
Feb. 11th. 1998 Junji Ogawa

Page 7
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Basic Bitline Structure (2)

Interleaved (Multiplexed)
Folded Shared S/As
BLs
Memory /BLU BLU Memory
Array Array
WLU WLU

S/As S/As

WLL WLL
Memory
Array
Memory
/BLL BLL BLL
Array

Less area occupied S/As

by S/As
Used in nearly all 16M
Relaxes S/A pitch
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

History (cont’d)
・16M DRAM (’92, conference’90)
-N-well CMOS, 4P2M
-Internal Vdd down-converter (5v ext.---3.3v int.)
-Shared Y-decoder, Interleaved S/A,
-Vpp supply WL driver, RDRAM(PLL/DLL)

・64M DRAM (’95, conference ’91)

-Triple well CMOS, Vss Substrate, 4P2M,
-Vdd=3.3v, Separate I/O PS-pin (Vddq/Vssq)
-SDRAM (clocked In, pipelined, burst I/O, term. I/F)
-COB, Staggered Sense amp.
Feb. 11th. 1998 Junji Ogawa

Page 8
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Circuit Evolution Picking up

・3Tr to 1Tr1C ・Address Multiplex
・Boosted Wordline ・Open BL to Folded BL
・Single Power Supply ・NMOS to CMOS
(Vbb gene., WL boost) ・Page & Refresh Mode
・Redundancy ・Appli. Specific Circuits
・Vdd/2 BL pre-charge (ex. SR for VRAM)
・ Internal DC converter ・Test mode
・ Clocked operation ・ Pipelined operation
・ PLL/DLL ・ High speed interface
・ Multi-bank core ・ Embedded core
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Cell Array and Circuits

(1) 1 Transistor 1 Capacitor Cell
・Size Comparison to SRAM Cell
(2) Array Example
(3) Major Circuits (today’s example)
・Sense amplifier
・Dynamic Row Decoder
・Wordline Driver

The other circuits interesting for VLSI designer

・Data bus amplifier ・Voltage Regulator
・ Reference generator ・Redundancy technique
・Replica technique ・High speed I/O circuits
Feb. 11th. 1998 Junji Ogawa

Page 9
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

SRAM v.s. DRAM

6Tr embedded SRAM 1Tr1C Standard DRAM

WL Access Tr
(Cell Tr,
Transfer Tr)
WL Cwb

Storage Node

Cs

Cbl
BL /BL BL
Plate

Gain element in cell Passive element

(No gain, Refresh needed)
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Comparison of SRAM and DRAM Cell Size

100
6Tr SRAM
Plainer
Cell Size [um2]

10
3Tr

Stack
0.1
DRAM
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Design Rule [um]
Feb. 11th. 1998 Junji Ogawa

Page 10
 MH students Feb. 11th. 1999

8 global data buses

32M-CELL BLOCK
S/A)
4096S/A+16R**S/A+64Red-S/A+16Mark-RAM(64
Mark-RAM
(4S/A
K)for 64 100%
3.5%+0.39% +1.56% + 1.56% =
CL)
(1024
32 Mbit array.

4R**S/
A 1024S/A+4R**S/A
+16Red-S/A+4Mark-RAM
7

A
4 Red-S/
A
256S/ Sub-Word Decoder
A
256S/
MWDEC (256CL)
MWDEC ←s/a-
0

MWL
256
256K Cell
Array 1M BLOCK #0
Standard DRAM Array Design Example

1
←s/a-
DQ
MWL

DRAM Array Example

64K 1M BLOCK #1
Junji Ogawa

Junji Ogawa
0

←s/a-
2
8 global data buses

1M BLOCK #2
←s/a-
3
and 8 amplifiers

1M BLOCK #3
←s/a-
4
1M BLOCK #4
64 Mbit DRAM
32 Mbit arrays

5
←s/a-
consists of two

1M BLOCK #5
←s/a-
6
1M BLOCK #6
←s/a-
7
1M BLOCK #7
←s/a-
8

Main Word Decoder / Driver

Page 11
1M BLOCK #8
9
←s/a-
1M BLOCK #9
bank 0 bank 8 bank 0 bank 8

←s/a-1
0
15

1M BLOCK #10

64 Mbit Core, a part of 256M DRAM

32 Mbit

15

←s/a-1
1
1M BLOCK #11
←s/a-1
2
DQ
7

8
←s/a-2
6
15

1M BLOCK #26
32 Mbit

7 ←s/a-2
7
1M BLOCK #27
←s/a-2
8
1M BLOCK #28

DQ
9
←s/a-2

0
7
Stanford CS Junji Ogawa

RCL 1M BLOCK #29

DRAM Design Overview

DRAM Design Overview

←s/a-3
0
CL 1M BLOCK #30
Mark
Out ←s/a-3
1
1M BLOCK #31
2
←s/a-3
←s/a-Ｒ
0 RowBLOCK
128K Spare #R

Feb. 11th. 1998

Feb. 11th. 1998

←s/a-Ｒ
1
C-DEC. C-DEC.
(64CL) C-DEC.
(64CL) C-DEC.
(64CL) (64CL)C-DEC. C-DEC.
(64CL) C-DEC.
(64CL) C-DEC.
(64CL) (64CL) Column Decoder
Driver &
(256CL)
COL. DECODER
EOR EOR & etc.
Mark(forCOL.
& Add RAM
)
Address
Mark RAM
& Spare Col.
Mark& Mark
Add RAM & Add.
RAM
(for 64K) Driver
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

DRAM Array Example (cont’d)

Interleaved S／A & Hierarchical Row Decoder/Driver

(shared bit lines are not shown)
１ ２ ３ Nmat

SA

SA

SA

SA
SA
SA

SA

SA

SA
SA
SA

SA

SA
SA

SA
SA

Q
P
Q

P
P

Clump TR or so
Main Row Dec

SA

SA

SA
SA

SA

SA

SA

SA
SA
SA
SA

SA
SA

SA

SA

SA
Q

P
P

Q
P

512K Array Nmat=16 or 12

( 256 WL x 2048 SA)

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Row Decoder and Driver

＜WL Strapping Type＞

Clump TR or so
Main Row Dec

VCC
Addresses WDi Contact only (Strapping)

Reset AL strap line

Dynamic P1 word line

NAND

Feb. 11th. 1998 Junji Ogawa

Page 12
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Row Decoder and Driver (cont’d)

＜Hierarchical WL Type＞
VPP
/pre#

Clump TR or so
level MWL

Main Row Dec

/rbnk# shifter

Pre-decode
address

# is bank No. MWDEC

Sub Word Decoder AL Main Word Line

VPP WDij WDik WDil WDim
Reset Reset Reset Reset
Addresses VPP → ↓ ↓ ↓ ↓

Reset
P1 sub-word line P
Dynamic P
NAND
Negative Voltage?

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Sense Amplifier Circuits - Folded Shared Interleaved -

BLTR CL BS BLTR
/BLL /BLR
ldb1z
ldb1x

ldb0x
ldb0z

nsa

psa

BLL BLR

Local Data Bus NSA PSA VPR

/RAS
CL
BS WD WL
BL PSA
RAS
/BL NSA
t
Add. LE
Feb. 11th. 1998 Junji Ogawa

Page 13
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Sense Amplifier Pitch Matched Layout

Bitlines

Nch Pch

Nch Pch Nch

Nch Pch

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Standard DRAM Design Feature

・Tightly depends on technology
・The row circuits is fully different from SRAM.
・Few product variation in the same technology
・“Trends” is mother , “Cost” is father .
・“Standard” gives us less freedom!
・Almost always analogue circuit design
・Simply forward critical path
・CAD: Spice-like circuits simulator
Fully handcraft layout,
Whole-chip tools must be a dream.
Feb. 11th. 1998 Junji Ogawa

Page 14
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Embedded DRAM or Merged D&L

・Merged DRAM and Logic
-Technology choice and cost issue
----People have talked too much above.
-Otherwise, that’s a near future evolution.
・Current Technology behind advanced DRAMs’
・Small ASIC seems to be not yet on the business.
・How solve the following technical problem?
memory wall, granularity, I/O power

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Speed Gap between DRAM and CPU

- Memory Wall -
Performance(Speed Ratio)

1000 μPU
60%/year
100
Increasing
The Gap
10

1 DRAM7%/year
80 85 90 95 00
Year

Feb. 11th. 1998 Junji Ogawa

Page 15
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

The numbers of DRAM on PCs

DRAM Generation
86 89 93 97 01 05
1Mb 4Mb 16Mb 64Mb 256Mb 1Gb

4MB 32 8
Memory/DRAM
Main Memory Size

growth @60%/year
8MB 16 4

16MB 32 8 2

32MB 16 4 1

64MB 8 2
Memory/System
128MB growth @25%/year 4 1

256MB 8 2
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Macro Power (MDL v.s. Standard DRAM)

External
4.0 Standard DRAM

3.0
Power [W]

0.35um
2.35W 8M Macro
I/O Load
2.0 Charging
70%
1.11W

1.0 Re-design

0
8 32 64 128 256
1 16 I/O width
Feb. 11th. 1998 Junji Ogawa

Page 16
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

Macro Power (cont’d)

2.35W
75 % Macro Power depends on
Load 47% the numbers of I/O
50ｐF
Power[W]

1.11W 70%

Load 1ｐF
0.78W
depend on I/O No.
Load 1ｐF (Column)
75% depend on I/O
No.
(Row)
15%
Independen
External use of 8M Macro t
Standard DRAM Macro Re-design & Shrink on I/O No.

Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

The First Commercial Product of Embedded DRAM

M32R/D（Mitsubishi）
・0.45µm DRAM
・32-bit RISC CPU
+ 16Mbit DRAM
2
・Die Size: 153.7mm
Feb. 11th. 1998 Junji Ogawa

Page 17
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

0.25um Embedded DRAM Products

DRAM v.s. Logic Size
Logic
Network
5000 Rich
Graphics G
Logic Gate ( K gates )

A
B
1500 MCU Core
E
E (TV)

500 H
D DRAM
E’ Rich
K

150
C
F

50
L J (HDD)

２ ４ ８ 32 74
16
DRAM Size (M bits )
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Memory Density and Logic Gates

: Affordable DRAM-density & Logic-gates in a 100mm2 Die
1 Gb
. 9
=0
Standard DRAM Technology ti o
Ra
a
Memory Density

e
Ar
M
100 Mb 0.18 um
D RA MDL Technology
0.25 um
0.35 um A
1 Pure Logic
0. Technology
10 Mb B
5
D
C 0.0
MDL Process
SRAM
1 Mb
10 K 100 K 1M 10 M Gates
Feb. 11th. 1998 Junji Ogawa

Page 18
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

DRAM Macro Size Shrink

ー Which could make cost effective ?
A
DRAM Macro Area（ｍｍ２）
16Mb 32Mb 10mm
DRAM

10mm
B
E

100 8Mb D ：32Mb

：16Mb
F C ： 8Mb

Cost Effective
Region? G

0
0.50 0.35 0.25 0.18 Rule（ｕｍ）
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Application Specific Memory

-Brief Introduction-
・Various ASM introduced since ’83
-VRAM: 64K to 4M VRAM
-Field Memory(NEC), Triple Port(FJ)
-mostly for ASICs or conference chips
・Only VRAM got a semi-standardization
・ Longer design TAT
as more complicated spec. and circuits
・Redundancy and Test isuues: big problems
・Never major products
Feb. 11th. 1998 Junji Ogawa

Page 19
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

256K Dual Port Video RAM

Standard DRAM

Parallel to Serial
Sift Register
BUS
CRT RAM CPU
Time Share

変
換
CPU efficiency 50%

(a) Conventional 2D Graphic System

VRAM

BUS
SAM

CRT CPU
RAM
Conditional Dual Port )
1024 bit transfer @100ns
CPU efficiency 95%
(b) 2D Graphic System used VRAM
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

256K Dual Port Video RAM (cont’d)

Column Dec.
(Serial Port)
A mp.
SAM Sout/Sin
S/A
A mp.
Dout/Sout
R
o (Random Port)
w
D Cell A rray
e
c
.

・Narrow pitch matched SAM (or Sift Register) design

・No explicit bus for a mass of data transfer at a time
・A hinted solution by utilizing a memory parallelism

Feb. 11th. 1998 Junji Ogawa

Page 20
Stanford CS Junji Ogawa MH students Feb. 11th. 1999

DRAM Design Overview

4M bit Cubic Memory (conference ’90)

・16b x 16b x 16b (4Kbit) virtual bit map space

・six different ways of column access on the fly access
Feb. 11th. 1998 Junji Ogawa

DRAM Design Overview

Summary
・Passive 1Tr1C cell leads all the features of dynamic
circuits and design complexity.
・The row circuits is fully different from SRAM.

・A Dinosaur, Standard DRAM, become almost dead,

because of both the technology saturation and
the narrow band-width itself.

・ The design technique should be transferred

for the coming embedded era.

Feb. 11th. 1998 Junji Ogawa

Page 21