Data Flow Modelling, Counters: Points To Remember

This document describes designing a 4-bit ripple counter using Verilog dataflow modeling. It contains diagrams of the counter modules built from D-flipflops. Dataflow code is provided for the T-flipflop and edge-triggered D-flipflop modules. The design is instantiated and tested in a stimulus module using a clock signal. The output simulation shows the counter counting up on each clock edge and being reset to zero by a clear signal.

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Data Flow Modelling, Counters: Points To Remember

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Muhammad Usman Rafiq

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DATA FLOW MODELLING, COUNTERS

Points to Remember

1
 When instantiating a module, the order of the ports used in instantiation must be the same as
their order in the module definition.

DATAFLOW MODELLING (CONTD)

Example: Ripple Counter

In this lab we will design a 4-bit ripple counter by using negative edge-triggered flip flop. We design
it using Verilog dataflow statements and test it with a stimulus module. The diagrams for the 4-bit
ripple carry counter modules are shown below. Fallowing figure shows the counter being built with
four T-flipflops.

2
As the T- FF is built with D- FF:

Dataflow code:

Verilog Code for T-flipflop

Finally, we define the lowest level module D_FF (edge_dff ), using dataflow statement.

3
Verilog Code for Edge-Triggered D-flipflop

4
The design block is now ready. Now we must instantiate the design block inside the stimulus block
to test the design. The clock has a time period of 20 with a 50% duty cycle.

NOTE: $finish statement is used whenever forever loop or always block is used, otherwise the
loop will keep on running indefinitely; it serves the useful purpose of suspending all initial
blocks. Also note that forever loop is normally used in conjunction with initial statement block,
whereas always can be used as a standalone block. All initial statements are executed
concurrently at time t =0 and the delays of one initial block do not affect the other initial block.
On the other hand the delays in one initial block containing begin and end are added.

5
The output of the simulation is shown below. Note that the clear signal resets the count to zero.

The waveforms are also shown below:

6
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Data Flow Modelling, Counters: Points To Remember

Uploaded by

Data Flow Modelling, Counters: Points To Remember

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DATA FLOW MODELLING, COUNTERS

DATAFLOW MODELLING (CONTD)

Example: Ripple Counter

Verilog Code for T-flipflop

The waveforms are also shown below:

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