Solid-State Electronics 117 (2016) 2–9

Contents lists available at ScienceDirect

Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

Ultra-thin body & buried oxide SOI substrate development

and qualification for Fully Depleted SOI device with back bias capability
Walter Schwarzenbach ⇑, Bich-Yen Nguyen, Frederic Allibert, Christophe Girard, Christophe Maleville
Soitec | Parc Technologique des Fontaines, 38190 Bernin, France

a r t i c l e i n f o a b s t r a c t

Article history: This paper reviews the properties of the SOI wafers fabricated using the Smart CutTM technology, with
Available online 24 December 2015 ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS platform. It focuses on the param-
eters that require specific attention for this technology, namely, the top silicon layer thickness uniformity
and buried oxide reliability. The first one is linked to the threshold voltage variability and the second to
the active role played by the BOX when a back-bias is used. An overview of the specific process optimiza-
tion and metrology developed to achieve the targeted specifications is given.
Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction (FD-SOI) [3] and FinFET on Bulk Silicon [4] or on SOI starting wafers
[5].
Portable, digital electronics and wireless communication mar-
kets have increased tremendously in the last five years, driving
worldwide semiconductor sales in 2015 to over $350B according 2. Planar Fully Depleted devices for extending CMOS scaling
to the Semiconductor Industry Association [1]. Electronic con-
sumers demand for more functionality, smaller form factor or FD-SOI with ultra-thin BOX (Buried OXide), known as Ultra-
lighter weight, longer battery life and lower cost. This means tran- Thin-Body and BOX (UTBB) substrate, is an attractive candidate
sistor scaling should follow Gordon Moore’s law and Robert Den- for extending Moore’s Law at 28 nm and beyond while keeping
nard’s scaling rule without compromising performance, power, the cost benefit from shrinking. FD-SOI devices represent an exten-
area or cost. However, as gate lengths approach sub-45 nm dimen- sion of the planar device architecture demonstrating several key
sions and gate oxides approach 1 nm, scaling becomes more chal- advantages needed for low power and ultra-low power circuits.
lenging, and new material and device structures are required to FD-SOI devices have excellent immunity to soft-error-rate and
overcome the fundamental physical limitations imposed by tradi- short channel effects leading to improved sub-threshold swing
tional semiconductor materials. The obstacles to continuing the and drain-induced barrier lowering, thus it improves performance
reduction of transistor dimensions can be traced to threshold volt- and/or power. FD-SOI devices also use the undoped channel result-
age and gate oxide thickness that cannot be scaled at the same rate ing in much lower threshold voltage variation due to minimizing
as supply voltage (Vdd) without leakage current exceeding stand-by random dopant fluctuation [6,7]. This enables operation-voltage
power requirements for portable electronics applications. Thus, scaling for reducing active power consumption and improves
transistor scaling rapidly reduces the maximum gate overdrive fac- SRAM and analog mismatch and gain, allowing superior digital/
tor, Cox (Vdd–VT) [2] or transistor drive current (Id), which is a mea- analog co-integration and area saving [8]. Other unique feature
sure of device/circuit performance. Moreover, higher channel of FD-SOI on thin BOX substrate is the back-bias capability [9],
doping concentrations and more abrupt, shallow source-drain which enables threshold voltage (VT) tuning for better perfor-
junctions used to control short-channel effects at very short gate mance/power trade-off without degradation (Fig. 1) and more cost
lengths result in carrier mobility degradation, increasing threshold effective solution than fabricating different VT transistors using
voltage variability, junction leakage, and capacitance. In response, channel doping or work-function tuning [7]. The flexibility allowed
many in the industry have switched to Fully-Depleted transistors by the back-bias, and the intrinsic value of the technology for
for better short channel effect and smaller variability. Two flavors energy efficient computing have been illustrated through several
have been proposed: planar Fully-Depleted Silicon-On-Insulator applications, including an FPGA (Field-Programmable Gate Array)
demonstrating successful operation down to voltages at and below
the minimum energy point of the circuit [10]. Compared to the
⇑ Corresponding author. standard 1.2 V operating voltage of the FPGA, a 13 reduction in

http://dx.doi.org/10.1016/j.sse.2015.11.008
0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.
 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9 3

Fig. 1. (a) FD-SOI with back bias [11], (b) ion vs. Ioff with back-bias up to ±2 V [12].

Power-Delay-Product was achieved through a combination of low 3.1. SOI product roadmap
voltage operation and fine-grained back-biasing, enabled by the
very thin BOX. SOI product roadmap for Planar Fully Depleted devices,
Another illustration came from a direct comparison between reported on Fig. 3, includes several product generations. UTBOX,
28 nm LPDC (Low-Density Parity-Check) decoders fabricated or UTBB substrates are designed for initial technology nodes start-
simultaneously in bulk and FD-SOI technologies [11]. Flatresse ing at 28 nm, including thin unstrained SOI and BOX layers on high
et al. demonstrated, on 28 nm FDSOI, 49% power reduction or quality silicon substrates with adapted orientation. These materi-
35% speed gain versus 28 nm bulk for performance oriented als are now in High Volume Manufacturing production or in risk
designs and 10X leakage reduction versus bulk for low standby production mode in Soitec lines. Soitec’s product roadmap already
power applications. anticipates advanced material needs, including the use of high
The planar FD-SOI devices are fully compatible with main- mobility materials with strained Si and SiGe ([Ge] up to 80%,
stream CMOS processing, designs and EDA tools. This allows including tensile or compressive strains) top layers. These engi-
retaining a low-disruption planar approach for low process/design neered substrates serve as basis for advanced device integration
cost and fast time to market, but it puts tight requirements on schemes targeting boosted performance [17,18].
starting wafers, which demands extremely thin and uniform sili-
con and buried oxide layers. Wafer manufacturers have worked
3.2. SOI thickness metrology
to fulfill these needs and are now able to reach atomic-level control
of thin silicon and oxide thicknesses. These wafers are in produc-
To ensure low transistor VT variability, SOI thickness monitoring
tion ramp and ready for high volume manufacturing. This paper
across the full spatial frequency range is required. This range of
reviews the Smart CutTM process optimization, quality of the thin
spatial frequencies corresponds to dimensions (or wavelengths)
SOI and BOX substrate, and substrate roadmap for scaling down
from 10 nm to 30 cm (wafer size) to fully cover the within-
to 10 nm node.
wafer thickness uniformity. It is also necessary to cover the
average wafer-to-wafer thickness variations. Fig. 4 illustrates such
3. Smart CutTM process for FD-SOI substrate spatial frequency domains with corresponding metrology & and
typical variations [15].
The Smart CutTM process, Fig. 2, is based on wafer bonding and At wafer level, ellipsometry gives access to SOI & BOX thick-
hydrogen implantation to transfer an ultra-thin silicon on oxide nesses. Using a properly defined 41 pts (points) map, as described
layer from a defect free high quality donor substrate to a handle on Fig. 5a, allows a correct evaluation of the within-wafer thick-
wafer. This uses the same Smart Cut process-steps as other SOI ness range. This is confirmed by comparing measurements results
products (partially depleted SOI devices), which have been in high obtained with said 41 pts map (Fig. 5b) to a more detailed mapping
volume manufacturing for well over a decade. Thus FD-SOI sub- (725 pts, Fig. 5c). Both maps yield the same measurement accu-
strate development benefited from 20 years of layer-transfer learn- racy, exhibiting ±0.5 nm wafer scale thickness variations. The
ing and volume production expertise. However, extensive 41 pts map obviously gives a higher measurement throughput
optimization of the Smart CutTM process is still essential for deliv- (tens of wafers per hour, >15 times faster w.r.t. 725 pts), to be com-
ering ultra-thin SOI and BOX films with well controlled wafer-to- patible with industrial requirements.
wafer and within-wafer uniformity [13]. To retain the excellent Since the ellipsometer is capable of covering wavelengths rang-
VT variation and for tightening performance/leakage distribution, ing from sub-millimeter to tens of centimeters, it enables unifor-
an SOI film uniformity within ±5A (3-sigma) is required and has mity inspection covering spatial wavelength corresponding to
been demonstrated [14,15]. To meet these requirements, the pro- ‘‘die-to-die” and ‘‘wafer-to-wafer” scales.
cess focuses on (1) a highly uniform thermal oxidation of a donor At sub-micrometer level (typically below 5 lm wavelength),
wafer to form the thin BOX with good electrical properties; (2) a well known atomic force microscopy metrology can be used to
conformal hydrogen implant through the oxide to define the sepa- monitor device-scale thickness variations. Fig. 6 shows excellent,
ration plane in the silicon, (3) a high temperature anneal to elimi- <1 A RMS on 30  30 lm2 scan, results obtained on FD-SOI sub-
nate the local SOI roughness while keeping excellent on-wafer SOI strates [19]. However, AFM only gives access to the surface varia-
uniformity. Further tightening of the wafer-to-wafer average thick- tions, not to the SOI film thickness variations. Though surface
ness distribution is then obtained through Adaptive Process Con- roughness is relevant to transistor properties, Si uniformity is the
trol (APC), which consist in tuning the finishing steps according main parameter of interest.
to the average wafer thickness after the high temperature anneal To address the SOI uniformity in a wavelength range from 1 lm
[16]. to 100 lm, a dedicated measurement technique called differential
4 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9

SOI Thickness Uniformity Driver Adapted to BOX film thickness

Roughness Driver

Fig. 2. Smart CutTM process adapted for FD-SOI material.

Fig. 3. Soitec product roadmap for FD-SOI substrates.

reflective microscopy (DRM) was developed. It enables measuring ±0.1 nm. Fig. 8 describes the tailored cleaning, specifically imple-
the thickness in a range of wavelengths covering the within-die mented. This APC module implemented in the FD-SOI line does
and cell-to-cell variability. The technique is based on the variation not induce any significant cost & cycle time impact and can be
of the intensity of the reflected light when the SOI layer thickness adapted on either batch or single wafer cleaners. Processes are
varies. To maximize the measurement’s precision, the wavelength fully automated.
is selected such that sensitivity to BOX thickness variations is min- Fig. 9 shows typical mean SOI thickness distribution on 10,000
imized. Associated with an optical microscope, digital camera, and production wafers, with and without such specific treatment,
proper image-treatment algorithms, it leads to average, sigma & demonstrating a wafer to wafer variation improved down to
peak to valley SOI thickness output over a typical 80  60 lm2 field ±0.1 nm.
of view [20,21]. This methods, schematically described on Fig. 7, is
now routinely available for production monitoring, on various 3.2.2. SOI thickness control at wafer scale – within-wafer uniformity
FD-SOI thickness stacks. FD-SOI tight within-wafer uniformity is obtained through an
optimization of the process steps, previously described on Fig. 2,
3.2.1. SOI thickness control at wafer scale – wafer-to-wafer combining [22].
Applications based on PDSOI wafers have high thickness-
uniformity requirements, typically ±1 nm wafer-to-wafer [16]. – Near-perfect condition for oxide growth, which leads to (i) BOX
This was achieved thanks to process and line optimization and layer uniformity (Fig. 10a) and (ii) reduction of the implantation
tool-to-tool matching. depth (i.e. fracture plane) variations.
With FD-SOI, thickness uniformity requirements become extre- – Optimized implant & splitting anneals for post splitting perfor-
mely stringent and wafer to wafer variations are reduced down to mance (Fig. 10b).
 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9 5

SOI

Box

Handle wafer

WtW WiW DRM AFM µm-1

Ellipso 10-6 Ellipso 10-2 1

Performance +/-5 Å 6-10 Å P-V < 1.0 Å RMS

127.5 Minimum/wafer
Average/wafer
Maximum/wafer
125.0
SOI thickness(Å)
122.5

Illustration 120.0

117.5

115.0

112.5

Fig. 4. SOI layer thickness control.

(a) (b) (c)

+/- 5 Å

Fig. 5. (a) 41 pts ellipsometry mapping (b) 41 pts mapping (c) 725 pts extended SOI thickness map of production 120/250 A SOI/BOX wafer. Both mapping show thickness
variation range within 1 nm.

wafers. To keep things in perspective, this means less than 5 silicon

inter-atomic distances over a 300 mm wafer.

3.2.3. SOI thickness control at device scale – roughness & high

frequency variability
Device scale thickness variation is monitored through micro-
roughness performance, including AFM & DRM metrologies. In
addition to conventional Smart Cut process step optimizations,
several finishing options have been evaluated, aiming to reduce
the final SOI surface roughness while keeping excellent on-wafer
SOI uniformity and industrial capability [23].
The use of Chemical-Mechanical-Polishing processes allow
excellent roughness performance but currently induces significant
on-wafer SOI uniformity degradation, even with limited Si
removal. As shown on Fig. 12, the on-wafer uniformity is steadily
degraded after incremental thickness removals.
Thermal smoothing through the surface diffusion process, as
described by Mullins–Herring surface diffusion equation [24],
Fig. 6. AFM scan, 30  30 lm2, on FD-SOI substrate. allows reducing surface roughness with a limited impact on
wafer-scale SOI uniformity. Fig. 13 shows AFM results on several
UTBOX substrate options. In contrast to the P0.3 nm RMS on
– Adapted finishing steps (sacrificial oxidation steps, smoothing 30  30 lm2 fields Partially Depleted SOI products, UTBOX for
anneal process) (Fig. 10c). Fully Depleted applications exhibits a 0.08 nm 30  30 lm2 RMS.
Corresponding peak-to-valley performance, as measured with
Fig. 10 shows typical on-wafer film and BOX thickness unifor- DRM metrology, is improved from 2 nm (PDSOI) down to 0.8 nm
mity evolution across the SmartCut process flow, for a single sub- (FD-SOI substrates).
strate in the median of the production distribution. Thus, Fig. 14 illustrates, through a Power Spectral Density (PSD)
Combining wafer to wafer & within wafer thickness variations, vs. Spatial frequency curve from a 30  30 lm2 AFM scan, that
Fig. 11 illustrates a ±0.5 nm SOI thickness control, all points, all Smart Cut finishing process optimization allows FD-SOI substrate
wafers, over an FD-SOI manufacturing volume of thousands of to reach a surface smoothness similar to polished bulk.
6 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9

(a) (b) 88 µm

66
µm

135
Microscope calibration (d) PV : 8 A
(c)
130

125
Ellipso thk, A

120

115 Elipso
Theory, 540nm
110

105

100
6000 7000 8000 9000 10000 11000 12000
Grey scale

Fig. 7. DRM schematics, (a) SOI & BOX reflectivity vs wavelength for 120/250 A stack, (b) typical gray scale optical microscope field of view, (c) digitalized gray scale vs
thickness correlation, (d) 120/250 thickness variation scan [20].

Finishing process flow description Cleaning #1

Sacrificial Thickness
Final sorting
oxidation measurement

Cleaning #N
Final thickness fine adjustment
Process step

Fig. 8. Specific FD-SOI cleaning tailoring schematics for wafer to wafer thickness control.

(a) (b)

0
-15 A -10 A -5 A Target +5A + 10 A + 15 A -15 A -10 A -5 A Target +5A + 10 A + 15 A
Mean SOI Thickness (A) Mean SOI Thickness (A)

Fig. 9. Wafer to wafer SOI mean thickness distribution, (a) PDSOI generation, (b) FD-SOI generation.

3.3. UTBOX defect density performance further reduced. Initial measurements on SP5 show promising
results, for even lower threshold inspection down to 29 nm.
SOI surface defectivity is measured with a threshold as low as
50 nm using KLA Tencor SP3Ò tools [25]. SOI defectivity is reduced
3.4. BOX layer – extended scale & electrical reliability
through the optimization of all Smart Cut conventional process
steps: oxidation, implant – splitting, bonding & finishing. It allows
FD-SOI substrates for 28FD & 22FD technology nodes are
UTBOX materials to reach best bulk quality levels. Fig. 15 compares
designed with a BOX layer of 25 or 20 nm. BOX layer thickness is
defectivity distribution measured on an SP3 at 50 nm threshold on
controlled within ±1 nm. BOX thickness reduction down to
polished silicon bulk and on final 12/25 nm UTBOX substrate. As
10 nm has been developed using the Smart Cut process, in order
advised by the ITRS roadmap, measurement threshold should be
to enable the FD scaling path thanks to improved electrostatic
 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9 7

σ = 0.25 Å σ = 1.08 Å σ = 1.30 Å

Range = 0.79 Å Range = 4.53Å Range = 5.62 Å
(a) (b) (c)

Fig. 10. Ellipsometry 41 pts within-wafer uniformity over process steps, showing a thickness range of (a) 0.08 nm after BOX formation, (b) 0.45 nm after splitting and (c)
0.56 nm on finished SOI [22].

Fig. 11. Production FD-SOI wafers: thickness distribution [22].

Fig. 12. On wafer uniformity & micro-roughness measured through SP2 Haze vs.
CMP Si removal [23].
Fig. 14. Power spectral density (PSD) from 30  30 lm2 AFM scans for polished
bulk, PDSOI & FD-SOI substrates [23].

Fig. 15. Measured SP3 defectivity distribution @ 50 nm threshold on (left) Si bulk &
Fig. 13. AFM micro-roughness performance vs finishing thermal smoothing [23]. (right) final UTBOX [23].
8 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9

UTBOX25 UTBOX10
SOI Layer SOI Layer

25 nm BOX Layer
BOX Layer 10 nm

Si Substrate

Fig. 16. BOX TEM cross section for (left) UTBOX25 & right (UTBOX10) [24].

Oxidized Bulk range control via the back gate [26]. Fig. 16 shows typical TEM cross sections
of BOX 25 nm & 10 nm thicknesses, associated with ultra-thin SOI.
Buried oxide layer benefits for PDSOI substrate include device
to device and device to substrate electrical isolation, leading to
possible isolation of 3D structures. For FD-SOI applications, BOX
layer electrical reliability checklist needs to take into account the
active role associated with back-bias modulation. In addition to
good resistance to breakdown, low leakage, low electrical pinhole
Qbd (C/cm²) density requirements from previous substrate generations, [27]
BOX layer needs to demonstrate good ageing behavior through
Fig. 17. UTBOX charge to breakdown, BOX 25 nm, with reference to oxidized bulk charge to breakdown (Qbd) & time dependant electrical break-
(light gray band). down (TDDB) measurements.
Charge to breakdown (Qbd) values up to 10 C/cm2 are measured
on finished 25 nm BOX FD-SOI substrates [27]. Fig. 17 reports such
distribution, as measured on finished FD-SOI materials from vol-
ume production, similar to 6–10 C/cm2 25 nm oxidized bulk
reference.
Fig. 18 reports the high-field BOX TDDB measurements along
with the low-field extrapolation, assuming a linear relationship
between breakdown and electric field [28]. On a 25 nm BOX, an
operating voltage of 16.5 V is derived to reach the 10 years lifetime
requirements, which is well above the actual back-bias voltages
(±3 V) and similar to values obtained on an oxidized and annealed
silicon reference, confirming reliability retention after the Smart
Cut process.
Fig. 19 reports consistent & stable DIT & QBOX values, from C(V)
measurements, on both Partially & Fully Depleted SOI technologies,
whatever BOX thickness, in the absence of forming gas anneal.
These expected low values, observed at the end of the SOI fabrica-
Fig. 18. TDDB, oxidized bulk & FD-SOI substrate [27].
tion process, are related to relatively high thermal treatments
occurrence.

(a) (b)
QBOX DIT
[cm-2] [eV-1.cm-2]
FDSOI PDSOI FDSOI PDSOI

BOX Thickness (nm) BOX Thickness (nm)

Fig. 19. (a) QBOX & (b) DIT measured vs BOX thickness [27].
 W. Schwarzenbach et al. / Solid-State Electronics 117 (2016) 2–9 9

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[9] Liu Q et al. Symp VLSI Tech; 2011. p. 160.
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