IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.

2, FEBRUARY 2016 1203

A New Hybrid Boosting Converter for Renewable

Energy Applications
Bin Wu, Student Member, IEEE, Shouxiang Li, Student Member, IEEE,
Yao Liu, and Keyue Ma Smedley, Fellow, IEEE

Abstract—A hybrid boosting converter (HBC) with collective ad- unique advantages and limitations. The switched capacitor
vantages of regulation capability from its boost structure and gain dc–dc converter can achieve high efficiency but has pulsat-
enhancement from its voltage multiplier structure is proposed in ing current and poor regulation capability. Introduction of
this paper. The new converter incorporates a bipolar voltage mul-
tiplier, featuring symmetrical configuration, single inductor and resonant switched-capacitor converter can alleviate the pul-
single switch, high gain capability with wide regulation range, low sating current but does not solve the regulation issue [13].
component stress, small output ripple and flexible extension, which The tapped-inductor and transformer facilitates gain boost-
make it suitable for front-end PV system and some other renewable ing function but requires snubber circuit to handle leakage
energy applications. The operation principal, component stress, problem [14]. The combination of above technologies usu-
and voltage ripple are analyzed in this paper. Performance com-
parison and evaluation with a number of previous single-switch ally yields promising circuit features but with excessive num-
single-inductor converters are provided. A 200-W 35 to 380 V ber of components [12]. In this paper, gain enhancement
second-order HBC prototype was built with peak efficiency at technology based on modification of traditional boost con-
95.44%. The experimental results confirms the feasibility of the verter while maintaining single inductor and single switch is
proposed converter. investigated, targeting at simplifying the circuit design, reduc-
Index Terms—Bipolar voltage multiplier (BVM), hybrid boost- ing the cost, satisfying the demands of normal high gain appli-
ing converter (HBC), nature interleaving, renewable energy, single- cations, and facilitating mass production.
switch single inductor. The idea of gain enhancement from a boost converter started
from quadratic boost [15]. It achieved higher voltage gain with
I. INTRODUCTION a single switch, yet introduced high component voltage stress.
Nevertheless, this converter motivated high gain converter de-
N recent years, the rapid development of renewable energy
I system calls for new generation of high gain dc/dc converters
with high efficiency and low cost. The front end of “Plug and
velopment follow on.
Many gain extension methods of boost converter by adding
only diodes and capacitors were investigated in the past. The
Play” PV system usually demands step-up converter which is method of combining boost converter with traditional Dick-
capable of boosting the voltage from 35 to 380 V with regulation son multiplier and Cockcroft–Walton multiplier to generate new
capability due to the low terminal voltage and the requirement of topologies were proposed in [16], such as topologies in Fig. 1(a)
MPPT tracking function for single PV panel. Considering a wind and (b). Air core inductor or stray inductor was used within
farm with internal medium-voltage dc (MVDC)-grid system, a voltage multiplier unit to reduce current pulsation in [17]. An
MVDC converter able to boost the voltage from 1–6 to 15–60 kV elementary circuit employing the super lift technique was pro-
is required to link the output of generator-facing rectifier to the posed in [18] and extended to higher gain applications such
MVDC line [1]. Some other energy storage systems such as fuel as Fig. 1(c). Its counterpart of negative output topology and
cell powered system also require high-gain dc/dc converter due double outputs topology were proposed and discussed in [19]
to their low voltage level at storage side. and [20]. The concept of multilevel boost converters was in-
In order to achieve high voltage conversion ratio with high vestigated in [21] and the topology of Fig. 1(d) was given as
efficiency, many high gain enhancement techniques were inves- central source connection converter. Besides, two switched ca-
tigated in the previous publications. Among them, switched- pacitor cells were proposed in [22] and numerous topologies
capacitor structure [2], [3], tapped/coupled inductor-based were derived by applying them to the basic PWM dc–dc con-
technique [4], [5], transformer-based technique [6], [7], volt- verters. Typical topologies are shown as Fig. 1(e) and (f). A
age multiplier structure [8], [9] or combinations of them [10]– modified voltage-lift cell was proposed in [23] and the topology
[12] attracted significant attentions. Each technology has its of Fig. 1(g) was produced.
Manuscript received November 24, 2014; revised January 30, 2015; accepted Inspired by the above topologies, a new hybrid boosting con-
March 24, 2015. Date of publication April 8, 2015; date of current version verter (HBC) with single switch and single inductor is proposed
September 29, 2015. Recommended for publication by Associate Editor M. M. by employing bipolar voltage multiplier (BVM) [32] in this pa-
Peretz.
The authors are with the Department of Electrical Engineering and Com- per. The second-order HBC is shown as Fig. 1(h). Compared
puter science, University of California, Irvine, CA 92617 USA (e-mail: with other listed topologies in Fig. 1, the proposed converter de-
binw1@uci.edu; shouxial@uci.edu; yaol9@uci.edu; smedley@uci.edu). creases the voltage rating of output filter capacitor and exhibits
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. the nature interleaving operation characteristics. Compared with
Digital Object Identifier 10.1109/TPEL.2015.2420994 the converter in Fig. 1(d), the proposed converter has smaller

0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
1204 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

Fig. 1. Previous high-gain dc–dc converters with single-switch single-inductor and proposed topology. (a) Boost + Dickson multiplier [16], (b) Boost +
Cockcroft–Walton multiplier [16], (c) superlift with elementary circuit [18], (d) central source multilevel boost converter [21], (e) Cuk derived [22], (f) Zeta derived
[22], (g) modified voltage lifter [23], and (h) proposed second-order HBC.

output ripple and higher components utilization rate with re- mance analysis such as components stress, voltage ripple and
spect to conversion ratio. Some interleaving technologies for circuit comparison are presented in Section IV. Simulation and
ripple reduction and power expansion were reported in the liter- experimental results are given in Section V and the conclusion
ature [24], [25], but these methods are normally based on circuit is drawn in Section VI.
branch expansion which requires more components. The pro-
posed topology has achieved smaller ripple with single switch
and single inductor while maintaining high voltage gain. II. PROPOSED GENERAL HBC TOPOLOGY AND ITS
Recently, many more structures achieving higher gain were OPERATIONAL PRINCIPAL
also reported [26]–[31], but they adopted at least two inductors The proposed HBC is shown in Fig. 2. There are two ver-
or switches, or some are based on tapped inductor/transformer, sions of HBC, odd-order HBC and even-order HBC as shown
which may complicate the circuit design and increase cost. in Fig. 2(a) and (b). The even-order topology integrates the in-
This paper is organized as follows: Section II gives the general put source as part of the output voltage, leading to a higher
topology of basic HBC and discusses the operation principal. components utilization rate with respect to the same voltage
The steady-state analysis is given in Section III. Circuit perfor- gain. However, they share similar other characteristics and
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1205

Fig. 4. Bipolar voltage multiplier. (a) Positive multiplier. (b) Negative

multiplier.

two “complimentary” PWM voltage waveforms at port AO and

port OB. Although the two voltage waveforms have their indi-
vidual high voltage level and low voltage level, the gap between
two levels is identical, which is an important characteristic of
inductive switching core for interleaving operation.

B. BVM
A BVM is composed of a positive multiplier branch and a
negative multiplier branch, shown in Fig. 4(a) and (b). Positive
multiplier is the same as traditional voltage multiplier while
the negative multiplier has the input at the cathode terminal of
cascaded diodes, which can generate negative voltage at anode
Fig. 2. Proposed general HBC topology. (a) Odd-order HBC. (b) Even-order terminal, shown in Fig. 4(b).
HBC. By defining the high voltage level at input AO as VOA+ , the
low voltage level as VOA− , and the duty cycle of high volt-
age level as D, the operational states of the even-order positive
multiplier is derived as Fig. 5 and illustrated as following:
1) State 1 [0, DTs]: When the voltage at port AO is at
high level, diodes Dia (i = 2k − 1, 2k − 3 . . . 3, 1) will be con-
ducted consecutively. Each diode becomes reversely biased be-
fore the next diode fully conducts. There are K substates resulted
as shown in Fig. 5(a).
Capacitor Cia (i = 2, 4 . . . 2k) are discharged during this
time interval. Assuming the flying capacitors get fully charged at
steady state and diodes voltage drop are neglected, the following
relationship can be derived:
Vc1a = VAO+ (1)
Fig. 3. Inductive three-terminal switching core.
Vcia = Vc(i+1)a (i = 2, 4, 6, ..., 2k − 2). (2)
2) State 2[dTs, Ts]: When the voltage at port AO steps to
circuit analysis method. Therefore, only even-order topology
low level, diode D2 k a is conducted first, shown as Fig. 5(b)-
is investigated in this paper.
(1). Then the diodes Dia (i = 2, 4, . . . 2k − 2) will be turned
on one after another from high number to low. Each diode
A. Inductive Switching Core
will be turned on when the previous one becomes blocked.
In a HBC topology, the inductor, switch and input source serve Only diode D2k a is conducted for the whole time interval of
as an “inductive switching core,” shown as Fig. 3. It can generate [0, dTs], since capacitor C(2k −1)a has to partially provide the
1206 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

Fig. 5. Operation modes of even-order BVM positive branch. (a) State 1[0, DTs]. (b) State 2[DTs,Ts].

load current during the whole time interval. Even though not C2a(eq ) is equivalent to a single diode C2a(eq ) . Similarly, the
all the diodes are conducted and blocked at the same time, the capacitor group Cia (i = 1, 3, . . . 2k − 1) can be replaced by
flying capacitors still have the following relationship by the end an equivalent capacitor C1a(eq ) and diode group Dia (i =
of this time interval: 1, 3, . . . 2k − 1) by D1a(eq ) . The final equivalent even-order
positive multiplier branch is given as Fig. 6(a). A similar
Vc2a = Vc1a − VAO− (3)
analysis yields the equivalent negative multiplier branch as
Vcia = Vc(i+1)a (i = 3, 5, 7, . . . , 2k − 1). (4) shown in Fig. 6(b).
According to (1)–(4), the voltage of equivalent capacitors
According to charge balance principal, the total amount of
C1a(eq ) ,C2a(eq ) can be expressed as following:
electrical charge flowing into capacitors Cia (i = 2, 4, . . . 2k)
should equal to that coming out from them in a switching period Vc2a(eq ) = k(VAO+ − VAO− ) (6)
at steady state, therefore
Vc1a(eq ) = (k − 1)(VAO + − VAO− ) + VAO+ . (7)
 k  DT S k  TS

i2ia dt = i2ia dt. (5) For the negative branch shown in Fig. 6(b), the following
0 D TS
i=1 i=1 results can be obtained based on similar analysis:
Thus, the capacitor group Cia (i = 2, 4 . . . 2k) can be re-
Vc2b(eq ) = k(VOB+ − VOB− ) (8)
placed by an equivalent capacitor C2a(eq ) .The diode group
Dia (i = 2, 4 . . . 2k) which provides the charging path for Vc1b(eq ) = (k − 1)(VOB+ − VOB− ) + VOB+ (9)
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1207

According to KCL in Fig. 5(b), voltage ripple of capacitors

Cia (i = 2, 4 . . . 2k) can be obtained
⎧
⎪
⎪ CΔVc2a = (i2k a(off ) + i2k −2a(off ) + . . . i4a(off )
⎪
⎪
⎪
⎪ + i2a(off ) )D TS
⎪
⎨
⎪ CΔVc4a = (i2k a(off ) + i2k −2a(off ) + . . . i4a(off ) )D TS
⎪
⎪
⎪
⎪ ···
⎪
⎪
⎩
CΔVc2k a = i2k a(off ) D TS
(17)
Fig. 6. Equivalent circuit. (a) Even-order positive multiplier. (b) Even-order 
negative multiplier. where D = 1 − D.
Based on the equations from (14) to (16), the equation group
(17) can be reduced to the following expression:
where VOB+ is the high voltage level of input port OB and VOB− ⎧
⎪ CΔVc2a = (k − 1 + D)IO TS
is the low voltage level. ⎪
⎪
⎪
⎨ CΔVc4a = (k − 2 + D)IO TS
3) Equivalent Capacitance Derivation: Assuming capacitors
Cia (i = 1, 2, 3, . . . 2k) have the same capacitance C, in order . (18)
⎪
⎪ ···
to derive the equivalent capacitance of C2a(eq ) and C1a(eq ) in ⎪
⎪
⎩ CΔVc2k a = (0 + D)IO TS
expression of C, a voltage ripple-based calculation method is
proposed in this section. Assuming the peak to peak voltage
Substituting (10) to (18), the following equation is derived:
ripple of the flying capacitors can be expressed as ΔVcia (i = 
1, 2, 3 . . . 2k), the ripple of equivalent capacitor C2a(eq ) is ΔV , k(k − 1)
CΔV = + kD IO TS . (19)
the following relationship can be approximated: 2
Meanwhile, the following equation can be derived based on
ΔV = ΔVc2a + ΔVc4a + . . . ΔVc2k a . (10)
discharging stage of equivalent capacitor C2a(eq ) :
In Fig. 5, assuming the average current of iia (i = 1, 2, C2a(eq ) ΔV = IO DTS . (20)
3 . . . 2k) during [0, dTs] is (i = 1, 2, 3 . . . 2k) i2ia(on) and
the average current of iia (i = 1, 2, 3 . . . 2k) during [dTs, Ts] Based on (19) and (20), the equivalent capacitor C2a(eq ) can
is iia(off ) (i = 1, 2, 3 . . . 2k), according to charge balance of be expressed
capacitorsCia (i = 2, 4 . . . 2k), it can be derived that 2D
C2a(eq ) = C. (21)

k(k − 1 + 2D)
iia(on) DTS = iia(off ) D TS (i = 2, 4, . . . 2k). (11)
Similarly, in order to derive the equivalent capacitance of
At the same time, state 1 gives C1a(eq ) , the following equation can be derived:
⎧
⎪
⎪ CΔVc1a = kIO TS
iia(on) = i(i+1)a(on) (i = 2, 4, . . . 2k − 2). (12) ⎪
⎪
⎨ CΔVc3a = (k − 1)IO TS
. (22)
State 2 gives ⎪
⎪ · · ·
⎪
⎪
⎩
CΔVc2(k −1)a = IO TS
iia(off ) = i(i+1)a(off ) (i = 1, 3, . . . 2k − 3). (13)
At the same time, the following equation exists:
Based on the (11)–(13), the following relationship can be
obtained: C1a(eq ) ΔV  = IO TS (23)

where ΔV = ΔVc1a + ΔVc3a + . . . ΔVc(2k −1)a .
i2a(off ) = i4a(off ) = . . . i(2k −4)a(off ) Therefore, the expression of C1a(eq) is obtained
= i(2k −2)a(off ) = i(2k −1)a(off ) . (14) 2
C1a(eq ) = C. (24)
(k + 1)k
Based on charge balance of capacitor C2k a , it can be derived
that Because of the symmetry, the equivalent capacitance C1b(eq )
and C2b(eq ) is given as following:
i2(k −1)a(off ) D TS = IO TS (15) 2
C1b(eq ) = C (25)
i2k a(off ) D TS = i2k a(on) DTS = Io DTS (16) (k + 1)k
2D
Vo u t C2b(eq ) = C. (26)
where Io = R . k(k − 1 + 2D )
1208 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

Fig. 7. Three operation states. (a) State 1[0, DTs]. (b) State 2[DTs, (D + D1)T s]. (c) State 3[(D + D1)T s, T s].

the inductive switching core analysis:

VAO+ = Vin (27)

VOB− = 0. (28)

2) State 2[DTs,(D + D1)Ts]: As illustrated in Fig. 7(b),

when S is turned off, the inductor current will free wheel through
diodes D2a(eq ) and D1b(eq ) .The inductor is shared by two charg-
ing boost loops. In the top loop, capacitor C1a(eq ) is releasing
energy to capacitor C2a(eq ) and load at the same time. In the
bottom loop, input source charges capacitor C1b(eq ) through the
inductor L. During this time interval, voltage generated at AO
and OB is expressed as following based on inductor balance
principal:

Fig. 8. Equivalent even-order HBC. D

VAO+ = −Vin (29)
D1
Vin (D + D1 )
The derivation of voltage and equivalent value of the equiva- VOB+ = . (30)
D1
lent flying capacitors can facilitate the output voltage calculation
and ripple estimation. 3) State 3[(D + D1)Ts, Ts]: Under certain conditions, the
circuit will work under DCM operation mode, thus the third
state in Fig. 7(c) appeals. At this state, the switch S is kept
C. Operation Principle of General Basic HBC
off. The inductor current has dropped to zero and all the diodes
Based on the simplification method discussed in previous sec- are blocked. The capacitor C2a(eq ) and C2a(eq ) are in series with
tion, the general even-order HBC in Fig. 2(b) can be simplified input source to power the load. During this time interval, voltage
to an equivalent HBC circuit, shown as Fig. 8. generated at port AO is zero while at OB is Vin .
Careful examination of the topology indicates that the two
“boost” like subcircuits are intertwined through the operation III. STEADY-STATE ANALYSIS
of the active switch S. The total output voltage of HBC is the
sum of the output voltage of two boost subcircuits plus the input A. Voltage Gain Derivation in CCM Mode
voltage. Three operation states are described as Fig. 7. In steady state, the CCM mode operation waveforms are given
1) State 1[0, DTs]: In Fig. 7(a), switch S is turned on as Fig. 9(a). The waveforms of VAO and VOB are presented based
and diodes D1a(eq ) , D2b(eq ) conduct while diodes D2a(eq ) and on operation principal analysis previously. Under CCM condi-
D1b(eq ) are reversely biased. The inductor L is charged by the tion, D1 = 1 − D = D . Based on (6) and (8), the equivalent
input source. Meanwhile, capacitor C1a(eq ) is charged by input voltage of C2a(eq ) and C2b(eq ) is obtained as
source and capacitor C2b(eq ) is charged by capacitor C2b(eq ) . At
this interval, the following equations can be derived based on Vin
Vc2b(eq ) = k (31)
D
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1209

In Fig. 9(b), the inductor current can be expressed as following

during state 2:
IL = ID 2a(eq ) + ID 1b(eq ) . (35)
According to charge balance principal of the circuit
ID 2a(eq ) = ID 1b(eq ) = IO (36)
where ID 2a(eq ) and ID 1b(eq ) are the average current in the whole
switching period.
As current waveforms of ID 2a(eq ) and ID 1b(eq ) should both
have triangle shape, they will share same peak current value,
which is half of the inductor peak current. Therefore
1 Vin
ID 2a(eq )p−p = ID 1b(eq )p−p = DTS . (37)
2 L
The average current of ID 2a(eq ) in a switching period is IO ,
thus
1 1 Vin 1
D1 TS DTS = IO . (38)
2 2 L TS
This can be simplified to
4IO L
D1 = . (39)
Vin TS D
Substituting (37) to (32), the following equation can be
derived:

Vin2 D2 TS
Vout = Vin + 2k Vin + . (40)
4IO L
Solving the (38) gives the voltage gain in DCM mode

2
Vout 2k + 1 + (2k + 1)2 + k 2D LT S R
= . (41)
Vin 2

C. BRM Mode Analysis

In order to derive boundary condition for CCM and DCM
mode, the average power balance is used
Vin (IL + ID 1a(eq ) ) = Vout IO (42)
where ID 1a(eq ) =IO = V R
out
.
Fig. 9. Key waveforms. (a) CCM. (b) DCM.
Thus, the average current of IL under CCM condition is
2k Vout
IL = . (43)
Vin D R
Vc2a(eq ) = k . (32)
D The current ripple of inductor is
Vin
Therefore, the voltage ratio of a general 2kth-order HBC ΔiL = DTS . (44)
2L
shown in Fig. 2(b) is derived as following:
Therefore, the CCM condition is
Vout 1 2k Vout Vin
= 1 + 2k  . (33) > DTS . (45)
Vin D D R 2L
B. Voltage Gain Derivation in DCM Mode The criteria can be rearranged as

Under DCM operation mode, the waveforms of voltage at 2L DD2

> = Kcrit (D). (46)
input port AO, OB are shown in Fig. 9(b). Based on (6) and (8), RTS 2k(D + 2k)
the voltage gain can be expressed as The curves of Kcrit (D) with k = 1, 2, 3 are shown in Fig. 10.
D + D1 It can be seen that when the voltage multiplier stage increases,
Vout = Vin + 2kVin . (34) it is easier to achieve CCM when other parameters are fixed.
D1
1210 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

TABLE I
COMPONENTS STRESS

Vm a x Ia v e Ir m s

Vin 2k I a IO √
S 2k D
D D D
D i a (i = 1, 3 . . . 2k − 1)
Vin IO
D i b (i = 2, 4 . . . 2k ) I0 √
D D
D i a (i = 2, 4 . . . 2k )
Vin IO
D i b (i = 1, 3 . . . 2k − 1) I0 √
D D

1
Cia Vin 0 IO k
DD
 
Fig. 10. K c rit (D) with variation of k. Vin i−1 1
C i a (i = 3, 5 . . . 2k − 1) 0 k− IO
D 2 DD
 
Vin i−1 1
C i b (i = 1, 3 . . . 2k − 1) 0 k− IO
D 2 DD
 
Vin i IO D
C i a (i = 2, 4 . . . 2k ) 0 k− + IO
D 2 D D
 
Vin i IO D
C i b (i = 2, 4 . . . 2k ) 0 k− + IO
D 2 D  D

Fig. 12. Voltage ripple cancellation with different duty cycle. (a) D = 0.8.
Fig. 11. Current waveforms of diodes and switch for stress calculation.
(b) D = 0.5.

IV. CONVERTER PERFORMANCE ANALYSIS

TABLE II
A. Component Stress Analysis COMPARISON OF NORMALIZED CAPACITOR VOLTAGE STRESS FOR CONVERTER

Detail analysis of components stress for the converter pro- Fig. 1 C1 C2 C3 C4 C5 Total
vides solid reference for components selection and optimiza-
tion. The components stress under CCM mode is estimated in (a) 1/3 1/3 1/3 2/3 1 8/3

this section. (b) 1/3 1/3 1/3 1/3 1/3 5/3

1 −D 2 −D 1 −D 8 − 4D
1) Diodes and Switch: According to the charge balance law (c) 1 0
3 −D 3 −D 3 −D 3 −D
of flying capacitors, all the diodes Dia (i = 1, 2, 3 . . . 2k) and
(d) 1/3 1/3 1/3 1/3 1/3 5/3
Dib (i = 1, 2, 3 . . . 2k) have the same average current IO during
one switching period. The average current during conduction (e) 1/2 1/2 1 0 0 2

state is used to calculate Irm s here. The current waveforms of (f)

D D
1 0 0
1 + 3D
diodes and switch are shown in Fig. 11. Their current stress and 1+D 1+D 1+D
3+D
voltage stress are listed in Table I. (g) D/2 1/2 1 0 0
2
2) Capacitors: According to the analysis of BVM in 1 −D 1 1 1 4 −D
Section II, the flying capacitors that are closer to inductive (h) 0
3 −D 3 −D 3 −D 3 −D 3 −D
switching core have larger charging or discharging current,
Note: C1–C4 are representing C1 a , C1 b , C2 a , C2 b for Fig. 1(h).
which exhibit larger voltage ripple. Their average charging and
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1211

TABLE III
COMPARISON OF PROPOSED SECOND-ORDER HBC AND OTHER CONVERTERS

M rip p le norm
Ms stress norm Vo u t Ts
Fig. 1 Converters Voltage gain Diodes Capacitors
= V s s t r e s s /V o u t = ΔVo u t /
RL C

3
(a) Boost + Dickson multiplier [16] 5 5 1/3 D
1 −D
3
(b) Boost + Cockcroft Walton multiplier [16] 5 5 1/3 3 + 3D
1 −D
3 −D
(c) Super-lift converter [18] 4 4 1/(3 – D) D
1 −D
3
(d) Multilevel boost converter [21] 5 5 1/3 3D
1 −D
2
(e) Cuk-derived converter [22] − 3 3 1/2 1 −D
1 −D
1+D
(f) Zeta-derived converter [22] 3 3 1/(1+D) 1 −D
1 −D
2
(g) Modified voltage lift converter [23] 3 3 1/2 D
1 −D
3 −D
(h) Proposed HBC 4 4 1/(3 – D) |2D − 1|
1 −D

B. Voltage Ripple Analysis

The output voltage ripple is determined by the ripple of equiv-
alent capacitor C2a(eq ) and C2b(eq ) , assuming the input source
has a constant voltage. As the equivalent capacitance of C2a(eq )
and C2b(eq ) are given as (21) and (26), the voltage ripple of
C2a(eq ) and C2b(eq ) can be presented as following:
IO TS
ΔVc2a(eq ) = k(k − 1 + 2D) (47)
2C
IO TS
ΔVc2b(eq ) = k(k − 1 + 2D ). (48)
2C
The final output ripple can be presented as following:
IO TS
Fig. 13. Comparison of voltage gain of converters (a)–(h). ΔVout = |ΔVc2a(eq ) − ΔVc2b(eq ) | = k |2D − 1| .(49)
C
According to the (47), when the duty cycle D is 0.5, the the-
oretical output voltage ripple is zero. The ripple examples of
D = 0.8 and 0.5 are compared in Fig. 12(a) and (b). The inter-
leaving operation has led to ripple cancelation of the capacitors
C2a(eq ) and C2b(eq ) .

C. Comparison of Proposed HBC With Previous Converters

In order to distinguish the proposed HBC converter, a com-
parison is carried out between the second-order HBC converter
and several previous published converters with single inductor
and single switch shown in Fig. 1(a)–(h). All capacitors are
assumed to have the same value C for easier comparison. The
voltage gain, component count, as well as normalized switch
stress and normalized output ripple are all listed for each topol-
ogy in Table III.
Fig. 14. Comparison of total capacitor normalized voltage stress in Table II. The absolute voltage gain curves for all topologies presented
in Fig. 1 are sketched in Fig. 13. The proposed HBC has good
gain boosting capability. However, it is difficult to judge the
discharging current can be used to estimate the RMS current, performance of each configuration merely based on the level
which is useful to evaluate power loss of each capacitor. The of its gain curve, especially with consideration of different
expressions of RMS current for each capacitor in a 2kth-order components count for different topologies. Most of the topolo-
HBC are also given in Table I. gies can extend their gain by adding more stags with a larger
1212 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

TABLE IV
PARAMETER SELECTED FOR PROTOTYPE BUILDING

Name Denomination Value

MOSEFT S 250 V/40 A, 29 m Ω(IRFP4330)

Inductor L 500 μH
Diode D1 a 200 V/20 A,VF = 0.78 V(STH2002C)
D2 a
D1 b
D2 b
Capacitor C1 a 250 V/100 μF, electrolytic capacitor
C2 a
C1 b
C2 b
Switching frequency fs 40 kHZ
Load R 722 Ω

Fig. 15. Comparison of normalized output ripple of converters (a)–(h).

between source and load, which may limit its applications in

number of capacitors and diodes. Therefore, more details should areas where common ground are not required between input
be taken into consideration to evaluate topologies, such as to- and output. Besides, due to direct connection between the input
tal normalized capacitor voltage rating and normalized output and output, the audio susceptibility may be an issue, which may
voltage ripple. require an input filter and fast control loop.
For the high gain dc–dc converters with single switch and
inductor, a critical aspect to realize high power density and low
V. EXPERIMENTAL RESULTS
cost is to decrease the physical size of capacitors. Diodes usu-
ally have comparably much smaller volume, whose effect to In order to verify the feasibility of proposed converter and its
the power density is neglected in this comparison. The voltage performance, simulation and experimental results of a second-
rating and capacitance value are the primary factors that affect order HBC converter in Fig. 1(h) are provided in this section.
the size of each capacitor. In order to compare the density of A prototype of 200 W 35 to 380 V second-order HBC was
each topology with same gain, the normalized voltage stresses built in the lab. The specifications of the prototype are listed in
of capacitors for each topology are calculated in Table II. The Table IV.
normalized voltage stress for a capacitor is defined by the ac- The experimental waveforms of drain-source voltage input
tual voltage stress of the capacitor divided by the output voltage current, input voltage and output voltage are given in Fig. 17(a).
Vout . The total normalized capacitor voltage stress is the sum Unnoticeable overshoot at voltage Vds is derived because of the
of all normalized capacitor voltage stress, which takes into ac- buffering function of capacitor C1a and C1b . The input current
count the capacitor number and voltage rating requirement. This is pulsating without terminating to zero and no rush current is
parameter can be used to evaluate the size of high gain dc–dc observed due to the operation frequency is chosen properly. The
converters with single switch and inductor. output voltage is boosted to 380 V and kept stable without high
The total normalized capacitor voltage stresses of all topolo- voltage rating filter capacitor. In Fig. 17(b), the voltage stress of
gies are sketched in Fig. 14 based on results in Table II, with four diodes is presented, which is relatively low and no voltage
variation of duty cycle. Compared with other listed topologies, overshoot is observed.
the proposed second order HBC has lowest total capacitor volt- In Fig. 18, the experimental output voltage ripple is presented
age stress in a wide range of duty cycle. This result shows the in contrast with that of capacitor C2a and C2b under different
superiority of proposed structure for high power density design. duty cycle conditions, with the output voltage maintained at
In addition to the normalized capacitor voltage stress com- 200 V to keep constant load current.
parison, the normalized output ripple comparison is given in According to the discussion in section IV-B, full ripple cancel-
Fig. 15 according to Table III. Among all the converters con- lation can be achieved under D = 0.5 condition. It is observed
sidered, the proposed HBC structure (h) has the lowest ripple in Fig. 18(a) that output ripple is nearly zero when duty cycle
in the duty cycle range of [1/3, 2/3]. When duty cycle ranges is 0.5. When duty cycle is increased to 0.8 shown as Fig. 18(b),
are higher than 2/3, only converter (e) and (f) show smaller rip- larger output ripple ΔVout is observed. The interleaved voltage
ple theoretically. However, under this condition, converter (e) ripple of C2a and C2b contributes the small output ripple for
and (f) exhibits much larger normalized total capacitor voltage proposed HBC topology.
stress and weaker gain boosting capability, as shown in Figs. 13 Under the light load condition, the HBC may enter DCM op-
and 14. erational mode easily according to discussions in Sections III-B
It should be pointed out that although the proposed HBC and C. The experimental results of BRM and DCM conditions
structure has the advantages in high power density and low are given as Fig. 19(a) and (b). Waveforms of Vout , Vin , IL and
cost design, it also has the intrinsic issue of uncommon ground Vds are presented. The efficiency curve of the prototype is tested
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1213

Fig. 16. Experimental waveforms. (a) V d s , Iin , V o u t , V in . (b) Diodes voltage: V d 2 a , V d 1 a , V d 1 b , V d 2 b .

Fig. 17. Experimental waveforms of voltage ripples: Vc 2 a , Vc 2 b ,Vo u t and driving signal Vg s under (a) D = 0.5, (b) D = 0.8.

Fig. 19. Efficiency curve with load variation (V in = 35 V, V o u t = 380 V).

VI. CONCLUSION
A new HBC composed of an inductive switching core and
BVM is proposed in this paper. The proposed converter has
the collective advantages of the gain boosting technique from
voltage multiplier and voltage regulation capability from boost
converter, featuring in nature interleaved operation, wide regu-
lation range, low component stresses, small output ripple, flex-
Fig. 18. Experimental waveforms of V o u t , V in , IL and V d s under (a) BRM ible gain extension, and high efficiency. Compared with other
condition and (b) DCM condition.
high gain boosting technologies such as tapped inductor, multi-
inductor/switch method or transformer-based method, the pro-
posed topology has reduced the complexity which is suitable
and shown in Fig. 19, with the load variation from 40 to 250 W. for mass production. Compared with other single switch and
A peak efficiency of 95.44% is achieved. single inductor dc–dc converters, it has a better component
1214 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

utilization rate, smaller output ripple and lower component [21] J. C. Rosas-Caro, J. M. Ramirez, F. Z. Peng, and A. Valderrabano, “A
stress. This paper provides operation principle, design consider- DC–DC multilevel boost converter,” IET Power Electron., vol. 3, no. 1,
pp. 129–137, Jan. 2010.
ation, and overall comparison with many other similar topolo- [22] E. Ismail and M. Al-Saffar, “A family of single-switch PWM converters
gies. A 200-W, 35 to 380 V second-order HBC prototype was with high step-up conversion ratio,” IEEE Trans. Circuits Syst. I, vol. 55,
constructed which achieved a peak efficiency of 95.44%. This no. 4, pp. 1159–1171, May 2008.
[23] S. Zhang, J. Xu, and P. Yang, “A single-switch high gain quadratic boost
converter is suitable for many renewable energy applications converter based on voltage-lift-technique,” in Proc. 10th Int. Power Energy
such as the front-end of PV system. Conf., 2012, pp. 71–75.
[24] Y. J. A. Alcazar, D. de Souza Oliveira, F. L. Tofoli, and R. P. Torrico-
Bascope, “DC–DC nonisolated boost converter based on the three-state
switching cell and voltage multiplier cells,” IEEE Trans. Ind. Electron.,
vol. 60, no. 10, pp. 4438–4449, Oct. 2013.
REFERENCES [25] W. L. W. Li and X. H. X. He, “An interleaved winding-coupled boost con-
[1] W. Chen, A. Q. Huang, C. Li, G. Wang, and W. Gu, “Analysis and verter with passive lossless clamp circuits,” IEEE Trans. Power Electron.,
comparison of medium voltage high power DC/DC converters for off- vol. 22, no. 4, pp. 1499–1507, Jul. 2007.
shore wind energy systems,” IEEE Trans. Power Electron., vol. 28, no. 4, [26] E. H. Ismail, M. A. Al-Saffar, A. J. Sabzali, and A. A. Fardoun, “High
pp. 2014–2023, Apr. 2013. voltage gain single-switch non-isolated DC-DC converters for renewable
[2] J. A. Starzyk, “A DC-DC charge pump design based on voltage dou- energy applications,” in Proc. IEEE Int. Conf. Sustain. Energy Technol.,
blers,” IEEE Trans. Circuits Syst. I Fundam. Theory Appl., vol. 48, no. 3, Dec. 2010, pp. 1–6.
pp. 350–359, Mar. 2001. [27] A. A. Fardoun and E. H. Ismail, “Ultra step-up DC–DC converter with
[3] F. L. Luo and H. Ye, “Positive output multiple-lift push–pull switched- reduced switch stress,” IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025–
capacitor luo-converters,” IEEE Trans. Ind. Electron., vol. 51, no. 3, 2034, Sep. 2010.
pp. 594–602, Jun. 2004. [28] Y. Zhao, X. Xiang, C. Li, Y. Gu, W. Li, and X. He, “Single-phase high
[4] N. Vazquez, L. Estrada, C. Hernandez, and E. Rodriguez, “The tapped- step-up converter with improved multiplier cell suitable for half-bridge-
inductor boost converter,” in Proc. IEEE Int. Symp. Ind. Electron., based PV inverter system,” IEEE Trans. Power Electron., vol. 29, no. 6,
Jun. 2007, pp. 538–543. pp. 2807–2816, Jun. 2014.
[5] R. Wai, C. Lin, R. Duan, and Y. Chang, “High-efficiency DC-DC con- [29] J.-K. Kim and G.-W. Moon, “Derivation, analysis, and comparison of
verter with high voltage gain and reduced switch stress,” IEEE Trans. Ind. nonisolated single-switch high step-up converters with low voltage stress,”
Electron., vol. 54, no. 1, pp. 354–364, Feb. 2007. IEEE Trans. Power Electron., vol. 30, no. 3, pp. 1336–1344, Mar. 2015.
[6] J. Lee, T. Liang, and J. Chen, “Isolated coupled-inductor-integrated DC– [30] Y. Zhang, J.-T. Sun, and Y.-F. Wang, “Hybrid boost three-level DC–DC
DC converter with nondissipative snubber for solar energy applications,” converter with high voltage gain for photovoltaic generation systems,”
IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 3337–3348, Jul. 2014. IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3659–3664, Aug. 2013.
[7] M. Delshad and H. Farzanehfard, “High step-up zero-voltage switch- [31] L. H. S. C. Barreto, P. P. Praca, D. S. Oliveira, and R. N. A. L. Silva,
ing current-fed isolated pulse width modulation DC–DC converter,” IET “High-voltage gain boost converter based on three-state commutation cell
Power Electron., vol. 4, no. 3, pp. 316–322, Mar. 2011. for battery charging using pv panels in a single conversion stage,” IEEE
[8] A. Lamantia, P. G. Maranesi, and L. Radrizzani, “Small-signal model of Trans. Power Electron., vol. 29, no. 1, pp. 150–158, Jan. 2014.
the Cockcroft-Walton voltage multiplier,” IEEE Trans. Power Electron., [32] B. Wu, S. Keyue, and S. Sigmond, “A new 3X interleaved bidirectional
vol. 9, no. 1, pp. 18–25, Jan. 1994. switched capacitor converter,” in Proc. IEEE Appl. Power Electron. Conf.
[9] P. Lin and L. Chua, “Topological generation and analysis of voltage mul- Expo., 2014, pp. 1433–1439.
tiplier circuits,” IEEE Trans. Circuits Syst., vol. 24, no. 10, pp. 517–530,
Oct. 1977.
[10] K.-C. Tseng, C.-C. Huang, and W.-Y. Shih, “A high step-up converter Bin Wu (S’14) was born in Zhejiang, China, in 1985.
with a voltage multiplier module for a photovoltaic system,” IEEE Trans. He received the B.S. degree in electrical engineer-
Power Electron., vol. 28, no. 6, pp. 3047–3057, Jun. 2013. ing from Zhejiang University, Hangzhou, China, in
[11] W. Li, W. Li, X. Xiang, Y. Hu, and X. He, “High step-up interleaved 2008, and the M.S. degree in power electronics from
converter with built-in transformer voltage multiplier cells for sustain- Xi’an Jiaotong University, Xi’an, China, in 2011. He
able energy applications,” IEEE Trans. Power Electron., vol. 29, no. 6, is currently working toward the Ph.D. degree in power
pp. 2829–2836, Jun. 2014. electronics at the University of California, Irvine, CA,
[12] X. Hu and C. Gong, “A high voltage gain DC–DC converter integrating USA.
coupled-inductor and diode–capacitor techniques,” IEEE Trans. Power His interests include switched capacitor converter,
Electron., vol. 29, no. 2, pp. 789–800, Feb. 2014. modeling, high gain dc–dc converter, electrical vehi-
[13] D. Cao and F. Z. Peng, “A family of zero current switching switched- cle and renewable energy integration.
capacitor dc-dc converters,” in Proc. 25th Annu. IEEE Appl. Power Elec-
tron. Conf. Expo., Feb. 2010, pp. 1365–1372.
[14] J. Yao, A. Abramovitz, and K. Smedley, “Steep gain bi-directional con-
verter with a regenerative snubber,” IEEE Trans. Power Electron., vol.
8993, no. c, p. 1, 2015.
[15] D. Maksimovic and S. Cuk, “Switching converters with wide DC
conversion range,” IEEE Trans. Power Electron., vol. 6, no. 1,
pp. 151–157, Jan. 1991.
Shouxiang Li (S’14) received the B.S. degree in elec-
[16] B. Axelrod, G. Golan, Y. Berkovich, and A. Shenkman, “Diode–capacitor
trical engineering and automation from the Beijing
voltage multipliers combined with boost-converters: Topologies and char-
Institute of Technology, Beijing, China, in 2011, and
acteristics,” IET Power Electron., vol. 5, no. 6, pp. 873–884, Jul. 2012. the M.S. degree in electrical engineering from the
[17] M. Prudente, L. L. Pfitscher, G. Emmendoerfer, E. F. Romaneli, and
University of California, Irvine, CA, USA, in 2013.
R. Gules, “Voltage multiplier cells applied to converters, non-isolated
He is currently working toward the Ph.D. degree at
DC–DC,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871–887, Mar.
the University of California, conducting his studies
2008. both in the Calit2 and the UCI Power Electronics
[18] F. L. Luo, S. Member, and H. Ye, “Positive output super-lift converters,”
Laboratory.
IEEE Trans. Power Electron., vol. 18, no. 1, pp. 105–113, Jan. 2003.
From 2012 to 2013, he was an Intern in the PMU
[19] F. L. Luo and H. Ye, “Negative output super-lift converters,” IEEE Trans.
Group of Broadcom Corporation, Irvine. From 2013
Power Electron., vol. 18, no. 5, pp. 1113–1121, Sep. 2003. to 2014, he was a Research Assistant at the UCI Power Electronics Laboratory.
[20] F. L. Luo, “Double output Luo-converters-voltage lift technique,” in
His research interests include switched capacitor converters, high-gain dc/dc
Proc. Int. Conf. Power Electron. Drives Energy Syst. Ind. Growth, 1998,
converters.
pp. 342–347.
WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS 1215

Yao Liu received the B.S. degree in electrical engi- Keyue Ma Smedley (S’87–M’90–SM’97–F’08) re-
neering from North China Electric Power University, ceived the B.S. and M.S. degrees in electrical engi-
Beijing, China, in 2013, and the M.S. degree in elec- neering from Zhejiang University, Hangzhou, China,
trical engineering from the University of California, in 1982 and 1985, respectively, and the M.S. and
Irvine, CA, USA, in 2015. Ph.D. degrees in electrical engineering from the
He is currently working at the Mixed Signal Lay- California Institute of Technology, Pasadena, CA,
out Design Group, Broadcom Corporation, Irvine. USA, in 1987 and 1991, respectively.
He has been a Research Assistant at the UCI Power She is currently a Professor at the Department of
Electronics Laboratory. His research interests include Electrical Engineering and Computer Science, Uni-
high gain dc–dc converters, renewable energy, and versity of California, Irvine (UCI), CA, USA, the
mixed signal design. Director of the UCI Power Electronics Laboratory,
and a Cofounder of One-Cycle Control, Inc. Her research interests include high-
efficiency dc–dc converters, high-fidelity class-D power amplifiers, single-phase
and three-phase PFC rectifiers, active power filters, inverters, V/VAR control,
energy storage system, and utility-scale fault current limiters. She is an inventor
of one-cycle control and the hexagram power converter. Her work has resulted in
more than 160 technical publications, more than 10 U.S./international patents,
two start-up companies, and numerous commercial applications.
Dr. Smedley is a recipient of the UCI Innovation Award 2005. Her work with
One-Cycle Control, Inc., has won the Department of the Army Achievement
Award in the Pentagon in 2010.

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