Metal Oxide Semiconductor Field Effect Transistor – (MOSFET)
Gate
L
poly
Source Drain
oxide
n channel n
Diffusion Diffusion
p substrate
1
The problem with the BJT vs MOFET
• The bipolar junction transistor has proven to be very
versatile and very capable as a digital integrated circuit
element.
• However, it has a serious problem. Its size.
– The average size of a BJT is on the order of 300 microns2.
• This is serious enough to the point that BJTs are no longer used in
the design of high density chips like microprocessors.
• The advantage of the MOFET is that it is much smaller
than the BJT.
2
The MOSFET Transistor
Source (S) Gate (G) Drain (D)
N-Type Diffusion
P-Type Substrate
n+ n+ Metal
SiO2 - Insulator
P
Substrate
• In the BJT, the base region acted as a valve by making the
two junctions either forward or reverse biased.
• In the FET, the electric field on the base is what controls the
flow of charge.
3
Basic MOS structure
Gate
Source Drain
poly
Si02
p channel p
Diffusion Diffusion
n substrate
• P-channel MOS consists of :
• a lightly doped substrate of n-type silicon.
• two regions heavily doped by diffusion with p-type impurities to
form the Source and the Drain.
• Region between two p-type sections serves as a channel. 4
Theory of Operation
• Assume that 0 volts are
applied to the source and S G D
drain and a positive n+ n+
voltage on the gate.
P
– The free holes in the
P-Type substrate are
pushed away and a Depletion
Region
Channel
depletion region is created.
– If the gate voltage is increased, the minority
electrons will be attracted to the surface and they
form a conduction channel between the N-Type
source and drain.
• It is said that the P-Type silicon at the surface goes
through an inversion and becomes more like N-Type.
5
Theory of Operation (Contd.)
• The voltage needed to
G
create this channel is S D
known as the Threshold n+ n+
Voltage VT. P
– VT is normally around 1 V for
P-Channel Devices. Depletion Channel
Region
• Once the conduction channel is created, a positive voltage
difference between the Source and Drain will get electrons
to move across the channel.
• The requirements for current flow are:
– VGS > VT and VDS > 0.
6
Theory of Operation (Contd.)
S G D
n+ n+
Pinch-off
• As VDS is increased more, the difference between VG and VD reduces.
– This will also
reduce the depth of the
channel on the drain side.
• If VDS is increased even more, the channel will disappear completely on
the drain side.
– The channel is in “pinch-off”.
7
Modes of Operation
• Cutoff
– If VGS < VT, then there is no conduction channel and the
current flow is 0.
ID = 0
• Linear Mode
– While VDS VGS – VT the device operates in the linear mode.
VDS
2
I D k (VGS VT )VDS
2
• K – Transconductance parameter OR The gain factor .
8
Modes of Operation
• Saturation
– When VGS > VT and VDS VGS – VT the device operates in
saturation modes (the channel is pinched off).
– The drain current is:
ID
k
2
(VGS VT ) 2
• What about Reverse mode?
– The drain and source of the MOSFET are fabricated
symmetrically so that they are interchangeable.
– The MOSFET does not have a reverse mode.
• The drain and source simply exchange operation.
9
Family of Curves
ID
VDS = VGS - VT
VGS=5
Linear
VGS=4
Saturation
VGS=3
VGS=2
VGS=1
VDS
VGS=0
10
Transconductance
• The transconductance parameter controls the relationship
between ID and VDS.
– The device transconductance parameter(device ) relates to
the process transconductance parameter k’ (process ) and
the device’s dimensions (width and length).
W
k k'
L
– The process transconductance parameter or process gain
factor in turn is a constant for a given process technology it
depends on the material used for manufacturing the chip.
k’ = mCOX
• m is the free charge mobility.
• COX is the oxide capacitance per unit area.
11
D+ D+
D+
VGS < VT ID=0 VGD > VT ID
VGD < VT ID
-
G+ VDS > 0 G VDS <VGS -VT -
IG=0 + G VDS >VGS -VT
+
IG=0
IG=0
VGS > VT VGS > VT
S-
S- S-
ID 0 V 2 DS
I D LIN (VGS VT ) I D SAT (VGS VT ) 2
2
VDS
2
Where ( ) is the gain factor or transconductance parameter
W
k k' k’ = μCOX
L
12
P-Channel MOSFET – PMOS
• The P-Channel MOSFET operates in exactly the same
way as the N-Channel.
– The only difference is that voltage polarities and current
directions are reversed.
• VT < 0
• Cutoff
– VSG –VT , ID = 0.
• Linear VSD
2
– VSG –VT and VSD VSG + VT I D k (VSG VT )VSD
2
• Saturation
– VSG –VT and VSD VSG + VT ID
k
(VGS VT )2
2
13
Layout of MOS devices
Gate
L
poly
Source Drain
oxide
n channel n
Diffusion Diffusion
p substrate
• Structure of an NMOS transistor
• a critical parameter and can be controlled by the designer
by varying the W/L ratio
14
Current Drive Capability
Gate
L
poly
Source Drain
oxide
n channel n
Diffusion Diffusion
p substrate
• Therefore for a given process technology
– Designer can control the performance of a circuit by specifying W and L
for each of the transistors utilised in the circuit.
• In general a large value for is preferred.
– improved drive capability
– W >> L
15
Minimum Feature Length
• However, a limit to how short L can be made.
• In general can regard the degree to which L can be made
short as the limit of the process technology in terms of the
resulting performance.
• Related to the commonly termed minimum feature
length that can be defined through photolithography.
– Currently 0.25micron (.25mm)
16
W >> L
Gate
L
poly
Source Drain
oxide
n channel n
Diffusion Diffusion
p substrate
• However associated disadvantages with W >> L
– More silicon area is used
– More power dissipated
• Tradeoff:
• Performance : SiO2 Area & Power
17
Resistors
Gate
L
• When electrons flow in the channel Source
poly
Drain
– they move length of the channel L
oxide
n channel n
Diffusion Diffusion
p substrate
• Conduction in channel resembles conduction in any resistive area.
• Another advantage of MOS devices is that they can be used not
only as a transistor but also as a resistor
– Resistor obtained by permanently biasing the Gate for conduction.
– Ratio of the Source-Drain voltage to channel current determines
value of resistance.
– Different resistor values may be constructed during manufacturing
by fixing L and W of the MOS device.
18
CMOS
• Complementary MOS Technology depends on
using both N-Type and P-Type devices on the
same chip.
19
