MODULE-3:

Data-Processing Circuits:Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD-to-Decimal Decoders, Seven-segment

Decoders,Encoders, EX-OR gates, Parity Generators and Checkers, Magnitude comparators (1 and 2 bit), Design of multiple
output circuits using PLDs.HDL Implementation of Data Processing Circuits

MULTIPLEXER
• It is a digital circuit with many inputs but only 1 output. By applying control-signals, we can steer any input to output.
• Thus, it is also called a data-selector and control inputs are termed select inputs (Figure:).
4:1 Multiplexer
• Depending on control inputs A and B, one of the 4 inputs D0 to D3 is steered to output Y.
• The logic equation of the circuit (Fig c) gives a SOP representation.
• Here, each AND gate generates a minterm which are finally summed by OR gate.
Y=A'B'D0+A'BD1+AB'D2+ABD3
If A=0, B=0; Y=0'0'D0+0'0D1+00'D2+ABD3
Y=1.1.D0+0+0+0 = D0
• In other words, for AB=00, the first AND gate to which D0 is connected remains active and equal to D0 and all
other AND gate are inactive with output held at logic 0. If D0=0, Y=0 and if D0=1, Y=1.
• Similarly, for AB=01, second AND gate will be active and all other AND gates remain inactive. Thus, output Y=D1.

Figure a)Multiplexer block diagram b)4:1 multiplexer truth table c)logic circuit

Logical expression of 8:1 mux, Y=A'B'C' D0 +A'B'C D1+A'BC'D2+ A'BCD3+ AB'C'D4+ AB'CD5+ ABC'D6+ ABCD7
For Eg, if ABC = 110, Y = D6
16:1 Multiplexer:

Logical expression of 16:1 mux,

Y=A'B'C'D' D0 +A'B'C'D D1+A'B'CD' D2+ A'B'CD D3+ A'BC'D' D4+ …………………+ ABCD' D14 + ABCD D15
For eg, if ABCD = 1111, Y = D15.
74150
• The 74150 is a 16-to-1 TTL multiplexer.
• Pin 9 is for the STROBE (an input signal) that disables or enables the multiplexer.
• A low strobe enables the multiplexer, so that output Y equals the complement of the input data bit:
Y=D'n where n is the decimal equivalent of ABCD.for eg, n=1, Y=D' 1
• On the other hand, a high strobe disables the multiplexer and forces the output into the high state. With a high
strobe, the value of ABCD doesn't matter.
MULTIPLEXER LOGIC
• Two standard methods for implementing a truth table are SOP and POS. The third method is the multiplexer solution. For
example to use a 74150 to implement Table , complement each Y output to get the corresponding data input.(note :output
is complemented if we use IC 74150)
•Following figure shows the truth table & implementation using MUX 74150.Output of this IC is a complement of the
data.ie, Y=D'n. So the terms whose output is 0(D1,D6,D7) in the table is connected to +5V.remaining connected to GND
• D0 is grounded, D1 is connected to +5V, D2 is grounded and so forth (Figure ).
When ABCD=0000, D0 is the selected input. Since D0 is low, Y is high.
When ABCD=0001, D1 is the selected input. Since D1 is high, Y is low.
• When the STROBE is low mux is enabled. Because of this, the STROBE is called an activelow signal; it causes
something to happen when it is low rather than when it is high.
Table Figure :Using a 74150 for multiplexer logic

Why Multiplexer is called Universal Logic Circuit?

• Because a 2n to 1 multiplexer can be used as a design solution for any 'n' variable truth table.
• 4 variables are given in table.So,16 : 1 mux is required.But it can be implemented using 8:1 mux using this method.
•Let's consider A, B and C variables to be fed as select inputs. The fourth variable D then has to be present as data
input(any one of A,B,C & D can be considered as data input). Here, EVM method can be used to convert 4-variable truth
into 3 variable truth table

Table : Four variable truth table Table : Three variable truth table Fig: realization using 8:1 mux

NIBBLE MULTIPLEXERS
• Sometimes, we want to select 1 of two input nibbles. In this case, we can use a nibble multiplexer.
• The control signal labeled SELECT determines which input nibble is transmitted to output (Fig:).
When SELECT=low, the four NAND gates on the left are activated. Therefore Y3Y2Y1Y0=A3A2A1A0
When SELECT=high, the four NAND gates on the right are activated. Therefore Y3Y2Y1Y0=B3B2B1B0
 Fig: Nibble Multiplexers
DEMULTIPLEXER
• It is a digital circuit with 1 input and many outputs (Fig).
• By applying control signals, we can steer the input signal to one of the output lines.The logical expression of Fig b. is
Yo=A'D , Y1 = AD

Fig: a)Demultiplexer block diagram b)Logic circuit of 1:2 demultiplexer

1:16 Demultiplexer
• The input data bit (D) is transmitted to the data bit of output lines. The selection of output lines depends on the value of
ABCD, the control input.
• When ABCD=0000, the upper AND gate is enabled while other AND gates are disabled. Therefore, data bit D is
transmitted only to the Y0 output, giving Y0=D. If D=low, Y0=low. If D=high, Y0=high.
• If ABCD=1111, all gates are disabled except the bottom AND gate. Then, D is transmitted only to the Y15 output and
Y15=D.

Figure : 1-to-16 demultiplexer

DECODERS
• It is a multiple-input, multiple-output logic circuit which converts coded inputs into coded outputs, where the
input and output codes are different (Figure: ).
• It is similar to a demultiplexer with one exception: there is no data input. The only inputs are the control bits.
1-of-16 Decoder:
• 1-of-16 decoder is called so because only 1 of the 16 output lines is high.
• For instance, when ABCD=0001, only the Y1 AND gate has all inputs high, therefore only the Y1 output is high.
IfABCD=0100, only the Y4 AND gate has all inputs high, as a result Y4=high. If we check the other ABCD possibilities
(0000 to 1111 ), it is understood that the subscript of the high output always equals the decimal equivalent of ABCD. For
this reason, the circuit is sometimes called a binary-to~ decimal decoder. Because it has 4 input lines and 16 output lines,
the circuit is also known as a 4-line to 16-line decoder
The 74154 is called a decoder-demultiplexer, because it can be used either as a decoder or as a demultiplexer.(make DATA
and STROBE grounded for decoder connections.)

Figure : 1-of-16 decoder

BCD-TO-DECIMAL DECODERS

BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit in a decimal number by its nibble
equivalent. For instance, decimal number 429 is changed to its BCD form as follows:

429= 0100 0010 1001

Some early computers processed BCD numbers. This means that the decimal numbers were changed into BCD numbers,
which the computer then added, subtracted, etc. The final answer was converted from BCD back to decimal numbers. Here
is an example of how to convert from the BCD form back to the decimal number:

0101 0111 1000 =578

So, 578 is the decimal equivalent of010I 0111 1000.(Note:ice that BCD digits are from 0000 to 1001. All combinations
above this (1010 to 1111) cannot exist in the BCD code because the highest decimal digit being coded is 9.)

The circuit shown in fig is called a l-of-10 decoder because only 1 of the 10 output lines is high. For instance, when ABCD
is 0011, only the Y3 AND gate has all high inputs; therefore, only the Y3 output is high, If ABCD changes to 1000, only
the Y8 AND gate has all high inputs; as a result, only the Y8 output goes high. If thececk the other ABCD possibilities
(0000 to 1001 ), you will find that the subscript of the high output always equals the decimal equivalent of the input BCD
digit. For this reason, the circuit is also called a BCD-to-decimal converter.
Typically, decoder will not be built with separate inverters and AND gates. Instead, TTL IC like the 7445 of Fig. is used.
Pin 16 connects to the supply voltage V cc and pin 8 is grounded. Pins 12 to 15 are for the BCD input (ABCD), while pins
I to 7 and 9 to 11 are for the outputs. In this IC, the active output line is in the low state. All other output lines are in the
high state, as shown in Table. Notice that an invalid BCD input (1010 to 1111) forces all output lines into the high state.
7-Segment Decoders:

A LED emits radiation when forward-biased. Because free electrons recombine with holes near the junction. As the free
electrons fall from a higher energy level to a lower one, they give up energy in the form of heat and light. By using
elements like gallium, arsenic, and phosphorus, LEDs can be manufactured, that emit red, green, yellow, blue, orange and
infrared (invisible) light. LEDs are useful in test instruments, pocket calculators, etc.

Seven-Segment Indicator

Figure shows a seven-segment indicator, i.e. seven LEDs labeled a through g. By forward-biasing different LEDs, we can
display the digits O through 9 (see Fig. ). For instance, to display a 0, we need to light up segments a, b, c, d, e, and f. To
light up a 5, we need segments a, c, d,f, and g. Seven-segment indicators may be the common-anode type where all anodes
are connected together (Fig.a) or the common-cathode type where all cathodes are connected together (Fig.b). With the
common anode type, current limiting resistor are connected between each LED and ground. The size of this resistor
determines how much current flows through the LED. The typical LED current is between I and 50 mA. The common-
cathode type of Fig.uses a current-limiting resistor between each LED and +Vee·

a.Common-anode type, (b) Common-cathode type

The 7446

A seven-segment decoder-driver is an IC decoder that can be used to drive a seven-segment indicator. There are two types
of decoder-drivers, corresponding to the common-anode and common-cathode indicators. Each decoder-driver has 4 input
pins (the BCD input) and 7 output pins (the a through g segments). Figure a shows a 7446 driving a common-anode
indicator. Logic circuits inside the 7446 convert the BCD input to the required output. For instance, if the BCD input is
0111, the internal logic (not shown) of the 7446 will force LEDs a, b, and c to conduct. As a result, digit 7 will appear on
the seven-segment indicator. The current-limiting resistors between the seven-segment indicator and the 7446 limits the
current in each segment to a safe value between I and 50 mA, depending on how bright the display needs to be.

The 7448
Figure b is the alternative decoding approach. Here, a 7448 drives a common-cathode indicator. Again,internal logic
converts the BCD input to the required output. For example, when a BCD input of 0I00 is used,the internal logic forces
LEDs b, c,f, and g to conduct. The seven-segment indicator then displays a 4. Unlike the 7446 that requires external
current-limiting resistors, the 7448 has its o,vn current-limiting resistors on the chip.
 7446 decoder-driver (common anode) 7448 decoder-driver(common cathode)

ENCODERS
• It converts an active input signal into a coded signal.
• There are ‘n’ input lines, only one of which is active.
• Internal logic within the encoder converts this active input to a coded binary output with ‘m’ bits.
Decimal to BCD Encoders
• The switches are push-button switches like those of a pocket calculator (Figure: 4.24).
• When button 3 is pressed, the C and D OR gates have high inputs, therefore the output is
ABCD=0011
If button 5 is pressed, output ABCD=0101
If button 9 is pressed, output ABCD=1001

Fig: Encoders Figure : Decimal-to-BCD encoder

The priority encoder IC74147:

•In the diagram X1 to X9 is decimal input. ABCD is output. Bubbles indicate active low inputs and outputs. When all
inputs are high the o/p are high. When X9 is low ,the ABCD o/p is LHHL. when X8 is the only low, ABCD is LHHH.
(Continue like this to analyse truth table.). The decimal equivalent of eight is 1000.But as the o/p are active low, o/p for X8
is 0111 ie LHHH.
 •IC74147 is called as priority encoder because it gives priority to the highest order input.If all inputs X1 through X9 are
low, the highest of these X9,is encoded to get an o/p of LHHL. ie,X9 has the highest priority over all others.
•If X8 is low and X9 is high then x8 has highest priority. So highest active low from X9 to X0 has priority and will
control the encoding.

EXCLUSIVE OR GATES
• This has a high output only when an odd number of inputs is high (Figure:).
• The upper AND gate forms the product A'B, while the lower one produces AB'. Therefore, the output of the OR
gate is Y=A'B+AB'
• This gate always produces an output 1 only when n-bit input has an odd number of 1s (Table).

Fig: Exclusive OR gate Table: Two input Exclusive OR gate Fig: Logic symbol

PARITY GENERATORS AND CHECKERS

• Even parity means an n-bit input has an even number of 1s. For e.g. 110011 has even parity because it contains four 1s.
• Odd parity means an n-bit input has an odd number of 1s. For e.g. 110001 have odd parity because it contains three 1s.
• The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks
the parity in the receiver is called a parity checker.
Parity Checker
• XOR gates can be used for checking the parity of a binary number because they produce an output 1 when the
input has an odd number of 1s. Therefore, an even parity input to an exclusive OR gate produces a low output,
while an odd parity input produces a high output (Figure: ).
Exclusive OR gate with 16 inputs Fig: Odd parity generator
Parity Generation
• In a computer, a binary number may represent an instruction that tells the computer to add, subtract etc. In this
case, an extra bit is added to the original binary number to produce a new binary number with even or odd parity (Fig).
• Suppose X7X6X5X4 X3X2X1X0=0100 0001.Then, the number has even parity, which means the XOR gate produces
an output 0. Because of the inverter X8=1 and the final 9-bit output is 1 0100 0001
• If X7X6X5X4 X3X2X1X0=0110 0001. Now, this has odd parity which means, the XOR gate produces an output 1.
But the inverter produces a 0, so that the final 9-bit output is 0 0110 0001. Again, the final output has odd parity.
• If the 8-bit input has even parity, a 1 comes out of the inverter to produce a final output with odd parity. On the
other hand, if the 8-bit input has odd parity, a 0 comes out of the inverter, and the final 9-bit output again has
odd parity.

What is the Practical Application of Parity Generation and Checking?

• Because of transient, noise and other disturbance paths, 1-bit errors sometimes occur when binary data is transmitted over
telephone lines or other communication paths.
• One way to check for errors is using odd parity generator at the transmitter and an odd-parity checker at the receiver.
• If no 1-bit errors occur in transmission, the received data will have odd parity. But if the transmitted bits is changed by
noise or any other disturbance, the received data will have even parity.

MAGNITUDE COMPARATOR
• It compares two n-bit binary numbers, say X and Y and activates one of these 3 outputs: X=Y, X>Y and X<Y(Fig).
• The logic equations for the outputs can be written as follows, where G, L, E stand for greater than, less than and
equal to respectively.
1. (A>B): G=AB' 2.(A<B):L=A'B 3.(A=B):E=A'B'+AB=(AB'+A'B)'=(G+L)'
Fig:a)Block diagram of magnitude comparator b)Circuit for 1-bit comparator.

Input Output
X Y X>Y X=Y X<Y
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
c)Truth table

•The same concept can be extended for n-bit comparator.

•Design of 2 bit comparator: Consider 2 bit numbers, X1X0, Y1Y0
The bit wise greater than terms are (G) : G1 = X1 Y1' , G1 = X0 Y0'
The bit wise less than terms are (L) : L 1 = X1' Y1 , L0 = X0' Y0
The bit wise equality term are (E) : E1 = (G1+ L1 ) ' , E0 = (G0+ L0 ) '
From above definitions,2 bit comparator output
(X=Y) = E1 E0 , (X>Y) = G1 + E1 G0 , (X<Y) = L1 + E1 L

The logic followed in arriving this equations is this : X = Y when both the bits are equal. X >Y if MSB of X is higher (G1
= 1) than that of Y. if MSB is equal given by E1 = 1 ,then LSB of X and Y is checked and if found higher (G0 =1) the
condition X > Y is fulfilled . similar logic gives us the X < Y term.
Thus, For any two n bit numbers X : Xn-1 Xn-2 ….X0 and Y:Yn-1 Yn-2 …Y0
We can write (X =Y) = En-1 En-2 …..E0
(X>Y) = Gn-1 + En-1 Gn-2 +…..
(X<Y) = Ln-1 + En-1 Ln-2+…..

PROGRAMMABLE LOGIC DEVICES (PLD):PAL,PLA and ROM are called as PLDs.

PROM:Fixed AND array and Programmable OR array

PROGRAMMABLE ARRAY LOGIC (PAL)

• It is a programmable array of logic gates on a single chip.PAL s are another design solution like SOP,POS and MUX
logic. This is different from a PROM because it has a programmable AND array and a fixed OR array.

•the ‘X’ on i/p side are fusible links.Solid dots ‘•’on the o/p side are fixed connection.

• PROM programmer can burn in the desired fundamental products, which are then ORed by the fixed o/p connections.
Figure: Structure of PAL
PROGRAMMABLE LOGIC ARRAYS (PLA)
• In this, the input signals are presented to an array of AND gates while the outputs are taken from an array of OR gates.
• In a PROM, the input AND gate array is fixed and cannot be altered, while the output OR gate array is fusible linked, and
can thus be programmed. In PAL, the output OR gate array is fixed while the input AND gate array is fusible linked and
thus programmable.
• The PLA is much more versatile than the PROM or the PAL, since both its AND gate array and its OR gate are fusible
linked and programmable.
• PLA is also more complicated to utilize since the number of fusible links are doubled.

Figure : Structure of PLA

Example 1: Suppose we want to generate the following boolean functions. Show how we can program a PLA.
f( a,b,c) = a’b’ + abc , g(a,b,c) = a’b’c’ + ab + bc , h(a,b,c) = c
Figure : Example of programming a PLA

Example 2: Show how we can use a PLA to recognize each of the 10 decimal digits represented in binary form and to
correctly drive a 7-segment display.If ‘0’ has to be displayed means,then except the ‘g’ segment remaining should glow.In
the same way other decimal digits can be displayed

Figure : 7-segment decoder using PLA

HDL Implementation
2:1 MUX
module mux2tol (A,DO,Dl,Y);
input A, DO, Dl;
output Y;
reg Y;
always@ (A or DO or Dl)
if {A==l) Y=Dl;
else Y=DO;
endmodule

2:1 mux using case statement

module mux2tol(A,D0,Dl,Y);
input A, DO, Dl;
output Y;
reg Y;
always@ (A or DO or Dl)
case (A)
0 : Y=DO;
1 : Y=Dl;
endcase
endmodule

Design a 4 to 1 multiplexer using conditional assign and case statements.

module mux4to1 (A,B,DO,Dl,D2,D3,Y);
input A,B,DO,Dl,D2,D3;
output Y;
assign Y = A ? { B ? D3 D1 : DO);
endmodule

module mux4to1 (A,B,DO,Dl,D2,D3,Y);

input A,B,DO,Dl,D2,D3;
output Y;
reg Y;
always@ (A or DO or Dl or D2 or D3)
case (A)
0 : Y=DO;
1 : Y=Dl;
2 : Y=D2;
3 : Y=D3;
endcase
endmodule

1:4 Demux
module demuxlto4(S,D,Y);
input (1:0J S;
input
output f3 : 0] Y;
reg [3:0] Y;
always @ (S or D)
case({D,S})
3'b100 :Y= 4’b0001;
3'b101 :Y= 4’b0010;
3'b110 :Y= 4’b0100;
3'b111 :Y= 4’b1000;
3'b100 :Y= 4’b0001;
default: Y= 4'b0000;
end.case
endmodule